Re: [PATCH v3 2/2] arm64: dts: qcom: qcm2290: Add CCI node

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 4/7/25 4:56 PM, Loic Poulain wrote:
> Hi Bryan,
> 
> 
> On Fri, Apr 4, 2025 at 2:10 PM Bryan O'Donoghue
> <bryan.odonoghue@linaro.org> wrote:
>>
>> On 03/04/2025 11:22, Loic Poulain wrote:
>>> Add Camera Control Interface (CCI), supporting two I2C masters.
>>>
>>> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
>>> ---
>>>   v2: Reorder commits; Update dts properties order and style
>>>   v3: No change for this patch
>>>
>>>   arch/arm64/boot/dts/qcom/qcm2290.dtsi | 50 +++++++++++++++++++++++++++
>>>   1 file changed, 50 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/qcm2290.dtsi b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> index 7fb5de92bc4c..43fcb4f40a8c 100644
>>> --- a/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/qcm2290.dtsi
>>> @@ -557,6 +557,20 @@ qup_uart4_default: qup-uart4-default-state {
>>>                               bias-disable;
>>>                       };
>>>
>>> +                     cci0_default: cci0-default-state {
>>> +                             pins = "gpio22", "gpio23";
>>> +                             function = "cci_i2c";
>>> +                             drive-strength = <2>;
>>> +                             bias-disable;
>>> +                     };
>>> +
>>> +                     cci1_default: cci1-default-state {
>>> +                             pins = "gpio29", "gpio30";
>>> +                             function = "cci_i2c";
>>> +                             drive-strength = <2>;
>>> +                             bias-disable;
>>> +                     };
>>> +
>>>                       sdc1_state_on: sdc1-on-state {
>>>                               clk-pins {
>>>                                       pins = "sdc1_clk";
>>> @@ -1603,6 +1617,42 @@ adreno_smmu: iommu@59a0000 {
>>>                       #iommu-cells = <2>;
>>>               };
>>>
>>> +             cci: cci@5c1b000 {
>>> +                     compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci";
>>> +                     reg = <0x0 0x5c1b000 0x0 0x1000>;
>>> +
>>> +                     interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
>>> +
>>> +                     clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>;
>>> +                     clock-names = "camss_top_ahb", "cci";
>>
>> do you not need an axi clock GCC_CAMSS_AXI_CLK ?
> 
> AFAIU AXI is not involved for CCI.

I'm not able to infer that from statically provided infromation, try
forcefully shutting the clock down (both the branch and _SRC) and
poking at the CCI

Konrad