* [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC
@ 2026-04-27 1:32 Jia Wang
2026-04-27 1:32 ` [PATCH v4 1/3] riscv: add UltraRISC SoC family Kconfig support Jia Wang
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Jia Wang @ 2026-04-27 1:32 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han,
Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley
Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang,
Conor Dooley, Krzysztof Kozlowski
This patch series adds PCIe controller support for the UltraRISC DP1000 SoC.
The DP1000 is an 8-core 64-bit RISC-V SoC based on UltraRISC CP100 cores,
supporting RV64GCBHX ISA with Hardware Virtualization and RISC-V H(v1.0)
Extension.
The PCIe controller is based on Synopsys DesignWare PCIe IP.
This series adds:
- Patch 1 adds the basic SoC family Kconfig support for UltraRISC platforms.
- Patch 2 adds the device tree bindings documentation for the PCIe controller.
- Patch 3 introduces the PCIe host controller driver.
The patches have been tested on UltraRISC DP1000 development board with
various PCIe devices including NVMe SSDs and network cards, verifying
link establishment, enumeration, and basic data transfer.
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
---
Changes in v4:
- Patch 3:
* Drop the wrapper struct and store struct dw_pcie directly as driver data.
* Drop the unused platform_get_irq() call.
* Move the extra DBI programming out of .start_link() into the host init
callback (and skip it when the link is already up), keeping .start_link()
limited to enabling LTSSM.
* Replace the hard-coded Completion Timeout value with a named macro.
* Do not force max_link_speed; keep the hardware default.
* Drop unused header includes.
- Link to v3: https://patch.msgid.link/20260415-ultrarisc-pcie-v3-0-73f06e972616@ultrarisc.com
Changes in v3:
- Fold the MAINTAINERS update into the binding/driver patches and drop
the standalone MAINTAINERS patch from v2.
- Patch 1:
* Trim DP1000-specific ISA/feature details from the help text.
- Patch 2:
* Simplify the description formatting and remove the redundant.
* Drop the max-link-speed property from the binding.
* Remove the redundant interrupts description line.
* Clean up the example.
- Patch 3:
* Drop unused regmap include.
* Drop the unused irq_mask[] field.
* Set pci->max_link_speed = 4 based on the fixed hardware capability.
- Link to v2: https://patch.msgid.link/20260407-ultrarisc-pcie-v2-0-2aa2a19a7fb3@ultrarisc.com
Changes in v2:
- Rebased onto v7.0-rc7.
- Patch 1:
* Removed unnecessary 'depends' line.
* Fixed help text indentation.
- Patch 2:
* No changes.
- Patch 3:
* Updated $ref to use 'snps,dw-pcie.yaml' as the base schema.
* Add interrupts/interrupt-names (MSI + INTx).
* Drop properties covered by generic DWC/PCI host bindings;
update example accordingly.
* Verified the schema passes 'make dt_binding_check' and 'yamllint'.
- Patch 4:
* Update commit message.
* Kconfig: switch PCIE_ULTRARISC to tristate; simplify help text.
* Convert suspend/resume to dev_pm_ops and called
`dw_pcie_suspend_noirq()` / `dw_pcie_resume_noirq()`.
* Use FIELD_MODIFY(); adjust DWC header macros/comments.
* Added empty `.pme_turn_off()` callback for DP1000 limitation.
* Renamed link callback to `start_link`.
* Switched to `module_platform_driver()`.
* Formatting cleanups (headers order, spacing, variable naming,
function names)
- Link to v1: https://patch.msgid.link/20260316-ultrarisc-pcie-v1-0-ef2946ede698@ultrarisc.com
---
Jia Wang (2):
riscv: add UltraRISC SoC family Kconfig support
dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller
Xincheng Zhang (1):
PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver
.../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 +++++++++++
MAINTAINERS | 8 +
arch/riscv/Kconfig.socs | 6 +
drivers/pci/controller/dwc/Kconfig | 12 ++
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-designware.h | 22 +++
drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++++
7 files changed, 317 insertions(+)
---
base-commit: e774d5f1bc27a85f858bce7688509e866f8e8a4e
change-id: 20260310-ultrarisc-pcie-494998763399
Best regards,
--
Jia Wang <wangjia@ultrarisc.com>
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v4 1/3] riscv: add UltraRISC SoC family Kconfig support 2026-04-27 1:32 [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC Jia Wang @ 2026-04-27 1:32 ` Jia Wang 2026-04-27 1:32 ` [PATCH v4 2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller Jia Wang ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Jia Wang @ 2026-04-27 1:32 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han, Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang, Conor Dooley The first SoC in the UltraRISC series is UR-DP1000, containing octa UltraRISC CP100 cores. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index d621b85dd63b..0b4d06a7b4bf 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -84,6 +84,12 @@ config ARCH_THEAD help This enables support for the RISC-V based T-HEAD SoCs. +config ARCH_ULTRARISC + bool "UltraRISC RISC-V SoCs" + help + This enables support for UltraRISC SoC platform hardware, + including boards based on the UR-DP1000. + config ARCH_VIRT bool "QEMU Virt Machine" select POWER_RESET -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller 2026-04-27 1:32 [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC Jia Wang 2026-04-27 1:32 ` [PATCH v4 1/3] riscv: add UltraRISC SoC family Kconfig support Jia Wang @ 2026-04-27 1:32 ` Jia Wang 2026-04-27 1:32 ` [PATCH v4 3/3] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver Jia Wang 2026-05-11 8:31 ` (subset) [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC Manivannan Sadhasivam 3 siblings, 0 replies; 6+ messages in thread From: Jia Wang @ 2026-04-27 1:32 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han, Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang, Krzysztof Kozlowski Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. Signed-off-by: Jia Wang <wangjia@ultrarisc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> --- .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 ++++++++++++++++++++++ MAINTAINERS | 7 ++ 2 files changed, 100 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml new file mode 100644 index 000000000000..512b935bf5d1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 PCIe Host Controller + +description: + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. + +maintainers: + - Xincheng Zhang <zhangxincheng@ultrarisc.com> + - Jia Wang <wangjia@ultrarisc.com> + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: ultrarisc,dp1000-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: config + + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [4, 16] + description: Number of lanes to use. + + interrupts: + items: + - description: MSI interrupt + - description: Legacy INTA interrupt + - description: Legacy INTB interrupt + - description: Legacy INTC interrupt + - description: Legacy INTD interrupt + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@21000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x21000000 0x0 0x01000000>, + <0x0 0x4fff0000 0x0 0x00010000>; + reg-names = "dbi", "config"; + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <16>; + interrupt-parent = <&plic>; + interrupts = <43>, <44>, <45>, <46>, <47>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d238590a31f2..818685933541 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20583,6 +20583,13 @@ S: Maintained F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml F: drivers/pci/controller/plda/pcie-starfive.c +PCIE DRIVER FOR ULTRARISC DP1000 +M: Xincheng Zhang <zhangxincheng@ultrarisc.com> +M: Jia Wang <wangjia@ultrarisc.com> +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml + PCIE ENDPOINT DRIVER FOR QUALCOMM M: Manivannan Sadhasivam <mani@kernel.org> L: linux-pci@vger.kernel.org -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 3/3] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver 2026-04-27 1:32 [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC Jia Wang 2026-04-27 1:32 ` [PATCH v4 1/3] riscv: add UltraRISC SoC family Kconfig support Jia Wang 2026-04-27 1:32 ` [PATCH v4 2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller Jia Wang @ 2026-04-27 1:32 ` Jia Wang 2026-05-11 6:12 ` Jia Wang 2026-05-11 8:31 ` (subset) [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC Manivannan Sadhasivam 3 siblings, 1 reply; 6+ messages in thread From: Jia Wang @ 2026-04-27 1:32 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han, Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Jia Wang From: Xincheng Zhang <zhangxincheng@ultrarisc.com> Add DP1000 SoC PCIe Root Complex driver. The controller only supports 32-bit aligned configuration space accesses. Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com> Signed-off-by: Jia Wang <wangjia@ultrarisc.com> --- MAINTAINERS | 1 + drivers/pci/controller/dwc/Kconfig | 12 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-designware.h | 22 ++++ drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++++++++++ 5 files changed, 211 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 818685933541..16203b804c16 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20589,6 +20589,7 @@ M: Jia Wang <wangjia@ultrarisc.com> L: linux-pci@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +F: drivers/pci/controller/dwc/pcie-ultrarisc.c PCIE ENDPOINT DRIVER FOR QUALCOMM M: Manivannan Sadhasivam <mani@kernel.org> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index d0aa031397fa..06f7d98259cd 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -548,4 +548,16 @@ config PCIE_VISCONTI_HOST Say Y here if you want PCIe controller support on Toshiba Visconti SoC. This driver supports TMPV7708 SoC. +config PCIE_ULTRARISC + tristate "UltraRISC PCIe host controller" + depends on ARCH_ULTRARISC || COMPILE_TEST + select PCIE_DW_HOST + select PCI_MSI + default y if ARCH_ULTRARISC + help + Enables support for the PCIe controller in the UltraRISC SoC. + This driver supports UR-DP1000 SoC. + By default, this symbol is enabled when ARCH_ULTRARISC is active, + requiring no further configuration on that platform. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 67ba59c02038..884c46b78e01 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o +obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ae6389dd9caa..88dcb0e7943a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -69,6 +69,8 @@ /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_FORCE 0x708 +/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ +#define PORT_LINK_NUM_MASK GENMASK(7, 0) #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) #define PCIE_PORT_AFR 0x70C @@ -96,6 +98,26 @@ #define PCIE_PORT_LANE_SKEW 0x714 #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) +/* + * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number + * Register. + * This register holds the ack frequency, latency, replay, fast link + * scaling timers, and max function number values. + * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. + * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us). + * When the LTSSM is in Config or L12 Entry State, 1ms + * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. + * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) + * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) + * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) + */ +#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 +#define PORT_FLT_SF_MASK GENMASK(30, 29) +#define PORT_FLT_SF_VAL_1024 0x0 +#define PORT_FLT_SF_VAL_256 0x1 +#define PORT_FLT_SF_VAL_64 0x2 +#define PORT_FLT_SF_VAL_16 0x3 + #define PCIE_PORT_DEBUG0 0x728 #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f #define PORT_LOGIC_LTSSM_STATE_L0 0x11 diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c new file mode 100644 index 000000000000..7326bd446590 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DWC PCIe RC driver for UltraRISC SoCs + * + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/resource.h> + +#include "pcie-designware.h" + +#define PCIE_CUS_CORE 0x400000 + +#define LTSSM_ENABLE BIT(7) +#define FAST_LINK_MODE BIT(12) +#define HOLD_PHY_RST BIT(14) +#define L1SUB_DISABLE BIT(15) + +#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 + +static struct pci_ops ultrarisc_pci_ops = { + .map_bus = dw_pcie_own_conf_map_bus, + .read = pci_generic_config_read32, + .write = pci_generic_config_write32, +}; + +static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct pci_host_bridge *bridge = pp->bridge; + u8 cap_exp; + u32 val; + + bridge->ops = &ultrarisc_pci_ops; + + if (dw_pcie_link_up(pci)) + return 0; + + val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); + val &= ~FAST_LINK_MODE; + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); + + val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); + FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); + dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); + + cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); + FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); + + val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); + FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); + dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); + + val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); + FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, + ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); + + val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); + val &= ~(HOLD_PHY_RST | L1SUB_DISABLE); + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); + + return 0; +} + +static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + /* + * DP1000 does not support sending PME_Turn_Off from the RC. + * Keep this callback empty to skip the generic MSG TLP path. + */ +} + +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { + .init = ultrarisc_pcie_host_init, + .pme_turn_off = ultrarisc_pcie_pme_turn_off, +}; + +static int ultrarisc_pcie_start_link(struct dw_pcie *pci) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); + val |= LTSSM_ENABLE; + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); + + return 0; +} + +static const struct dw_pcie_ops dw_pcie_ops = { + .start_link = ultrarisc_pcie_start_link, +}; + +static int ultrarisc_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dw_pcie_rp *pp; + struct dw_pcie *pci; + int ret; + + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev = dev; + pci->ops = &dw_pcie_ops; + + /* Set a default value suitable for at most 16 in and 16 out windows */ + pci->atu_size = SZ_8K; + + pp = &pci->pp; + + platform_set_drvdata(pdev, pci); + + pp->num_vectors = MAX_MSI_IRQS; + /* No L2/L3 Ready indication is available on this platform. */ + pp->skip_l23_ready = true; + pp->ops = &ultrarisc_pcie_host_ops; + + ret = dw_pcie_host_init(pp); + if (ret) { + dev_err(dev, "Failed to initialize host\n"); + return ret; + } + + return 0; +} + +static int ultrarisc_pcie_suspend_noirq(struct device *dev) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + + return dw_pcie_suspend_noirq(pci); +} + +static int ultrarisc_pcie_resume_noirq(struct device *dev) +{ + struct dw_pcie *pci = dev_get_drvdata(dev); + + return dw_pcie_resume_noirq(pci); +} + +static const struct dev_pm_ops ultrarisc_pcie_pm_ops = { + NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, + ultrarisc_pcie_resume_noirq) +}; + +static const struct of_device_id ultrarisc_pcie_of_match[] = { + { + .compatible = "ultrarisc,dp1000-pcie", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); + +static struct platform_driver ultrarisc_pcie_driver = { + .driver = { + .name = "ultrarisc-pcie", + .of_match_table = ultrarisc_pcie_of_match, + .suppress_bind_attrs = true, + .pm = &ultrarisc_pcie_pm_ops, + }, + .probe = ultrarisc_pcie_probe, +}; +module_platform_driver(ultrarisc_pcie_driver); + +MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); +MODULE_LICENSE("GPL"); -- 2.34.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 3/3] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver 2026-04-27 1:32 ` [PATCH v4 3/3] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver Jia Wang @ 2026-05-11 6:12 ` Jia Wang 0 siblings, 0 replies; 6+ messages in thread From: Jia Wang @ 2026-05-11 6:12 UTC (permalink / raw) To: Jia Wang Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Lorenzo Pieralisi, Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Jingoo Han, Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley, linux-riscv, linux-kernel, linux-pci, devicetree On 2026-04-27 09:32 +0800, Jia Wang wrote: > From: Xincheng Zhang <zhangxincheng@ultrarisc.com> > > Add DP1000 SoC PCIe Root Complex driver. > > The controller only supports 32-bit aligned configuration space accesses. > > Signed-off-by: Xincheng Zhang <zhangxincheng@ultrarisc.com> > Signed-off-by: Jia Wang <wangjia@ultrarisc.com> > --- > MAINTAINERS | 1 + > drivers/pci/controller/dwc/Kconfig | 12 ++ > drivers/pci/controller/dwc/Makefile | 1 + > drivers/pci/controller/dwc/pcie-designware.h | 22 ++++ > drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++++++++++ > 5 files changed, 211 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 818685933541..16203b804c16 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -20589,6 +20589,7 @@ M: Jia Wang <wangjia@ultrarisc.com> > L: linux-pci@vger.kernel.org > S: Maintained > F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml > +F: drivers/pci/controller/dwc/pcie-ultrarisc.c > > PCIE ENDPOINT DRIVER FOR QUALCOMM > M: Manivannan Sadhasivam <mani@kernel.org> > diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig > index d0aa031397fa..06f7d98259cd 100644 > --- a/drivers/pci/controller/dwc/Kconfig > +++ b/drivers/pci/controller/dwc/Kconfig > @@ -548,4 +548,16 @@ config PCIE_VISCONTI_HOST > Say Y here if you want PCIe controller support on Toshiba Visconti SoC. > This driver supports TMPV7708 SoC. > > +config PCIE_ULTRARISC > + tristate "UltraRISC PCIe host controller" > + depends on ARCH_ULTRARISC || COMPILE_TEST > + select PCIE_DW_HOST > + select PCI_MSI > + default y if ARCH_ULTRARISC > + help > + Enables support for the PCIe controller in the UltraRISC SoC. > + This driver supports UR-DP1000 SoC. > + By default, this symbol is enabled when ARCH_ULTRARISC is active, > + requiring no further configuration on that platform. > + > endmenu > diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile > index 67ba59c02038..884c46b78e01 100644 > --- a/drivers/pci/controller/dwc/Makefile > +++ b/drivers/pci/controller/dwc/Makefile > @@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o > obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o > obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o > obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o > +obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o > > # The following drivers are for devices that use the generic ACPI > # pci_root.c driver but don't support standard ECAM config access. > diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h > index ae6389dd9caa..88dcb0e7943a 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.h > +++ b/drivers/pci/controller/dwc/pcie-designware.h > @@ -69,6 +69,8 @@ > > /* Synopsys-specific PCIe configuration registers */ > #define PCIE_PORT_FORCE 0x708 > +/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ > +#define PORT_LINK_NUM_MASK GENMASK(7, 0) > #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) > > #define PCIE_PORT_AFR 0x70C > @@ -96,6 +98,26 @@ > #define PCIE_PORT_LANE_SKEW 0x714 > #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) > > +/* > + * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number > + * Register. > + * This register holds the ack frequency, latency, replay, fast link > + * scaling timers, and max function number values. > + * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. > + * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us). > + * When the LTSSM is in Config or L12 Entry State, 1ms > + * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. > + * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) > + * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) > + * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) > + */ > +#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 > +#define PORT_FLT_SF_MASK GENMASK(30, 29) > +#define PORT_FLT_SF_VAL_1024 0x0 > +#define PORT_FLT_SF_VAL_256 0x1 > +#define PORT_FLT_SF_VAL_64 0x2 > +#define PORT_FLT_SF_VAL_16 0x3 > + > #define PCIE_PORT_DEBUG0 0x728 > #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f > #define PORT_LOGIC_LTSSM_STATE_L0 0x11 > diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/controller/dwc/pcie-ultrarisc.c > new file mode 100644 > index 000000000000..7326bd446590 > --- /dev/null > +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c > @@ -0,0 +1,175 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * DWC PCIe RC driver for UltraRISC SoCs > + * > + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. > + */ > + > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/pci.h> > +#include <linux/platform_device.h> > +#include <linux/resource.h> > + > +#include "pcie-designware.h" > + > +#define PCIE_CUS_CORE 0x400000 > + > +#define LTSSM_ENABLE BIT(7) > +#define FAST_LINK_MODE BIT(12) > +#define HOLD_PHY_RST BIT(14) > +#define L1SUB_DISABLE BIT(15) > + > +#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 > + > +static struct pci_ops ultrarisc_pci_ops = { > + .map_bus = dw_pcie_own_conf_map_bus, > + .read = pci_generic_config_read32, > + .write = pci_generic_config_write32, > +}; > + > +static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct pci_host_bridge *bridge = pp->bridge; > + u8 cap_exp; > + u32 val; > + > + bridge->ops = &ultrarisc_pci_ops; > + > + if (dw_pcie_link_up(pci)) > + return 0; > + > + val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); > + val &= ~FAST_LINK_MODE; > + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); > + > + val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); > + FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); > + dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); > + > + cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); > + FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); > + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); > + > + val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); > + FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); > + dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); > + > + val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); > + FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, > + ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); > + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); > + > + val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); > + val &= ~(HOLD_PHY_RST | L1SUB_DISABLE); > + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); > + > + return 0; > +} > + > +static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) > +{ > + /* > + * DP1000 does not support sending PME_Turn_Off from the RC. > + * Keep this callback empty to skip the generic MSG TLP path. > + */ > +} > + > +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = { > + .init = ultrarisc_pcie_host_init, > + .pme_turn_off = ultrarisc_pcie_pme_turn_off, > +}; > + > +static int ultrarisc_pcie_start_link(struct dw_pcie *pci) > +{ > + u32 val; > + > + val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); > + val |= LTSSM_ENABLE; > + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); > + > + return 0; > +} > + > +static const struct dw_pcie_ops dw_pcie_ops = { > + .start_link = ultrarisc_pcie_start_link, > +}; > + > +static int ultrarisc_pcie_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct dw_pcie_rp *pp; > + struct dw_pcie *pci; > + int ret; > + > + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); > + if (!pci) > + return -ENOMEM; > + > + pci->dev = dev; > + pci->ops = &dw_pcie_ops; > + > + /* Set a default value suitable for at most 16 in and 16 out windows */ > + pci->atu_size = SZ_8K; > + > + pp = &pci->pp; > + > + platform_set_drvdata(pdev, pci); > + > + pp->num_vectors = MAX_MSI_IRQS; > + /* No L2/L3 Ready indication is available on this platform. */ > + pp->skip_l23_ready = true; > + pp->ops = &ultrarisc_pcie_host_ops; > + > + ret = dw_pcie_host_init(pp); > + if (ret) { > + dev_err(dev, "Failed to initialize host\n"); > + return ret; > + } > + > + return 0; > +} > + > +static int ultrarisc_pcie_suspend_noirq(struct device *dev) > +{ > + struct dw_pcie *pci = dev_get_drvdata(dev); > + > + return dw_pcie_suspend_noirq(pci); > +} > + > +static int ultrarisc_pcie_resume_noirq(struct device *dev) > +{ > + struct dw_pcie *pci = dev_get_drvdata(dev); > + > + return dw_pcie_resume_noirq(pci); > +} > + > +static const struct dev_pm_ops ultrarisc_pcie_pm_ops = { > + NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, > + ultrarisc_pcie_resume_noirq) > +}; > + > +static const struct of_device_id ultrarisc_pcie_of_match[] = { > + { > + .compatible = "ultrarisc,dp1000-pcie", > + }, > + {}, > +}; > +MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); > + > +static struct platform_driver ultrarisc_pcie_driver = { > + .driver = { > + .name = "ultrarisc-pcie", > + .of_match_table = ultrarisc_pcie_of_match, > + .suppress_bind_attrs = true, > + .pm = &ultrarisc_pcie_pm_ops, > + }, > + .probe = ultrarisc_pcie_probe, > +}; > +module_platform_driver(ultrarisc_pcie_driver); > + > +MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); > +MODULE_LICENSE("GPL"); > > -- > 2.34.1 > > Gentle ping. Best Regards, Jia Wang ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: (subset) [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC 2026-04-27 1:32 [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC Jia Wang ` (2 preceding siblings ...) 2026-04-27 1:32 ` [PATCH v4 3/3] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver Jia Wang @ 2026-05-11 8:31 ` Manivannan Sadhasivam 3 siblings, 0 replies; 6+ messages in thread From: Manivannan Sadhasivam @ 2026-05-11 8:31 UTC (permalink / raw) To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas, Jingoo Han, Xincheng Zhang, Krzysztof Kozlowski, Conor Dooley, Jia Wang Cc: linux-riscv, linux-kernel, linux-pci, devicetree, Conor Dooley, Krzysztof Kozlowski On Mon, 27 Apr 2026 09:32:09 +0800, Jia Wang wrote: > This patch series adds PCIe controller support for the UltraRISC DP1000 SoC. > The DP1000 is an 8-core 64-bit RISC-V SoC based on UltraRISC CP100 cores, > supporting RV64GCBHX ISA with Hardware Virtualization and RISC-V H(v1.0) > Extension. > > The PCIe controller is based on Synopsys DesignWare PCIe IP. > This series adds: > - Patch 1 adds the basic SoC family Kconfig support for UltraRISC platforms. > - Patch 2 adds the device tree bindings documentation for the PCIe controller. > - Patch 3 introduces the PCIe host controller driver. > > [...] Applied, thanks! [2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller commit: 09b78d6ec24624c2f5192dbf0c6e05cad61c529d [3/3] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver commit: 34f9bebe1cf573cf9735a71c1d484b57f65e5314 Best regards, -- Manivannan Sadhasivam <mani@kernel.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-05-11 8:31 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-04-27 1:32 [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC Jia Wang 2026-04-27 1:32 ` [PATCH v4 1/3] riscv: add UltraRISC SoC family Kconfig support Jia Wang 2026-04-27 1:32 ` [PATCH v4 2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller Jia Wang 2026-04-27 1:32 ` [PATCH v4 3/3] PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver Jia Wang 2026-05-11 6:12 ` Jia Wang 2026-05-11 8:31 ` (subset) [PATCH v4 0/3] riscv: Add PCIe support for UltraRISC DP1000 SoC Manivannan Sadhasivam
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