* [PATCH] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map
@ 2026-04-07 20:18 Krzysztof Kozlowski
2026-04-08 10:21 ` Konrad Dybcio
2026-05-12 20:22 ` Bjorn Andersson
0 siblings, 2 replies; 3+ messages in thread
From: Krzysztof Kozlowski @ 2026-04-07 20:18 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-arm-msm, devicetree, linux-kernel
Cc: Krzysztof Kozlowski
Make the complicated interrupt-map property (with multiple '0' entries)
a bit more readable by using known define for GIC_SPI.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur.dtsi | 32 ++++++++++++-------------
arch/arm64/boot/dts/qcom/kaanapali.dtsi | 8 +++----
arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 +++----
arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 +++----
4 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi
index f23cf81ddb77..0a3cf2c62c3e 100644
--- a/arch/arm64/boot/dts/qcom/glymur.dtsi
+++ b/arch/arm64/boot/dts/qcom/glymur.dtsi
@@ -2776,10 +2776,10 @@ pcie4: pci@1bf0000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 0 0 513 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 0 0 514 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 0 0 515 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 0 0 516 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
<&gcc GCC_PCIE_4_CFG_AHB_CLK>,
@@ -2986,10 +2986,10 @@ pcie5: pci@1b40000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 0 0 526 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 0 0 428 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 0 0 429 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
<&gcc GCC_PCIE_5_CFG_AHB_CLK>,
@@ -3252,10 +3252,10 @@ pcie6: pci@1c00000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 0 0 472 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 0 0 473 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 0 0 474 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 0 0 475 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_6_AUX_CLK>,
<&gcc GCC_PCIE_6_CFG_AHB_CLK>,
@@ -3462,10 +3462,10 @@ pcie3b: pci@1b80000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 0 0 831 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 0 0 832 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 0 0 833 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 0 0 834 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
<&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/kaanapali.dtsi b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
index 7cc326aa1a1a..322ebfad6bf7 100644
--- a/arch/arm64/boot/dts/qcom/kaanapali.dtsi
+++ b/arch/arm64/boot/dts/qcom/kaanapali.dtsi
@@ -2313,10 +2313,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
iommu-map = <0 &apps_smmu 0x1400 0x1>,
<0x100 &apps_smmu 0x1401 0x1>;
- interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 0x7>;
#interrupt-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index d41b5c470c48..347706011637 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -955,10 +955,10 @@ pcie0: pcie@1c00000 {
"msi7",
"global";
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>,
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 18fb52c14acd..ae7891c0eddc 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -5202,10 +5202,10 @@ pcie0: pcie@1c00000 {
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
--
2.51.0
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map
2026-04-07 20:18 [PATCH] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map Krzysztof Kozlowski
@ 2026-04-08 10:21 ` Konrad Dybcio
2026-05-12 20:22 ` Bjorn Andersson
1 sibling, 0 replies; 3+ messages in thread
From: Konrad Dybcio @ 2026-04-08 10:21 UTC (permalink / raw)
To: Krzysztof Kozlowski, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree,
linux-kernel
On 4/7/26 10:18 PM, Krzysztof Kozlowski wrote:
> Make the complicated interrupt-map property (with multiple '0' entries)
> a bit more readable by using known define for GIC_SPI.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map
2026-04-07 20:18 [PATCH] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map Krzysztof Kozlowski
2026-04-08 10:21 ` Konrad Dybcio
@ 2026-05-12 20:22 ` Bjorn Andersson
1 sibling, 0 replies; 3+ messages in thread
From: Bjorn Andersson @ 2026-05-12 20:22 UTC (permalink / raw)
To: Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-arm-msm, devicetree, linux-kernel, Krzysztof Kozlowski
On Tue, 07 Apr 2026 22:18:40 +0200, Krzysztof Kozlowski wrote:
> Make the complicated interrupt-map property (with multiple '0' entries)
> a bit more readable by using known define for GIC_SPI.
>
>
Applied, thanks!
[1/1] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map
commit: 08569936a11b8ed20f95783d80d1ba2f4e93fa93
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2026-04-07 20:18 [PATCH] arm64: dts: qcom: Use GIC_SPI macro for interrupt-map Krzysztof Kozlowski
2026-04-08 10:21 ` Konrad Dybcio
2026-05-12 20:22 ` Bjorn Andersson
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