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From: Jia Wang <wangjia@ultrarisc.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Jia Wang <wangjia@ultrarisc.com>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	 Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	 Alexandre Ghiti <alex@ghiti.fr>,
	Daniel Lezcano <daniel.lezcano@kernel.org>,
	 Thomas Gleixner <tglx@kernel.org>,
	 Samuel Holland <samuel.holland@sifive.com>,
	 Anup Patel <anup@brainfault.org>,
	Mark Brown <broonie@kernel.org>,
	 Andi Shyti <andi.shyti@kernel.org>,
	 Mika Westerberg <mika.westerberg@linux.intel.com>,
	 Andrew Lunn <andrew+netdev@lunn.ch>,
	 "David S. Miller" <davem@davemloft.net>,
	Eric Dumazet <edumazet@google.com>,
	 Jakub Kicinski <kuba@kernel.org>,
	Paolo Abeni <pabeni@redhat.com>,
	 Alexandre Torgue <alexandre.torgue@foss.st.com>,
	 Giuseppe Cavallaro <peppe.cavallaro@st.com>,
	 Jose Abreu <joabreu@synopsys.com>,
	 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>,
	 Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>,
	 Paul Walmsley <paul.walmsley@sifive.com>,
	 Palmer Dabbelt <palmer@sifive.com>,
	Conor Dooley <conor@kernel.org>,
	 devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	 linux-kernel@vger.kernel.org, linux-spi@vger.kernel.org,
	 linux-i2c@vger.kernel.org, netdev@vger.kernel.org,
	 dmaengine@vger.kernel.org
Subject: Re: [PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree
Date: Thu, 27 Aug 2026 12:54:53 +0800	[thread overview]
Message-ID: <178780649385.1608658.14465948095163858225.b4-reply@b4> (raw)
In-Reply-To: <db174bcd-3b21-464f-ab56-439d65e2a064@lunn.ch>

On 2026-08-27 04:46 +0200, Andrew Lunn wrote:
> On Thu, Aug 27, 2026 at 10:19:43AM +0800, Jia Wang wrote:
> > On 2026-08-24 15:02 +0200, Andrew Lunn wrote:
> > > > +&ethernet {
> > > > +	phy-handle = <&phy0>;
> > > > +	/*
> > > > +	 * YT8531 RGMII timing on this board requires no PHY internal delays.
> > > 
> > > Please extend this sentence with an explanation why it needs no delay?
> > > 
> > > There are times this is correct, but it is also mostly wrong. Without
> > > an explanation, i cannot say if this is correct or not.
> > > 
> > 
> > Thanks for the review.
> > 
> > The DP1000 SoC integration provides the required TX and RX RGMII clock
> > skew, so enabling the YT8531 internal delays would apply the delay twice.
> 
> Please take a read of
> 
> https://elixir.bootlin.com/linux/v6.15/source/Documentation/devicetree/bindings/net/ethernet-controller.yaml#L287
> 
> You need to make the MAC driver do the correct thing:
> 
> # There are a small number of cases where the MAC has hard coded
> # delays which cannot be disabled. The 'phy-mode' only describes the
> # PCB.  The inability to disable the delays in the MAC does not change
> # the meaning of 'phy-mode'. It does however mean that a 'phy-mode' of
> # 'rgmii' is now invalid, it cannot be supported, since both the PCB
> # and the MAC and PHY adding delays cannot result in a functional
> # link. Thus the MAC should report a fatal error for any modes which
> # cannot be supported. When the MAC implements the delay, it must
> # ensure that the PHY does not also implement the same delay. So it
> # must modify the phy-mode it passes to the PHY, removing the delay it
> # has added. Failure to remove the delay will result in a
> # non-functioning link.
> 

Thanks for the clarification.

I will update the DTS to use "rgmii-id" and add a small DP1000 stmmac
glue driver. The driver will account for the fixed TX and RX MAC delays
using phy_fix_phy_mode_for_mac_delays(), reject unsupported modes, and
pass "rgmii" to the PHY.

>     Andrew
> 

Best regards,
Jia Wang



  reply	other threads:[~2026-08-27  4:55 UTC|newest]

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24  5:54 [PATCH 00/12] riscv: Add device tree support for UltraRISC DP1000 Jia Wang via B4 Relay
2026-08-24  5:54 ` [PATCH 01/12] dt-bindings: riscv: cpus: Fix yamllint style issues Jia Wang via B4 Relay
2026-08-24 16:35   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 02/12] dt-bindings: vendor-prefixes: Add shenrongda Jia Wang via B4 Relay
2026-08-24 17:03   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 03/12] dt-bindings: riscv: cpus: Add UltraRISC CP100 compatible Jia Wang via B4 Relay
2026-08-24 17:02   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 04/12] dt-bindings: riscv: Add UltraRISC DP1000 board compatibles Jia Wang via B4 Relay
2026-08-24 17:04   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 05/12] dt-bindings: timer: Add UltraRISC DP1000 CLINT Jia Wang via B4 Relay
2026-08-24 17:05   ` Conor Dooley
2026-08-24  5:54 ` [PATCH 06/12] spi: dt-bindings: snps,dw-apb-ssi: Add compatible for UltraRISC DP1000 SoC Jia Wang via B4 Relay
2026-08-24 17:07   ` Conor Dooley
2026-08-24 17:15     ` Conor Dooley
2026-08-25  8:16       ` Jia Wang
2026-08-24  5:54 ` [PATCH 07/12] dt-bindings: i2c: dw: " Jia Wang via B4 Relay
2026-08-24 17:07   ` Conor Dooley
2026-08-24 17:14     ` Conor Dooley
2026-08-25  8:45       ` Jia Wang
2026-08-24  5:54 ` [PATCH 08/12] dt-bindings: net: snps,dwmac: " Jia Wang via B4 Relay
2026-08-24 17:09   ` Conor Dooley
2026-08-24 17:13     ` Conor Dooley
2026-08-25 10:12       ` Jia Wang
2026-08-27  8:17         ` Jia Wang
2026-08-25  6:16   ` sashiko-bot
2026-08-24  5:54 ` [PATCH 09/12] dt-bindings: dma: snps,dw-axi-dmac: Add UltraRISC DP1000 compatible Jia Wang via B4 Relay
2026-08-24 17:03   ` Conor Dooley
2026-08-24 17:11     ` Conor Dooley
2026-08-26  5:31       ` Jia Wang
2026-08-24  5:54 ` [PATCH 10/12] riscv: dts: ultrarisc: Add initial device tree for UltraRISC DP1000 Jia Wang via B4 Relay
2026-08-25  6:16   ` sashiko-bot
2026-08-24  5:54 ` [PATCH 11/12] riscv: dts: ultrarisc: Add Shenzhen Rongda M0 board device tree Jia Wang via B4 Relay
2026-08-24 13:02   ` Andrew Lunn
2026-08-27  2:19     ` Jia Wang
2026-08-27  2:46       ` Andrew Lunn
2026-08-27  4:54         ` Jia Wang [this message]
2026-08-25  6:16   ` sashiko-bot
2026-08-24  5:54 ` [PATCH 12/12] riscv: dts: ultrarisc: Add Milk-V Titan " Jia Wang via B4 Relay
2026-08-24 13:06   ` Andrew Lunn
2026-08-27  2:24     ` Jia Wang
2026-08-25  6:16   ` sashiko-bot

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