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From: Michael Walle <michael@walle.cc>
To: Horatiu Vultur <horatiu.vultur@microchip.com>
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	claudiu.beznea@microchip.com, nicolas.ferre@microchip.com
Subject: Re: [PATCH] ARM: dts: lan966x: Fix the interrupt number for internal PHYs
Date: Tue, 13 Sep 2022 10:00:08 +0200	[thread overview]
Message-ID: <1f9ea2607ea1d8e0d4a2530a4c7dab41@walle.cc> (raw)
In-Reply-To: <20220913075719.y63uvvwzquk435ht@soft-dev3-1.localhost>

Am 2022-09-13 09:57, schrieb Horatiu Vultur:
>> Accoring to Table 3-155: Shared Peripheral Interrupts
>> There are ID47 and ID48 listed as "MIIM controller 0 interrupt".
>> Whatever that is, because the internal PHYs are on MIIM
>> controller 1.
>> 
>> But 80 and 81 would be ID48 and ID49. Did you test the
>> interrupts?
> 
> Looking the same table (3-155) in the documentation that I have these
> interrupts correspond to ID112 and ID113 (Embedded CuPHY port 0/1 
> interrupt).
> And because these are shared peripheral interrupts, it is required to
> substract 32. Therefore I got the numbers 80 and 81.

Ahh, I need more coffee :) Yes you are right.

> As the internal PHYs don't have yet interrupt support, I have sent a
> patch here [1] and I have tested it with this.
> 
> [1] https://www.spinics.net/lists/kernel/msg4511731.html

Thanks for the pointer!

-michael

  reply	other threads:[~2022-09-13  8:00 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-12 19:26 [PATCH] ARM: dts: lan966x: Fix the interrupt number for internal PHYs Horatiu Vultur
2022-09-13  7:18 ` Michael Walle
2022-09-13  7:57   ` Horatiu Vultur
2022-09-13  8:00     ` Michael Walle [this message]
2022-09-13  7:18 ` Claudiu.Beznea
2022-09-13  7:24   ` Michael Walle

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