Re: [PATCH 01/14] DEVICETREE: Add bindings for PIC32 interrupt controller

[Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>]

On Fri, Nov 20, 2015 at 05:17:13PM -0700, Joshua Henderson wrote:
> From: Cristian Birsan <cristian.birsan-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> 
> Document the devicetree bindings for the interrupt controller on Microchip
> PIC32 class devices. This also adds a header defining associated interrupts
> and related settings.
> 
> Signed-off-by: Cristian Birsan <cristian.birsan-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> Signed-off-by: Joshua Henderson <joshua.henderson-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
> ---
>  .../microchip,pic32mz-evic.txt                     |   65 ++++++
>  .../interrupt-controller/microchip,pic32mz-evic.h  |  238 ++++++++++++++++++++
>  2 files changed, 303 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
>  create mode 100644 include/dt-bindings/interrupt-controller/microchip,pic32mz-evic.h
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
> new file mode 100644
> index 0000000..12fb91f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,pic32mz-evic.txt
> @@ -0,0 +1,65 @@
> +Microchip PIC32MZ Interrupt Controller
> +======================================
> +
> +The Microchip PIC32MZ SOC contains an Enhanced Vectored Interrupt Controller
> +(EVIC) version 2. It handles internal and external interrupts and provides
> +support for priority, sub-priority, irq type and polarity.
> +
> +Required properties
> +-------------------
> +
> +- compatible: Should be "microchip,evic-v2"

This should be more specific like "microchip,pic32mz-evic". You can keep 
this one in addition if you like for matching.

Rob
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