* [PATCH V4 1/3] ASoC: fsl_esai: spba clock is needed by esai device
2015-11-24 9:19 [PATCH V4 0/3] add spba clock for fsl audio IP Shengjiu Wang
@ 2015-11-24 9:19 ` Shengjiu Wang
2015-11-24 9:19 ` [PATCH V4 2/3] ASoC: fsl_spdif: spba clk is needed by spdif device Shengjiu Wang
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Shengjiu Wang @ 2015-11-24 9:19 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, timur,
nicoleotsuka, Xiubo.Lee, lgirdwood, broonie, perex, tiwai,
shawnguo
Cc: alsa-devel, linuxppc-dev, linux-kernel, devicetree
ESAI need to enable the spba clock, when sdma is using share peripheral
script. In this case, there is two spba master port is used, if don't
enable the clock, the spba bus will have arbitration issue, which may
cause read/write wrong data from/to ESAI registers.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
Documentation/devicetree/bindings/sound/fsl,esai.txt | 5 +++++
sound/soc/fsl/fsl_esai.c | 17 +++++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt
index d3b6b5f..cd3ee5d 100644
--- a/Documentation/devicetree/bindings/sound/fsl,esai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt
@@ -27,6 +27,11 @@ Required properties:
derive HCK, SCK and FS.
"fsys" The system clock derived from ahb clock used to
derive HCK, SCK and FS.
+ "spba" The spba clock is required when ESAI is placed as a
+ bus slave of the Shared Peripheral Bus and when two
+ or more bus masters (CPU, DMA or DSP) try to access
+ it. This property is optional depending on the SoC
+ design.
- fsl,fifo-depth : The number of elements in the transmit and receive
FIFOs. This number is the maximum allowed value for
diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
index 504e731..054e64b 100644
--- a/sound/soc/fsl/fsl_esai.c
+++ b/sound/soc/fsl/fsl_esai.c
@@ -35,6 +35,7 @@
* @coreclk: clock source to access register
* @extalclk: esai clock source to derive HCK, SCK and FS
* @fsysclk: system clock source to derive HCK, SCK and FS
+ * @spbaclk: SPBA clock (optional, depending on SoC design)
* @fifo_depth: depth of tx/rx FIFO
* @slot_width: width of each DAI slot
* @slots: number of slots
@@ -54,6 +55,7 @@ struct fsl_esai {
struct clk *coreclk;
struct clk *extalclk;
struct clk *fsysclk;
+ struct clk *spbaclk;
u32 fifo_depth;
u32 slot_width;
u32 slots;
@@ -469,6 +471,11 @@ static int fsl_esai_startup(struct snd_pcm_substream *substream,
ret = clk_prepare_enable(esai_priv->coreclk);
if (ret)
return ret;
+ if (!IS_ERR(esai_priv->spbaclk)) {
+ ret = clk_prepare_enable(esai_priv->spbaclk);
+ if (ret)
+ goto err_spbaclk;
+ }
if (!IS_ERR(esai_priv->extalclk)) {
ret = clk_prepare_enable(esai_priv->extalclk);
if (ret)
@@ -499,6 +506,9 @@ err_fsysclk:
if (!IS_ERR(esai_priv->extalclk))
clk_disable_unprepare(esai_priv->extalclk);
err_extalck:
+ if (!IS_ERR(esai_priv->spbaclk))
+ clk_disable_unprepare(esai_priv->spbaclk);
+err_spbaclk:
clk_disable_unprepare(esai_priv->coreclk);
return ret;
@@ -564,6 +574,8 @@ static void fsl_esai_shutdown(struct snd_pcm_substream *substream,
clk_disable_unprepare(esai_priv->fsysclk);
if (!IS_ERR(esai_priv->extalclk))
clk_disable_unprepare(esai_priv->extalclk);
+ if (!IS_ERR(esai_priv->spbaclk))
+ clk_disable_unprepare(esai_priv->spbaclk);
clk_disable_unprepare(esai_priv->coreclk);
}
@@ -819,6 +831,11 @@ static int fsl_esai_probe(struct platform_device *pdev)
dev_warn(&pdev->dev, "failed to get fsys clock: %ld\n",
PTR_ERR(esai_priv->fsysclk));
+ esai_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
+ if (IS_ERR(esai_priv->spbaclk))
+ dev_warn(&pdev->dev, "failed to get spba clock: %ld\n",
+ PTR_ERR(esai_priv->spbaclk));
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH V4 2/3] ASoC: fsl_spdif: spba clk is needed by spdif device
2015-11-24 9:19 [PATCH V4 0/3] add spba clock for fsl audio IP Shengjiu Wang
2015-11-24 9:19 ` [PATCH V4 1/3] ASoC: fsl_esai: spba clock is needed by esai device Shengjiu Wang
@ 2015-11-24 9:19 ` Shengjiu Wang
2015-11-24 9:19 ` [PATCH V4 3/3] ASoC: fsl_asrc: spba clock is needed by asrc device Shengjiu Wang
2015-11-24 9:31 ` [PATCH V4 0/3] add spba clock for fsl audio IP Nicolin Chen
3 siblings, 0 replies; 5+ messages in thread
From: Shengjiu Wang @ 2015-11-24 9:19 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, timur,
nicoleotsuka, Xiubo.Lee, lgirdwood, broonie, perex, tiwai,
shawnguo
Cc: alsa-devel, linuxppc-dev, linux-kernel, devicetree
SPDIF need to enable the spba clock, when sdma is using share peripheral
script. In this case, there is two spba master port is used, if don't
enable the clock, the spba bus will have arbitration issue, which may
cause read/write wrong data from/to SPDIF registers.
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
Documentation/devicetree/bindings/sound/fsl,spdif.txt | 5 +++++
sound/soc/fsl/fsl_spdif.c | 19 +++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
index b5ee32e..4ca39dd 100644
--- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt
@@ -27,6 +27,11 @@ Required properties:
Transceiver Clock Diagram" of SoC reference manual.
It can also be referred to TxClk_Source bit of
register SPDIF_STC.
+ "spba" The spba clock is required when SPDIF is placed as a
+ bus slave of the Shared Peripheral Bus and when two
+ or more bus masters (CPU, DMA or DSP) try to access
+ it. This property is optional depending on the SoC
+ design.
- big-endian : If this property is absent, the native endian mode
will be in use as default, or the big endian mode
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index 28a8823..151849f 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -88,6 +88,7 @@ struct spdif_mixer_control {
* @rxclk: rx clock sources for capture
* @coreclk: core clock for register access via DMA
* @sysclk: system clock for rx clock rate measurement
+ * @spbaclk: SPBA clock (optional, depending on SoC design)
* @dma_params_tx: DMA parameters for transmit channel
* @dma_params_rx: DMA parameters for receive channel
*/
@@ -106,6 +107,7 @@ struct fsl_spdif_priv {
struct clk *rxclk;
struct clk *coreclk;
struct clk *sysclk;
+ struct clk *spbaclk;
struct snd_dmaengine_dai_dma_data dma_params_tx;
struct snd_dmaengine_dai_dma_data dma_params_rx;
/* regcache for SRPC */
@@ -474,6 +476,14 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream,
return ret;
}
+ if (!IS_ERR(spdif_priv->spbaclk)) {
+ ret = clk_prepare_enable(spdif_priv->spbaclk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to enable spba clock\n");
+ goto err_spbaclk;
+ }
+ }
+
ret = spdif_softreset(spdif_priv);
if (ret) {
dev_err(&pdev->dev, "failed to soft reset\n");
@@ -515,6 +525,9 @@ disable_txclk:
for (i--; i >= 0; i--)
clk_disable_unprepare(spdif_priv->txclk[i]);
err:
+ if (!IS_ERR(spdif_priv->spbaclk))
+ clk_disable_unprepare(spdif_priv->spbaclk);
+err_spbaclk:
clk_disable_unprepare(spdif_priv->coreclk);
return ret;
@@ -548,6 +561,8 @@ static void fsl_spdif_shutdown(struct snd_pcm_substream *substream,
spdif_intr_status_clear(spdif_priv);
regmap_update_bits(regmap, REG_SPDIF_SCR,
SCR_LOW_POWER, SCR_LOW_POWER);
+ if (!IS_ERR(spdif_priv->spbaclk))
+ clk_disable_unprepare(spdif_priv->spbaclk);
clk_disable_unprepare(spdif_priv->coreclk);
}
}
@@ -1261,6 +1276,10 @@ static int fsl_spdif_probe(struct platform_device *pdev)
return PTR_ERR(spdif_priv->coreclk);
}
+ spdif_priv->spbaclk = devm_clk_get(&pdev->dev, "spba");
+ if (IS_ERR(spdif_priv->spbaclk))
+ dev_warn(&pdev->dev, "no spba clock in devicetree\n");
+
/* Select clock source for rx/tx clock */
spdif_priv->rxclk = devm_clk_get(&pdev->dev, "rxtx1");
if (IS_ERR(spdif_priv->rxclk)) {
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH V4 3/3] ASoC: fsl_asrc: spba clock is needed by asrc device
2015-11-24 9:19 [PATCH V4 0/3] add spba clock for fsl audio IP Shengjiu Wang
2015-11-24 9:19 ` [PATCH V4 1/3] ASoC: fsl_esai: spba clock is needed by esai device Shengjiu Wang
2015-11-24 9:19 ` [PATCH V4 2/3] ASoC: fsl_spdif: spba clk is needed by spdif device Shengjiu Wang
@ 2015-11-24 9:19 ` Shengjiu Wang
2015-11-24 9:31 ` [PATCH V4 0/3] add spba clock for fsl audio IP Nicolin Chen
3 siblings, 0 replies; 5+ messages in thread
From: Shengjiu Wang @ 2015-11-24 9:19 UTC (permalink / raw)
To: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, timur,
nicoleotsuka, Xiubo.Lee, lgirdwood, broonie, perex, tiwai,
shawnguo
Cc: alsa-devel, linuxppc-dev, linux-kernel, devicetree
ASRC need to enable the spba clock, when sdma is using share peripheral
script. In this case, there is two spba master port is used, if don't
enable the clock, the spba bus will have arbitration issue, which may
cause read/write wrong data from/to ASRC registers
Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>
---
Documentation/devicetree/bindings/sound/fsl,asrc.txt | 5 +++++
sound/soc/fsl/fsl_asrc.c | 14 ++++++++++++++
sound/soc/fsl/fsl_asrc.h | 2 ++
3 files changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
index b93362a..3e26a94 100644
--- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt
+++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt
@@ -25,6 +25,11 @@ Required properties:
"mem" Peripheral access clock to access registers.
"ipg" Peripheral clock to driver module.
"asrck_<0-f>" Clock sources for input and output clock.
+ "spba" The spba clock is required when ASRC is placed as a
+ bus slave of the Shared Peripheral Bus and when two
+ or more bus masters (CPU, DMA or DSP) try to access
+ it. This property is optional depending on the SoC
+ design.
- big-endian : If this property is absent, the little endian mode
will be in use as default. Otherwise, the big endian
diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c
index 9f087d4..cf382475 100644
--- a/sound/soc/fsl/fsl_asrc.c
+++ b/sound/soc/fsl/fsl_asrc.c
@@ -859,6 +859,10 @@ static int fsl_asrc_probe(struct platform_device *pdev)
return PTR_ERR(asrc_priv->ipg_clk);
}
+ asrc_priv->spba_clk = devm_clk_get(&pdev->dev, "spba");
+ if (IS_ERR(asrc_priv->spba_clk))
+ dev_warn(&pdev->dev, "failed to get spba clock\n");
+
for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
sprintf(tmp, "asrck_%x", i);
asrc_priv->asrck_clk[i] = devm_clk_get(&pdev->dev, tmp);
@@ -939,6 +943,11 @@ static int fsl_asrc_runtime_resume(struct device *dev)
ret = clk_prepare_enable(asrc_priv->ipg_clk);
if (ret)
goto disable_mem_clk;
+ if (!IS_ERR(asrc_priv->spba_clk)) {
+ ret = clk_prepare_enable(asrc_priv->spba_clk);
+ if (ret)
+ goto disable_ipg_clk;
+ }
for (i = 0; i < ASRC_CLK_MAX_NUM; i++) {
ret = clk_prepare_enable(asrc_priv->asrck_clk[i]);
if (ret)
@@ -950,6 +959,9 @@ static int fsl_asrc_runtime_resume(struct device *dev)
disable_asrck_clk:
for (i--; i >= 0; i--)
clk_disable_unprepare(asrc_priv->asrck_clk[i]);
+ if (!IS_ERR(asrc_priv->spba_clk))
+ clk_disable_unprepare(asrc_priv->spba_clk);
+disable_ipg_clk:
clk_disable_unprepare(asrc_priv->ipg_clk);
disable_mem_clk:
clk_disable_unprepare(asrc_priv->mem_clk);
@@ -963,6 +975,8 @@ static int fsl_asrc_runtime_suspend(struct device *dev)
for (i = 0; i < ASRC_CLK_MAX_NUM; i++)
clk_disable_unprepare(asrc_priv->asrck_clk[i]);
+ if (!IS_ERR(asrc_priv->spba_clk))
+ clk_disable_unprepare(asrc_priv->spba_clk);
clk_disable_unprepare(asrc_priv->ipg_clk);
clk_disable_unprepare(asrc_priv->mem_clk);
diff --git a/sound/soc/fsl/fsl_asrc.h b/sound/soc/fsl/fsl_asrc.h
index 4aed63c..68802cd 100644
--- a/sound/soc/fsl/fsl_asrc.h
+++ b/sound/soc/fsl/fsl_asrc.h
@@ -426,6 +426,7 @@ struct fsl_asrc_pair {
* @paddr: physical address to the base address of registers
* @mem_clk: clock source to access register
* @ipg_clk: clock source to drive peripheral
+ * @spba_clk: SPBA clock (optional, depending on SoC design)
* @asrck_clk: clock sources to driver ASRC internal logic
* @lock: spin lock for resource protection
* @pair: pair pointers
@@ -442,6 +443,7 @@ struct fsl_asrc {
unsigned long paddr;
struct clk *mem_clk;
struct clk *ipg_clk;
+ struct clk *spba_clk;
struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
spinlock_t lock;
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH V4 0/3] add spba clock for fsl audio IP
2015-11-24 9:19 [PATCH V4 0/3] add spba clock for fsl audio IP Shengjiu Wang
` (2 preceding siblings ...)
2015-11-24 9:19 ` [PATCH V4 3/3] ASoC: fsl_asrc: spba clock is needed by asrc device Shengjiu Wang
@ 2015-11-24 9:31 ` Nicolin Chen
3 siblings, 0 replies; 5+ messages in thread
From: Nicolin Chen @ 2015-11-24 9:31 UTC (permalink / raw)
To: Shengjiu Wang
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, timur,
Xiubo.Lee, lgirdwood, broonie, perex, tiwai, shawnguo, alsa-devel,
linuxppc-dev, linux-kernel, devicetree
On Tue, Nov 24, 2015 at 05:19:31PM +0800, Shengjiu Wang wrote:
> add spba clock for fsl audio IP
>
> Changes in V3
> - add error check for spba clock
>
> Shengjiu Wang (3):
> ASoC: fsl_esai: spba clock is needed by esai device
> ASoC: fsl_spdif: spba clk is needed by spdif device
> ASoC: fsl_asrc: spba clock is needed by asrc device
For all three,
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
>
> Documentation/devicetree/bindings/sound/fsl,asrc.txt | 5 +++++
> Documentation/devicetree/bindings/sound/fsl,esai.txt | 5 +++++
> Documentation/devicetree/bindings/sound/fsl,spdif.txt | 5 +++++
> sound/soc/fsl/fsl_asrc.c | 14 ++++++++++++++
> sound/soc/fsl/fsl_asrc.h | 2 ++
> sound/soc/fsl/fsl_esai.c | 17 +++++++++++++++++
> sound/soc/fsl/fsl_spdif.c | 19 +++++++++++++++++++
> 7 files changed, 67 insertions(+)
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 5+ messages in thread