[RFC PATCH 2/5] DT: mailbox: add binding doc for the ARM SMC mailbox

[RFC PATCH 2/5] DT: mailbox: add binding doc for the ARM SMC mailbox

[Andre Przywara]

Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
 .../devicetree/bindings/mailbox/arm-smc.txt        | 53 ++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.txt

diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.txt b/Documentation/devicetree/bindings/mailbox/arm-smc.txt
new file mode 100644
index 0000000..9919a12
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/arm-smc.txt
@@ -0,0 +1,53 @@
+ARM SMC Mailbox Driver
+======================
+
+This mailbox driver uses the ARM smc (secure monitor call) instruction to
+trigger a mailbox-connected activity in firmware running on the very same
+core as the caller. By nature this operation is synchronous and this
+driver provides no way for asynchronous messages to be delivered the other
+way round, from firmware to the OS. However the value of r0/w0 the firmware
+returns after the smc call is delivered as a received message to the
+mailbox framework, so a synchronous communication can be established.
+
+One usecase of this mailbox is the SCP interface, which uses shared memory
+to transfer commands and parameters and mailboxes to trigger a function
+call. This driver allows SoC without a separate management processor (or
+when such a processor is not available or used) to use this standardized
+interface anyway.
+
+The driver requires no special hardware, any core which supports the SMC
+instruction can be used. This requires firmware in monitor mode/EL3 to
+handle the mailbox message.
+
+Mailbox Device Node:
+====================
+
+Required properties:
+--------------------
+- compatible:		Shall be "arm,smc-mbox"
+- #mbox-cells		Shall be 1 - the index of the channel needed.
+- identifiers		An array of 32-bit values specifying the function
+			IDs used by each mailbox channel. Those function IDs
+			follow the ARM SMC calling convention standard [1].
+			There is one identifier per channel and the number
+			of supported channels is determined by the length
+			of this array.
+
+Example:
+--------
+
+	mailbox: smc_mbox {
+		#mbox-cells = <1>;
+		compatible = "arm,smc-mbox";
+		identifiers = <0x82000001 0x82000002>;
+	};
+
+	scpi {
+		compatible = "arm,scpi";
+		mboxes = <&mailbox 0>;
+		shmem = <&cpu_scp_shmem>;
+	};
+
+
+[1]
+http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0028a/index.html
-- 
2.9.0

[RFC PATCH 3/5] arm64: dts: sunxi: add SCPI node to sun50i-a64.dtsi

[Andre Przywara]

Support for variable frequency clocks is implemented in ARM Trusted
Firmware, which sits in SRAM and waits for SCPI requests.
Add the respective SMC mailbox node and a 512-byte chunk of SRAM to
allow SCPI calls to be handled by the firmware.

Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 70d0382..9fc540e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -131,8 +131,34 @@
 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
 
+	mailbox: mbox@0 {
+		compatible = "arm,smc-mbox";
+		#mbox-cells = <1>;
+		identifiers = <0x82000001>;
+	};
+
+	sram: sram@18000{
+		compatible = "mmio-sram";
+		reg = <0x10000 0x8000>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x10000 0x8000>;
+
+		cpu_scp_mem: scp-shmem@7e00 {
+			compatible = "mmio-sram";
+			reg = <0x7e00 0x200>;
+		};
+	};
+
 	/include/ "sun50i-a64-clocks.dtsi"
 
+	scpi {
+		compatible = "arm,scpi";
+		mboxes = <&mailbox 0>;
+		shmem = <&cpu_scp_mem>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
-- 
2.9.0

[RFC PATCH 4/5] arm64: dts: sunxi: add SCPI driven clocks and nodes for A64 MMC

[Andre Przywara]

The MMC controllers in the Allwinner A64 SoC are somewhat compatible
with the versions used in other Allwinner SoCs.
Tell Linux about the three MMC clocks that the firmware implements and
add nodes to represent the MMC controllers.
The actual hardware is capable of new transfer modes, which the driver
does not fully support yet, also the clock part has changed, but it
works like this at least for SD card accesses.

Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 61 +++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 9fc540e..0f6044b 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -157,6 +157,19 @@
 		compatible = "arm,scpi";
 		mboxes = <&mailbox 0>;
 		shmem = <&cpu_scp_mem>;
+
+		clocks {
+			compatible = "arm,scpi-clocks";
+
+			scpi_clk: scpi_clocks {
+				compatible = "arm,scpi-variable-clocks";
+				#clock-cells = <1>;
+				clock-indices = <0>, <1>,
+						<2>;
+				clock-output-names = "mmc0_clk", "mmc1_clk",
+						     "mmc2_clk";
+			};
+		};
 	};
 
 	soc {
@@ -165,6 +178,54 @@
 		#size-cells = <1>;
 		ranges;
 
+		mmc0: mmc@1c0f000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&bus_gates 8>, <&scpi_clk 0>,
+				 <&scpi_clk 0>, <&scpi_clk 0>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
+			resets = <&ahb_rst 8>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc@1c10000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&bus_gates 9>, <&scpi_clk 1>,
+				 <&scpi_clk 1>, <&scpi_clk 1>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
+			resets = <&ahb_rst 9>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc@1c11000 {
+			compatible = "allwinner,sun50i-a64-mmc",
+				     "allwinner,sun5i-a13-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&bus_gates 10>, <&scpi_clk 2>,
+				 <&scpi_clk 2>, <&scpi_clk 2>;
+			clock-names = "ahb", "mmc",
+				      "output", "sample";
+			resets = <&ahb_rst 10>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		pio: pinctrl@1c20800 {
 			compatible = "allwinner,sun50i-a64-pinctrl";
 			reg = <0x01c20800 0x400>;
-- 
2.9.0

[RFC PATCH 5/5] arm64: dts: sunxi: add MMC nodes to Pine64 and BPi-M64 .dts

[Andre Przywara]

Those two boards connect a microSD card slot to the MMC0 controller.
Add the dummy regulator and enable MMC0 to allow accessing the SD card.

The BananaPi M64 has an on-board eMMC chip connected to the MMC2
controller, but the existing MMC driver does not support this properly
yet, so keep this one disabled for now.

Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
---
 .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 29 ++++++++++++++++++++++
 .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 20 +++++++++++++++
 2 files changed, 49 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index bc0ed4c..f98c351 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -59,6 +59,35 @@
 	aliases {
 		serial0 = &uart0;
 	};
+
+	soc {
+		reg_vcc3v3: vcc3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_vcc3v3>;
+	cd-gpios = <&pio 5 6 0>;
+	cd-inverted;
+	disable-wp;
+	status = "okay";
+};
+
+&mmc2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc2_pins>;
+	bus-width = <8>;
+	vmmc-supply = <&reg_vcc3v3>;
+	non-removable;
+	status = "disabled";
 };
 
 &uart0 {
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 077a56f..a3957ca 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -59,6 +59,26 @@
 	aliases {
 		serial0 = &uart0;
 	};
+
+	soc {
+		reg_vcc3v3: vcc3v3 {
+			compatible = "regulator-fixed";
+			regulator-name = "vcc3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+		};
+	};
+};
+
+&mmc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc0_pins>, <&mmc0_default_cd_pin>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_vcc3v3>;
+	cd-gpios = <&pio 5 6 0>;
+	cd-inverted;
+	disable-wp;
+	status = "okay";
 };
 
 &uart0 {
-- 
2.9.0

Re: [RFC PATCH 4/5] arm64: dts: sunxi: add SCPI driven clocks and nodes for A64 MMC

[Icenowy Zheng]

09.08.2016, 19:58, "Andre Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>:
>  The MMC controllers in the Allwinner A64 SoC are somewhat compatible
>  with the versions used in other Allwinner SoCs.
>  Tell Linux about the three MMC clocks that the firmware implements and
>  add nodes to represent the MMC controllers.
>  The actual hardware is capable of new transfer modes, which the driver
>  does not fully support yet, also the clock part has changed, but it
>  works like this at least for SD card accesses.
>
>  Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>  ---
>   arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 61 +++++++++++++++++++++++++++
>   1 file changed, 61 insertions(+)
>
>  diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>  index 9fc540e..0f6044b 100644
>  --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>  +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>  @@ -157,6 +157,19 @@
>                   compatible = "arm,scpi";
>                   mboxes = <&mailbox 0>;
>                   shmem = <&cpu_scp_mem>;
>  +
>  + clocks {
>  + compatible = "arm,scpi-clocks";
>  +
>  + scpi_clk: scpi_clocks {
>  + compatible = "arm,scpi-variable-clocks";
>  + #clock-cells = <1>;
>  + clock-indices = <0>, <1>,


I found a problem of the "standardize" process.
There cannot be an authority to keep the clock ID standardized, in both 

>  + <2>;
>  + clock-output-names = "mmc0_clk", "mmc1_clk",
>  + "mmc2_clk";
>  + };
>  + };
>           };
>
>           soc {
>  @@ -165,6 +178,54 @@
>                   #size-cells = <1>;
>                   ranges;
>
>  + mmc0: mmc@1c0f000 {
>  + compatible = "allwinner,sun50i-a64-mmc",
>  + "allwinner,sun5i-a13-mmc";
>  + reg = <0x01c0f000 0x1000>;
>  + clocks = <&bus_gates 8>, <&scpi_clk 0>,
>  + <&scpi_clk 0>, <&scpi_clk 0>;
>  + clock-names = "ahb", "mmc",
>  + "output", "sample";
>  + resets = <&ahb_rst 8>;
>  + reset-names = "ahb";
>  + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>  + status = "disabled";
>  + #address-cells = <1>;
>  + #size-cells = <0>;
>  + };
>  +
>  + mmc1: mmc@1c10000 {
>  + compatible = "allwinner,sun50i-a64-mmc",
>  + "allwinner,sun5i-a13-mmc";
>  + reg = <0x01c10000 0x1000>;
>  + clocks = <&bus_gates 9>, <&scpi_clk 1>,
>  + <&scpi_clk 1>, <&scpi_clk 1>;
>  + clock-names = "ahb", "mmc",
>  + "output", "sample";
>  + resets = <&ahb_rst 9>;
>  + reset-names = "ahb";
>  + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>  + status = "disabled";
>  + #address-cells = <1>;
>  + #size-cells = <0>;
>  + };
>  +
>  + mmc2: mmc@1c11000 {
>  + compatible = "allwinner,sun50i-a64-mmc",
>  + "allwinner,sun5i-a13-mmc";
>  + reg = <0x01c11000 0x1000>;
>  + clocks = <&bus_gates 10>, <&scpi_clk 2>,
>  + <&scpi_clk 2>, <&scpi_clk 2>;
>  + clock-names = "ahb", "mmc",
>  + "output", "sample";
>  + resets = <&ahb_rst 10>;
>  + reset-names = "ahb";
>  + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>  + status = "disabled";
>  + #address-cells = <1>;
>  + #size-cells = <0>;
>  + };
>  +
>                   pio: pinctrl@1c20800 {
>                           compatible = "allwinner,sun50i-a64-pinctrl";
>                           reg = <0x01c20800 0x400>;
>  --
>  2.9.0
>
>  _______________________________________________
>  linux-arm-kernel mailing list
>  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>  http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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Re: [RFC PATCH 2/5] DT: mailbox: add binding doc for the ARM SMC mailbox

[Rob Herring]

On Tue, Aug 09, 2016 at 12:53:00PM +0100, Andre Przywara wrote:
> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
> ---
>  .../devicetree/bindings/mailbox/arm-smc.txt        | 53 ++++++++++++++++++++++
>  1 file changed, 53 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mailbox/arm-smc.txt
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/arm-smc.txt b/Documentation/devicetree/bindings/mailbox/arm-smc.txt
> new file mode 100644
> index 0000000..9919a12
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/arm-smc.txt
> @@ -0,0 +1,53 @@
> +ARM SMC Mailbox Driver
> +======================
> +
> +This mailbox driver uses the ARM smc (secure monitor call) instruction to
> +trigger a mailbox-connected activity in firmware running on the very same
> +core as the caller. By nature this operation is synchronous and this
> +driver provides no way for asynchronous messages to be delivered the other
> +way round, from firmware to the OS. However the value of r0/w0 the firmware
> +returns after the smc call is delivered as a received message to the
> +mailbox framework, so a synchronous communication can be established.

Clever

> +
> +One usecase of this mailbox is the SCP interface, which uses shared memory
> +to transfer commands and parameters and mailboxes to trigger a function
> +call. This driver allows SoC without a separate management processor (or
> +when such a processor is not available or used) to use this standardized
> +interface anyway.
> +
> +The driver requires no special hardware, any core which supports the SMC
> +instruction can be used. This requires firmware in monitor mode/EL3 to
> +handle the mailbox message.
> +
> +Mailbox Device Node:
> +====================
> +
> +Required properties:
> +--------------------
> +- compatible:		Shall be "arm,smc-mbox"
> +- #mbox-cells		Shall be 1 - the index of the channel needed.
> +- identifiers		An array of 32-bit values specifying the function

Minimally, needs 'arm' prefix. 'identifiers' is pretty vague. Perhaps 
'arm,smc-func-ids' to say exactly what they are.

> +			IDs used by each mailbox channel. Those function IDs
> +			follow the ARM SMC calling convention standard [1].
> +			There is one identifier per channel and the number
> +			of supported channels is determined by the length
> +			of this array.
> +
> +Example:
> +--------
> +
> +	mailbox: smc_mbox {
> +		#mbox-cells = <1>;
> +		compatible = "arm,smc-mbox";
> +		identifiers = <0x82000001 0x82000002>;
> +	};
> +
> +	scpi {
> +		compatible = "arm,scpi";
> +		mboxes = <&mailbox 0>;
> +		shmem = <&cpu_scp_shmem>;
> +	};
> +
> +
> +[1]
> +http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0028a/index.html
> -- 
> 2.9.0
> 

Re: [RFC PATCH 4/5] arm64: dts: sunxi: add SCPI driven clocks and nodes for A64 MMC

[André Przywara]

On 10/08/16 16:01, Icenowy Zheng wrote:

Hi,

> 09.08.2016, 19:58, "Andre Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>:
>>  The MMC controllers in the Allwinner A64 SoC are somewhat compatible
>>  with the versions used in other Allwinner SoCs.
>>  Tell Linux about the three MMC clocks that the firmware implements and
>>  add nodes to represent the MMC controllers.
>>  The actual hardware is capable of new transfer modes, which the driver
>>  does not fully support yet, also the clock part has changed, but it
>>  works like this at least for SD card accesses.
>>
>>  Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>>  ---
>>   arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 61 +++++++++++++++++++++++++++
>>   1 file changed, 61 insertions(+)
>>
>>  diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>  index 9fc540e..0f6044b 100644
>>  --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>  +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>  @@ -157,6 +157,19 @@
>>                   compatible = "arm,scpi";
>>                   mboxes = <&mailbox 0>;
>>                   shmem = <&cpu_scp_mem>;
>>  +
>>  + clocks {
>>  + compatible = "arm,scpi-clocks";
>>  +
>>  + scpi_clk: scpi_clocks {
>>  + compatible = "arm,scpi-variable-clocks";
>>  + #clock-cells = <1>;
>>  + clock-indices = <0>, <1>,
> 
> 
> I found a problem of the "standardize" process.
> There cannot be an authority to keep the clock ID standardized, in both 

Why would this need to be standardized? All we would need to take care
of is matching firmware and DT. Ideally firmware generates (or provides)
that part of the DT, so it just puts in the bits and IDs it actually
implements.
Actually I am more for exploiting the "name" field for a clock that SCPI
provides. It allows clocks to be identified without knowing any ID in
advance, up to the point where we have something like "Ethernet" as a
clock identifier. I wonder if Linux could make use of that somehow.

Cheers,
Andre

> 
>>  + <2>;
>>  + clock-output-names = "mmc0_clk", "mmc1_clk",
>>  + "mmc2_clk";
>>  + };
>>  + };
>>           };
>>
>>           soc {
>>  @@ -165,6 +178,54 @@
>>                   #size-cells = <1>;
>>                   ranges;
>>
>>  + mmc0: mmc@1c0f000 {
>>  + compatible = "allwinner,sun50i-a64-mmc",
>>  + "allwinner,sun5i-a13-mmc";
>>  + reg = <0x01c0f000 0x1000>;
>>  + clocks = <&bus_gates 8>, <&scpi_clk 0>,
>>  + <&scpi_clk 0>, <&scpi_clk 0>;
>>  + clock-names = "ahb", "mmc",
>>  + "output", "sample";
>>  + resets = <&ahb_rst 8>;
>>  + reset-names = "ahb";
>>  + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>>  + status = "disabled";
>>  + #address-cells = <1>;
>>  + #size-cells = <0>;
>>  + };
>>  +
>>  + mmc1: mmc@1c10000 {
>>  + compatible = "allwinner,sun50i-a64-mmc",
>>  + "allwinner,sun5i-a13-mmc";
>>  + reg = <0x01c10000 0x1000>;
>>  + clocks = <&bus_gates 9>, <&scpi_clk 1>,
>>  + <&scpi_clk 1>, <&scpi_clk 1>;
>>  + clock-names = "ahb", "mmc",
>>  + "output", "sample";
>>  + resets = <&ahb_rst 9>;
>>  + reset-names = "ahb";
>>  + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>>  + status = "disabled";
>>  + #address-cells = <1>;
>>  + #size-cells = <0>;
>>  + };
>>  +
>>  + mmc2: mmc@1c11000 {
>>  + compatible = "allwinner,sun50i-a64-mmc",
>>  + "allwinner,sun5i-a13-mmc";
>>  + reg = <0x01c11000 0x1000>;
>>  + clocks = <&bus_gates 10>, <&scpi_clk 2>,
>>  + <&scpi_clk 2>, <&scpi_clk 2>;
>>  + clock-names = "ahb", "mmc",
>>  + "output", "sample";
>>  + resets = <&ahb_rst 10>;
>>  + reset-names = "ahb";
>>  + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>>  + status = "disabled";
>>  + #address-cells = <1>;
>>  + #size-cells = <0>;
>>  + };
>>  +
>>                   pio: pinctrl@1c20800 {
>>                           compatible = "allwinner,sun50i-a64-pinctrl";
>>                           reg = <0x01c20800 0x400>;
>>  --
>>  2.9.0
>>
>>  _______________________________________________
>>  linux-arm-kernel mailing list
>>  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>>  http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

Re: [RFC PATCH 4/5] arm64: dts: sunxi: add SCPI driven clocks and nodes for A64 MMC

[Icenowy Zheng]

11.08.2016, 07:20, "André Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>:
> On 10/08/16 16:01, Icenowy Zheng wrote:
>
> Hi,
>
>>  09.08.2016, 19:58, "Andre Przywara" <andre.przywara-5wv7dgnIgG8@public.gmane.org>:
>>>   The MMC controllers in the Allwinner A64 SoC are somewhat compatible
>>>   with the versions used in other Allwinner SoCs.
>>>   Tell Linux about the three MMC clocks that the firmware implements and
>>>   add nodes to represent the MMC controllers.
>>>   The actual hardware is capable of new transfer modes, which the driver
>>>   does not fully support yet, also the clock part has changed, but it
>>>   works like this at least for SD card accesses.
>>>
>>>   Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>>>   ---
>>>    arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 61 +++++++++++++++++++++++++++
>>>    1 file changed, 61 insertions(+)
>>>
>>>   diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>   index 9fc540e..0f6044b 100644
>>>   --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>   +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
>>>   @@ -157,6 +157,19 @@
>>>                    compatible = "arm,scpi";
>>>                    mboxes = <&mailbox 0>;
>>>                    shmem = <&cpu_scp_mem>;
>>>   +
>>>   + clocks {
>>>   + compatible = "arm,scpi-clocks";
>>>   +
>>>   + scpi_clk: scpi_clocks {
>>>   + compatible = "arm,scpi-variable-clocks";
>>>   + #clock-cells = <1>;
>>>   + clock-indices = <0>, <1>,
>>
>>  I found a problem of the "standardize" process.
>>  There cannot be an authority to keep the clock ID standardized, in both
>
> Why would this need to be standardized? All we would need to take care
> of is matching firmware and DT. Ideally firmware generates (or provides)
> that part of the DT, so it just puts in the bits and IDs it actually
> implements.
> Actually I am more for exploiting the "name" field for a clock that SCPI
> provides. It allows clocks to be identified without knowing any ID in
> advance, up to the point where we have something like "Ethernet" as a
> clock identifier. I wonder if Linux could make use of that somehow.
Using names is a good idea. 
>
> Cheers,
> Andre
>
>>>   + <2>;
>>>   + clock-output-names = "mmc0_clk", "mmc1_clk",
>>>   + "mmc2_clk";
>>>   + };
>>>   + };
>>>            };
>>>
>>>            soc {
>>>   @@ -165,6 +178,54 @@
>>>                    #size-cells = <1>;
>>>                    ranges;
>>>
>>>   + mmc0: mmc@1c0f000 {
>>>   + compatible = "allwinner,sun50i-a64-mmc",
>>>   + "allwinner,sun5i-a13-mmc";
>>>   + reg = <0x01c0f000 0x1000>;
>>>   + clocks = <&bus_gates 8>, <&scpi_clk 0>,
>>>   + <&scpi_clk 0>, <&scpi_clk 0>;
>>>   + clock-names = "ahb", "mmc",
>>>   + "output", "sample";
>>>   + resets = <&ahb_rst 8>;
>>>   + reset-names = "ahb";
>>>   + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
>>>   + status = "disabled";
>>>   + #address-cells = <1>;
>>>   + #size-cells = <0>;
>>>   + };
>>>   +
>>>   + mmc1: mmc@1c10000 {
>>>   + compatible = "allwinner,sun50i-a64-mmc",
>>>   + "allwinner,sun5i-a13-mmc";
>>>   + reg = <0x01c10000 0x1000>;
>>>   + clocks = <&bus_gates 9>, <&scpi_clk 1>,
>>>   + <&scpi_clk 1>, <&scpi_clk 1>;
>>>   + clock-names = "ahb", "mmc",
>>>   + "output", "sample";
>>>   + resets = <&ahb_rst 9>;
>>>   + reset-names = "ahb";
>>>   + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
>>>   + status = "disabled";
>>>   + #address-cells = <1>;
>>>   + #size-cells = <0>;
>>>   + };
>>>   +
>>>   + mmc2: mmc@1c11000 {
>>>   + compatible = "allwinner,sun50i-a64-mmc",
>>>   + "allwinner,sun5i-a13-mmc";
>>>   + reg = <0x01c11000 0x1000>;
>>>   + clocks = <&bus_gates 10>, <&scpi_clk 2>,
>>>   + <&scpi_clk 2>, <&scpi_clk 2>;
>>>   + clock-names = "ahb", "mmc",
>>>   + "output", "sample";
>>>   + resets = <&ahb_rst 10>;
>>>   + reset-names = "ahb";
>>>   + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>>>   + status = "disabled";
>>>   + #address-cells = <1>;
>>>   + #size-cells = <0>;
>>>   + };
>>>   +
>>>                    pio: pinctrl@1c20800 {
>>>                            compatible = "allwinner,sun50i-a64-pinctrl";
>>>                            reg = <0x01c20800 0x400>;
>>>   --
>>>   2.9.0
>>>
>>>   _______________________________________________
>>>   linux-arm-kernel mailing list
>>>   linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>>>   http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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