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From: Baruch Siach <baruch@tkos.co.il>
To: Miquel Raynal <miquel.raynal@free-electrons.com>
Cc: Mark Rutland <mark.rutland@arm.com>, Andrew Lunn <andrew@lunn.ch>,
	Jason Cooper <jason@lakedaemon.net>,
	Nadav Haklai <nadavh@marvell.com>,
	linux-pm@vger.kernel.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	Antoine Tenart <antoine.tenart@free-electrons.com>,
	Will Deacon <will.deacon@arm.com>,
	David Sniatkiwicz <davidsn@marvell.com>,
	Eduardo Valentin <edubezval@gmail.com>,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Gregory Clement <gregory.clement@free-electrons.com>,
	Zhang Rui <rui.zhang@intel.com>,
	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
	linux-arm-kernel@lists.infradead.org,
	Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Subject: Re: [PATCH v3 04/11] thermal: armada: Rationalize register accesses
Date: Mon, 18 Dec 2017 00:02:35 +0200	[thread overview]
Message-ID: <20171217220235.4uwy4nw77gf3kvfp@tarshish> (raw)
In-Reply-To: <20171216221838.v6gtaoqy2xhozapp@tarshish>

Hi Miquèl,

On Sun, Dec 17, 2017 at 12:18:38AM +0200, Baruch Siach wrote:
> On Thu, Dec 14, 2017 at 11:30:04AM +0100, Miquel Raynal wrote:
> > Bindings were incomplete for a long time by only exposing one of the two
> > available control registers. To ease the migration to the full bindings
> > (already in use for the Armada 375 SoC), rename the pointers for
> > clarification. This way, it will only be needed to add another pointer
> > to access the other control register when the time comes.
> > 
> > This avoids dangerous situations where the offset 0 of the control
> > area can be either one register or the other depending on the bindings
> > used. After this change, device trees of other SoCs could be migrated to
> > the "full" bindings if they may benefit from features from the
> > unaccessible register, without any change in the driver.
> > 
> > Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
> > ---
> 
> [...]
> 
> > +	/*
> > +	 * Legacy DT bindings only described "control1" register (also referred
> > +	 * as "control MSB" on old documentation). New bindings cover
> > +	 * "control0/control LSB" and "control1/control MSB" registers within
> > +	 * the same resource, which is then of size 8 instead of 4.
> > +	 */
> > +	if ((res->end - res->start) == LEGACY_CONTROL_MEM_LEN) {
> > +		/* ->control0 unavailable in this configuration */
> > +		priv->control1 = control + LEGACY_CONTROL1_OFFSET;
> > +	} else {
> > +		priv->control0 = control + CONTROL0_OFFSET;
> > +		priv->control1 = control + CONTROL1_OFFSET;
> > +	}
> 
> I think we need to add a check here that the control registers area size 
> matches the expected value given the compatible string. In case of mismatch 
> probe should fail.

One more thing. You should probably use resource_size() instead of open coding 
it. resource_size() does "res->end - res->start + 1". Are you sure your code 
is correct?

> >  	priv->data = (struct armada_thermal_data *)match->data;
> >  	priv->data->init_sensor(pdev, priv);

baruch

-- 
     http://baruch.siach.name/blog/                  ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -

  reply	other threads:[~2017-12-17 22:02 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-14 10:30 [PATCH v3 00/11] Armada thermal: improvements and A7K/A8K SoCs support Miquel Raynal
2017-12-14 10:30 ` [PATCH v3 01/11] dt-bindings: thermal: Describe Armada AP806 and CP110 Miquel Raynal
     [not found]   ` <20171214103011.24713-2-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-15  8:27     ` Baruch Siach
2017-12-15  8:32       ` Miquel RAYNAL
2017-12-15  8:44         ` Baruch Siach
2017-12-15  8:44         ` Gregory CLEMENT
     [not found]           ` <87po7gmlcs.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-15 10:52             ` Miquel RAYNAL
2017-12-15 23:28               ` Rob Herring
2017-12-16 12:50                 ` Miquel RAYNAL
2017-12-14 10:30 ` [PATCH v3 02/11] thermal: armada: Use msleep for long delays Miquel Raynal
2017-12-14 10:51   ` Gregory CLEMENT
2017-12-14 10:30 ` [PATCH v3 06/11] thermal: armada: Add support for Armada CP110 Miquel Raynal
     [not found]   ` <20171214103011.24713-7-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-14 11:11     ` Gregory CLEMENT
     [not found]       ` <87tvwto96y.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-14 11:33         ` Miquel RAYNAL
2017-12-14 11:37           ` Gregory CLEMENT
     [not found]             ` <87a7ylo803.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-14 12:24               ` Miquel RAYNAL
2017-12-14 10:30 ` [PATCH v3 07/11] thermal: armada: Update Kconfig and module description Miquel Raynal
     [not found]   ` <20171214103011.24713-8-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-14 11:13     ` Gregory CLEMENT
     [not found]       ` <87po7ho93k.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-14 11:17         ` Miquel RAYNAL
2017-12-14 11:30           ` Gregory CLEMENT
2017-12-14 11:36             ` Miquel RAYNAL
2017-12-14 13:10             ` Thomas Petazzoni
     [not found] ` <20171214103011.24713-1-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-14 10:30   ` [PATCH v3 03/11] thermal: armada: Simplify the check of the validity bit Miquel Raynal
2017-12-14 10:52     ` Gregory CLEMENT
     [not found]     ` <20171214103011.24713-4-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-15  8:33       ` Baruch Siach
2017-12-15 10:56         ` Miquel RAYNAL
2017-12-14 10:30   ` [PATCH v3 04/11] thermal: armada: Rationalize register accesses Miquel Raynal
     [not found]     ` <20171214103011.24713-5-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-14 10:55       ` Gregory CLEMENT
2017-12-16 22:18       ` Baruch Siach
2017-12-17 22:02         ` Baruch Siach [this message]
2017-12-18 12:37           ` Miquel RAYNAL
2017-12-15  8:56     ` Baruch Siach
2017-12-18 13:48       ` Miquel RAYNAL
2017-12-14 10:30   ` [PATCH v3 05/11] thermal: armada: Add support for Armada AP806 Miquel Raynal
     [not found]     ` <20171214103011.24713-6-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-14 11:05       ` Gregory CLEMENT
2017-12-18  9:41         ` Miquel RAYNAL
2017-12-18 11:11           ` Baruch Siach
2017-12-18 12:25             ` Miquel RAYNAL
2017-12-16 22:22     ` Baruch Siach
2017-12-14 10:30   ` [PATCH v3 08/11] thermal: armada: Change sensors trim default value Miquel Raynal
2017-12-14 10:30 ` [PATCH v3 09/11] thermal: armada: Wait sensors validity before exiting the init callback Miquel Raynal
2017-12-14 11:23   ` Gregory CLEMENT
2017-12-14 11:27     ` Miquel RAYNAL
2017-12-14 10:30 ` [PATCH v3 10/11] thermal: armada: Give useful names to the thermal zone Miquel Raynal
2017-12-14 10:30 ` [PATCH v3 11/11] ARM64: dts: marvell: Add thermal support for A7K/A8K Miquel Raynal

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