From: Florian Fainelli <f.fainelli@gmail.com>
To: bcm-kernel-feedback-list@broadcom.com
Cc: Florian Fainelli <f.fainelli@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Brian Norris <computersforpeace@gmail.com>,
Gregory Fong <gregory.0xf0@gmail.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
"moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
open list <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 4/9] soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs
Date: Tue, 19 Dec 2017 11:22:42 -0800 [thread overview]
Message-ID: <20171219192247.29799-5-f.fainelli@gmail.com> (raw)
In-Reply-To: <20171219192247.29799-1-f.fainelli@gmail.com>
On Broadcom Brahma-B53 CPUs, the CPU_CREDIT_REG offset got moved to
0x0b0 instead of 0x184, correct this such that we correcty
enable/disable write-pairing for these chips.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
drivers/soc/bcm/brcmstb/biuctrl.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c
index c3c548fcaa8c..e8322e663831 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -21,12 +21,13 @@
#include <linux/syscore_ops.h>
#include <linux/soc/brcmstb/brcmstb.h>
-#define CPU_CREDIT_REG_OFFSET 0x184
+#define B15_CPU_CREDIT_REG_OFFSET 0x184
+#define B53_CPU_CREDIT_REG_OFFSET 0x0b0
#define CPU_CREDIT_REG_MCPx_WR_PAIRING_EN_MASK 0x70000000
static void __iomem *cpubiuctrl_base;
static bool mcp_wr_pairing_en;
-static unsigned int cpu_credit_reg_offset = CPU_CREDIT_REG_OFFSET;
+static unsigned int cpu_credit_reg_offset;
static int __init mcp_write_pairing_set(void)
{
@@ -53,7 +54,7 @@ static int __init mcp_write_pairing_set(void)
static int __init setup_hifcpubiuctrl_regs(void)
{
- struct device_node *np;
+ struct device_node *np, *cpu_dn;
int ret = 0;
np = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
@@ -70,6 +71,23 @@ static int __init setup_hifcpubiuctrl_regs(void)
}
mcp_wr_pairing_en = of_property_read_bool(np, "brcm,write-pairing");
+
+ cpu_dn = of_get_cpu_node(0, NULL);
+ if (!cpu_dn) {
+ pr_err("failed to obtain CPU device node\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15"))
+ cpu_credit_reg_offset = B15_CPU_CREDIT_REG_OFFSET;
+ else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53"))
+ cpu_credit_reg_offset = B53_CPU_CREDIT_REG_OFFSET;
+ else {
+ pr_err("unsupported CPU\n");
+ ret = -EINVAL;
+ }
+ of_node_put(cpu_dn);
out:
of_node_put(np);
return ret;
--
2.9.3
next prev parent reply other threads:[~2017-12-19 19:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-19 19:22 [PATCH v2 0/9] soc: brcmstb: biuctrl updates for 64-bit chips Florian Fainelli
2017-12-19 19:22 ` [PATCH v2 1/9] dt-bindings: arm: Add entry for Broadcom Brahma-B53 Florian Fainelli
2017-12-19 19:22 ` [PATCH v2 2/9] dt-bindings: arm: brcmstb: Correct BIUCTRL node documentation Florian Fainelli
[not found] ` <20171219192247.29799-3-f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-12-20 21:24 ` Rob Herring
2017-12-19 19:22 ` [PATCH v2 3/9] soc: brcmstb: Make CPU credit offset more parameterized Florian Fainelli
2017-12-19 19:22 ` Florian Fainelli [this message]
2017-12-19 19:22 ` [PATCH v2 5/9] soc: brcmstb: biuctrl: Prepare for saving/restoring other registers Florian Fainelli
2017-12-19 19:22 ` [PATCH v2 6/9] soc: brcmstb: biuctrl: Wire-up new registers Florian Fainelli
2017-12-19 19:22 ` [PATCH v2 7/9] soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings Florian Fainelli
2017-12-19 19:22 ` [PATCH v2 8/9] soc: brcmstb: Split initialization Florian Fainelli
2017-12-19 19:22 ` [PATCH v2 9/9] soc: brcmstb: biuctrl: Move to early_initcall Florian Fainelli
[not found] ` <20171219192247.29799-1-f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2017-12-21 1:38 ` [PATCH v2 0/9] soc: brcmstb: biuctrl updates for 64-bit chips Florian Fainelli
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