[PATCH v2 0/2] arm64: dts: renesas: Add support for R-Car E3 and Ebisu board

[PATCH v2 0/2] arm64: dts: renesas: Add support for R-Car E3 and Ebisu board

[Yoshihiro Shimoda]

This patch is based on the renesas-devel-20180418-v4.17-rc1 tag of
renesas.git.
This code doesn't use dt-bindings definitions to avoid dependency.

Changes from v1:
 - Change some nodes places in patch 1.
   Discussed on https://patchwork.kernel.org/patch/10335237/


Takeshi Kihara (1):
  arm64: dts: renesas: Add Renesas Ebisu board support

Yoshihiro Shimoda (1):
  arm64: dts: renesas: Add Renesas R8A77990 SoC support

 arch/arm64/boot/dts/renesas/Makefile           |   1 +
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts |  37 +++++++
 arch/arm64/boot/dts/renesas/r8a77990.dtsi      | 127 +++++++++++++++++++++++++
 3 files changed, 165 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi

-- 
1.9.1

[PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Yoshihiro Shimoda]

This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
  - PSCI
  - CPU (single)
  - Cache controller
  - Main clocks and controller
  - Interrupt controller
  - Timer
  - PMU
  - Reset controller
  - Product register
  - System controller
  - UART for console

Inspried by a patch by Takeshi Kihara in the BSP.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a77990.dtsi | 127 ++++++++++++++++++++++++++++++
 1 file changed, 127 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
new file mode 100644
index 0000000..3a19b9e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -0,0 +1,127 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree Source for the r8a77990 SoC
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r8a77990";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* 1 core only at this point */
+		a53_0: cpu@0 {
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0>;
+			device_type = "cpu";
+			power-domains = <&sysc 5>;
+			next-level-cache = <&L2_CA53>;
+			enable-method = "psci";
+		};
+
+		L2_CA53: cache-controller@0 {
+			compatible = "cache";
+			reg = <0>;
+			power-domains = <&sysc 21>;
+			cache-unified;
+			cache-level = <2>;
+		};
+	};
+
+	extal_clk: extal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	pmu_a53 {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&a53_0>;
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		cpg: clock-controller@e6150000 {
+			compatible = "renesas,r8a77990-cpg-mssr";
+			reg = <0 0xe6150000 0 0x1000>;
+			clocks = <&extal_clk>;
+			clock-names = "extal";
+			#clock-cells = <2>;
+			#power-domain-cells = <0>;
+			#reset-cells = <1>;
+		};
+
+		rst: reset-controller@e6160000 {
+			compatible = "renesas,r8a77990-rst";
+			reg = <0 0xe6160000 0 0x0200>;
+		};
+
+		sysc: system-controller@e6180000 {
+			compatible = "renesas,r8a77990-sysc";
+			reg = <0 0xe6180000 0 0x0400>;
+			#power-domain-cells = <1>;
+		};
+
+		scif2: serial@e6e88000 {
+			compatible = "renesas,scif-r8a77990",
+				     "renesas,rcar-gen3-scif", "renesas,scif";
+			reg = <0 0xe6e88000 0 64>;
+			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 310>;
+			clock-names = "fck";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 310>;
+			status = "disabled";
+		};
+
+		gic: interrupt-controller@f1010000 {
+			compatible = "arm,gic-400";
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0x0 0xf1010000 0 0x1000>,
+			      <0x0 0xf1020000 0 0x20000>,
+			      <0x0 0xf1040000 0 0x20000>,
+			      <0x0 0xf1060000 0 0x20000>;
+			interrupts = <GIC_PPI 9
+					(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+			clocks = <&cpg CPG_MOD 408>;
+			clock-names = "clk";
+			power-domains = <&sysc 32>;
+			resets = <&cpg 408>;
+		};
+
+		prr: chipid@fff00044 {
+			compatible = "renesas,prr";
+			reg = <0 0xfff00044 0 4>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+};
-- 
1.9.1

[PATCH v2 2/2] arm64: dts: renesas: Add Renesas Ebisu board support

[Yoshihiro Shimoda]

From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

Basic support for the Renesas Ebisu board based on R-Car E3:
  - Memory,
  - Main crystal,
  - Serial console,

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[shimoda: rebase and add SPDX-License-Identifier]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
 arch/arm64/boot/dts/renesas/Makefile           |  1 +
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 37 ++++++++++++++++++++++++++
 2 files changed, 38 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 5ede060..a235961 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -10,4 +10,5 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
 dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
 dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
+dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
 dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
new file mode 100644
index 0000000..63ee134
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Device Tree Source for the ebisu board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a77990.dtsi"
+
+/ {
+	model = "Renesas Ebisu board based on r8a77990";
+	compatible = "renesas,ebisu", "renesas,r8a77990";
+
+	aliases {
+		serial0 = &scif2;
+	};
+
+	chosen {
+		bootargs = "ignore_loglevel";
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@48000000 {
+		device_type = "memory";
+		/* first 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x38000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <48000000>;
+};
+
+&scif2 {
+	status = "okay";
+};
-- 
1.9.1

Re: [PATCH v2 0/2] arm64: dts: renesas: Add support for R-Car E3 and Ebisu board

[Simon Horman]

On Fri, Apr 20, 2018 at 09:28:15PM +0900, Yoshihiro Shimoda wrote:
> This patch is based on the renesas-devel-20180418-v4.17-rc1 tag of
> renesas.git.
> This code doesn't use dt-bindings definitions to avoid dependency.
> 
> Changes from v1:
>  - Change some nodes places in patch 1.
>    Discussed on https://patchwork.kernel.org/patch/10335237/

Thanks for the update, applied.

Re: [PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Geert Uytterhoeven]

Hi Shimoda-san,

On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
>   - PSCI
>   - CPU (single)
>   - Cache controller
>   - Main clocks and controller
>   - Interrupt controller
>   - Timer
>   - PMU
>   - Reset controller
>   - Product register
>   - System controller
>   - UART for console
>
> Inspried by a patch by Takeshi Kihara in the BSP.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Thanks for you patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> @@ -0,0 +1,127 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Device Tree Source for the r8a77990 SoC
> + *
> + * Copyright (C) 2018 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       compatible = "renesas,r8a77990";
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       cpus {

> +               L2_CA53: cache-controller@0 {
> +                       compatible = "cache";
> +                       reg = <0>;

Please no unit-addresses and reg properties for cache controllers.

> +                       power-domains = <&sysc 21>;
> +                       cache-unified;
> +                       cache-level = <2>;
> +               };
> +       };

> +       psci {
> +               compatible = "arm,psci-0.2";

"arm,psci-1.0", "arm,psci-0.2"?

> +               method = "smc";
> +       };
> +
> +       soc: soc {

> +               rst: reset-controller@e6160000 {
> +                       compatible = "renesas,r8a77990-rst";
> +                       reg = <0 0xe6160000 0 0x0200>;
> +               };
> +
> +               sysc: system-controller@e6180000 {
> +                       compatible = "renesas,r8a77990-sysc";
> +                       reg = <0 0xe6180000 0 0x0400>;
> +                       #power-domain-cells = <1>;
> +               };
> +
> +               scif2: serial@e6e88000 {
> +                       compatible = "renesas,scif-r8a77990",
> +                                    "renesas,rcar-gen3-scif", "renesas,scif";
> +                       reg = <0 0xe6e88000 0 64>;
> +                       interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_MOD 310>;
> +                       clock-names = "fck";

I assume you plan to add the other clocks later? That's fine for me.

> +                       power-domains = <&sysc 32>;
> +                       resets = <&cpg 310>;
> +                       status = "disabled";
> +               };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/2] arm64: dts: renesas: Add Renesas Ebisu board support

[Geert Uytterhoeven]

On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> Basic support for the Renesas Ebisu board based on R-Car E3:
>   - Memory,
>   - Main crystal,
>   - Serial console,
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> [shimoda: rebase and add SPDX-License-Identifier]
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Simon Horman]

On Tue, Apr 24, 2018 at 10:26:37AM +0200, Geert Uytterhoeven wrote:
> Hi Shimoda-san,
> 
> On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
> >   - PSCI
> >   - CPU (single)
> >   - Cache controller
> >   - Main clocks and controller
> >   - Interrupt controller
> >   - Timer
> >   - PMU
> >   - Reset controller
> >   - Product register
> >   - System controller
> >   - UART for console
> >
> > Inspried by a patch by Takeshi Kihara in the BSP.
> >
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Thanks for you patch!

Thanks for your review.

As I've already applied this patch I'd like to ask Shimoda-san
to send incremental patches to address the issues you raise below.

> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > @@ -0,0 +1,127 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Device Tree Source for the r8a77990 SoC
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +       compatible = "renesas,r8a77990";
> > +       #address-cells = <2>;
> > +       #size-cells = <2>;
> > +
> > +       cpus {
> 
> > +               L2_CA53: cache-controller@0 {
> > +                       compatible = "cache";
> > +                       reg = <0>;
> 
> Please no unit-addresses and reg properties for cache controllers.
> 
> > +                       power-domains = <&sysc 21>;
> > +                       cache-unified;
> > +                       cache-level = <2>;
> > +               };
> > +       };
> 
> > +       psci {
> > +               compatible = "arm,psci-0.2";
> 
> "arm,psci-1.0", "arm,psci-0.2"?
> 
> > +               method = "smc";
> > +       };
> > +
> > +       soc: soc {
> 
> > +               rst: reset-controller@e6160000 {
> > +                       compatible = "renesas,r8a77990-rst";
> > +                       reg = <0 0xe6160000 0 0x0200>;
> > +               };
> > +
> > +               sysc: system-controller@e6180000 {
> > +                       compatible = "renesas,r8a77990-sysc";
> > +                       reg = <0 0xe6180000 0 0x0400>;
> > +                       #power-domain-cells = <1>;
> > +               };
> > +
> > +               scif2: serial@e6e88000 {
> > +                       compatible = "renesas,scif-r8a77990",
> > +                                    "renesas,rcar-gen3-scif", "renesas,scif";
> > +                       reg = <0 0xe6e88000 0 64>;
> > +                       interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
> > +                       clocks = <&cpg CPG_MOD 310>;
> > +                       clock-names = "fck";
> 
> I assume you plan to add the other clocks later? That's fine for me.
> 
> > +                       power-domains = <&sysc 32>;
> > +                       resets = <&cpg 310>;
> > +                       status = "disabled";
> > +               };
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
> 

Re: [PATCH v2 2/2] arm64: dts: renesas: Add Renesas Ebisu board support

[Simon Horman]

On Tue, Apr 24, 2018 at 10:31:57AM +0200, Geert Uytterhoeven wrote:
> On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
> <yoshihiro.shimoda.uh@renesas.com> wrote:
> > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> >
> > Basic support for the Renesas Ebisu board based on R-Car E3:
> >   - Memory,
> >   - Main crystal,
> >   - Serial console,
> >
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > [shimoda: rebase and add SPDX-License-Identifier]
> > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> 
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Thanks, tag added.

RE: [PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Yoshihiro Shimoda]

Hi, Simon-san,

> From: Simon Horman, Sent: Tuesday, April 24, 2018 5:37 PM
> 
> On Tue, Apr 24, 2018 at 10:26:37AM +0200, Geert Uytterhoeven wrote:
> > Hi Shimoda-san,
> >
> > On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
> > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
> > >   - PSCI
> > >   - CPU (single)
> > >   - Cache controller
> > >   - Main clocks and controller
> > >   - Interrupt controller
> > >   - Timer
> > >   - PMU
> > >   - Reset controller
> > >   - Product register
> > >   - System controller
> > >   - UART for console
> > >
> > > Inspried by a patch by Takeshi Kihara in the BSP.
> > >
> > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> >
> > Thanks for you patch!
> 
> Thanks for your review.
> 
> As I've already applied this patch I'd like to ask Shimoda-san
> to send incremental patches to address the issues you raise below.

I got it. I'll send incremental patches.

Best regards,
Yoshihiro Shimoda

> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
> > > @@ -0,0 +1,127 @@
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > +/*
> > > + * Device Tree Source for the r8a77990 SoC
> > > + *
> > > + * Copyright (C) 2018 Renesas Electronics Corp.
> > > + */
> > > +
> > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > > +
> > > +/ {
> > > +       compatible = "renesas,r8a77990";
> > > +       #address-cells = <2>;
> > > +       #size-cells = <2>;
> > > +
> > > +       cpus {
> >
> > > +               L2_CA53: cache-controller@0 {
> > > +                       compatible = "cache";
> > > +                       reg = <0>;
> >
> > Please no unit-addresses and reg properties for cache controllers.
> >
> > > +                       power-domains = <&sysc 21>;
> > > +                       cache-unified;
> > > +                       cache-level = <2>;
> > > +               };
> > > +       };
> >
> > > +       psci {
> > > +               compatible = "arm,psci-0.2";
> >
> > "arm,psci-1.0", "arm,psci-0.2"?
> >
> > > +               method = "smc";
> > > +       };
> > > +
> > > +       soc: soc {
> >
> > > +               rst: reset-controller@e6160000 {
> > > +                       compatible = "renesas,r8a77990-rst";
> > > +                       reg = <0 0xe6160000 0 0x0200>;
> > > +               };
> > > +
> > > +               sysc: system-controller@e6180000 {
> > > +                       compatible = "renesas,r8a77990-sysc";
> > > +                       reg = <0 0xe6180000 0 0x0400>;
> > > +                       #power-domain-cells = <1>;
> > > +               };
> > > +
> > > +               scif2: serial@e6e88000 {
> > > +                       compatible = "renesas,scif-r8a77990",
> > > +                                    "renesas,rcar-gen3-scif", "renesas,scif";
> > > +                       reg = <0 0xe6e88000 0 64>;
> > > +                       interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
> > > +                       clocks = <&cpg CPG_MOD 310>;
> > > +                       clock-names = "fck";
> >
> > I assume you plan to add the other clocks later? That's fine for me.
> >
> > > +                       power-domains = <&sysc 32>;
> > > +                       resets = <&cpg 310>;
> > > +                       status = "disabled";
> > > +               };
> >
> > Gr{oetje,eeting}s,
> >
> >                         Geert
> >
> > --
> > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> >
> > In personal conversations with technical people, I call myself a hacker. But
> > when I'm talking to journalists I just say "programmer" or something like that.
> >                                 -- Linus Torvalds
> >

Re: [PATCH v2 1/2] arm64: dts: renesas: Add Renesas R8A77990 SoC support

[Simon Horman]

On Wed, Apr 25, 2018 at 02:47:41AM +0000, Yoshihiro Shimoda wrote:
> Hi, Simon-san,
> 
> > From: Simon Horman, Sent: Tuesday, April 24, 2018 5:37 PM
> > 
> > On Tue, Apr 24, 2018 at 10:26:37AM +0200, Geert Uytterhoeven wrote:
> > > Hi Shimoda-san,
> > >
> > > On Fri, Apr 20, 2018 at 2:28 PM, Yoshihiro Shimoda
> > > <yoshihiro.shimoda.uh@renesas.com> wrote:
> > > > This patch adds basic support for the Renesas R-Car E3 (R8A77990) SoC:
> > > >   - PSCI
> > > >   - CPU (single)
> > > >   - Cache controller
> > > >   - Main clocks and controller
> > > >   - Interrupt controller
> > > >   - Timer
> > > >   - PMU
> > > >   - Reset controller
> > > >   - Product register
> > > >   - System controller
> > > >   - UART for console
> > > >
> > > > Inspried by a patch by Takeshi Kihara in the BSP.
> > > >
> > > > Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
> > >
> > > Thanks for you patch!
> > 
> > Thanks for your review.
> > 
> > As I've already applied this patch I'd like to ask Shimoda-san
> > to send incremental patches to address the issues you raise below.
> 
> I got it. I'll send incremental patches.

Thanks, much appreciated.