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From: Vinod Koul <vkoul@kernel.org>
To: Wesley Cheng <wcheng@codeaurora.org>
Cc: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com,
	robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de,
	mgautam@codeaurora.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v5 2/5] phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs
Date: Fri, 3 Apr 2020 11:31:27 +0530	[thread overview]
Message-ID: <20200403060127.GM72691@vkoul-mobl> (raw)
In-Reply-To: <1585880634-15222-3-git-send-email-wcheng@codeaurora.org>

On 02-04-20, 19:23, Wesley Cheng wrote:
> This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs.  There
> are potentially multiple instances of this UTMI PHY on the
> SOC, all which can utilize this driver.  The V2 driver will
> have a different register map compared to V1.

Some nitpicks below, otherwise:

Reviewed-by: Vinod Koul <vkoul@kernel.org>

> +/**
> + * struct qcom_snps_hsphy - structure holding snps hs phy attributes
> + *
> + * @phy: generic phy
> + * @base: iomapped memory space for qubs2 phy
> + *
> + * @cfg_ahb_clk: AHB2PHY interface clock
> + * @ref_clk: phy reference clock
> + * @iface_clk: phy interface clock
> + * @phy_reset: phy reset control
> + * @vregs: regulator supplies bulk data
> +

This is missing the marker * for kernel doc

> + * @phy_initialized: if PHY has been initialized correctly
> + *

This empty line is redundant

> + */
> +struct qcom_snps_hsphy {
> +	struct phy *phy;
> +	void __iomem *base;
> +
> +	struct clk *cfg_ahb_clk;
> +	struct clk *ref_clk;
> +	struct reset_control *phy_reset;
> +	struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS];
> +
> +	bool phy_initialized;
> +};
> +
> +static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
> +				    u32 mask, u32 val)

coding style mandates that second line should start at preceeding line
opening brace :), so can you please make it:

static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset,
                                              u32 mask, u32 val)

-- 
~Vinod

  reply	other threads:[~2020-04-03  6:01 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-03  2:23 [PATCH v5 0/5] Add SS/HS-USB changes for Qualcomm SM8150 chipset Wesley Cheng
2020-04-03  2:23 ` [PATCH v5 1/5] dt-bindings: phy: Add binding for qcom,usb-snps-femto-v2 Wesley Cheng
2020-04-03  2:23 ` [PATCH v5 2/5] phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs Wesley Cheng
2020-04-03  6:01   ` Vinod Koul [this message]
2020-04-03 16:56     ` Wesley Cheng
2020-04-03  2:23 ` [PATCH v5 3/5] phy: qcom-qmp: Add SM8150 QMP USB3 PHY support Wesley Cheng
2020-04-03  2:23 ` [PATCH v5 4/5] phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB Wesley Cheng
2020-04-03  2:23 ` [PATCH v5 5/5] phy: qcom-qmp: Rename UFS PCS QMP v4 registers Wesley Cheng

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