From: <daire.mcnamara@microchip.com>
To: <conor.dooley@microchip.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<lpieralisi@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Cc: Daire McNamara <daire.mcnamara@microchip.com>
Subject: [PATCH v2 9/9] riscv: dts: microchip: add parent ranges and dma-ranges for IKRD v2022.09
Date: Wed, 21 Dec 2022 16:26:30 +0000 [thread overview]
Message-ID: <20221221162630.3632486-10-daire.mcnamara@microchip.com> (raw)
In-Reply-To: <20221221162630.3632486-1-daire.mcnamara@microchip.com>
From: Conor Dooley <conor.dooley@microchip.com>
we have replaced the "microchip,matro0" hack property with what was
suggested by Rob - create a parent bus and use ranges and dma-ranges in
the parent bus and pcie device to achieve the address translations we
need. Add the appropriate ranges and dma-ranges for the v2022.09 IKRD
so that it remains functional.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
---
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 62 +++++++++++--------
1 file changed, 35 insertions(+), 27 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 1069134f2e12..51ce87e70b33 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -26,33 +26,41 @@ i2c2: i2c@40000200 {
status = "disabled";
};
- pcie: pcie@3000000000 {
- compatible = "microchip,pcie-host-1.0";
- #address-cells = <0x3>;
- #interrupt-cells = <0x1>;
- #size-cells = <0x2>;
- device_type = "pci";
- reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
- reg-names = "cfg", "apb";
- bus-range = <0x0 0x7f>;
- interrupt-parent = <&plic>;
- interrupts = <119>;
- interrupt-map = <0 0 0 1 &pcie_intc 0>,
- <0 0 0 2 &pcie_intc 1>,
- <0 0 0 3 &pcie_intc 2>,
- <0 0 0 4 &pcie_intc 3>;
- interrupt-map-mask = <0 0 0 7>;
- clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
- clock-names = "fic1", "fic3";
- ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
- dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>;
- msi-parent = <&pcie>;
- msi-controller;
- status = "disabled";
- pcie_intc: interrupt-controller {
- #address-cells = <0>;
- #interrupt-cells = <1>;
- interrupt-controller;
+ fabric-pcie-bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>,
+ <0x30 0x0 0x30 0x0 0x10 0x0>;
+ dma-ranges = <0x0 0x0 0x10 0x0 0x0 0x80000000>;
+ pcie: pcie@3000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
+ clock-names = "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>;
+ dma-ranges = <0x3000000 0x10 0x0 0x0 0x0 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ status = "disabled";
+ pcie_intc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
};
};
--
2.25.1
prev parent reply other threads:[~2022-12-21 16:27 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-21 16:26 [PATCH v2 0/9] PCI: microchip: Partition address translations daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 1/9] PCI: microchip: Correct the DED and SEC interrupt bit offsets daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 2/9] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 4/9] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 5/9] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 6/9] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 7/9] PCI: microchip: Partition outbound address translation daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 8/9] PCI: microchip: Partition inbound " daire.mcnamara
2022-12-22 5:30 ` kernel test robot
2022-12-30 19:52 ` Bjorn Helgaas
2022-12-21 16:26 ` daire.mcnamara [this message]
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