From: <daire.mcnamara@microchip.com>
To: <conor.dooley@microchip.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
<lpieralisi@kernel.org>, <kw@linux.com>, <bhelgaas@google.com>,
<linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-pci@vger.kernel.org>
Cc: Daire McNamara <daire.mcnamara@microchip.com>
Subject: [PATCH v2 1/9] PCI: microchip: Correct the DED and SEC interrupt bit offsets
Date: Wed, 21 Dec 2022 16:26:22 +0000 [thread overview]
Message-ID: <20221221162630.3632486-2-daire.mcnamara@microchip.com> (raw)
In-Reply-To: <20221221162630.3632486-1-daire.mcnamara@microchip.com>
From: Daire McNamara <daire.mcnamara@microchip.com>
The SEC and DED interrupt bits were the wrong way round so the SEC
interrupt handler attempted to mask, unmask, and clear the DED interrupt
and vice versa. Correct the bit offsets so each interrupt handler
operates properly.
Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver")
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/pci/controller/pcie-microchip-host.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pcie-microchip-host.c b/drivers/pci/controller/pcie-microchip-host.c
index 0ebf7015e9af..5c89caaab8c9 100644
--- a/drivers/pci/controller/pcie-microchip-host.c
+++ b/drivers/pci/controller/pcie-microchip-host.c
@@ -167,12 +167,12 @@
#define EVENT_PCIE_DLUP_EXIT 2
#define EVENT_SEC_TX_RAM_SEC_ERR 3
#define EVENT_SEC_RX_RAM_SEC_ERR 4
-#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 5
-#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 6
+#define EVENT_SEC_PCIE2AXI_RAM_SEC_ERR 5
+#define EVENT_SEC_AXI2PCIE_RAM_SEC_ERR 6
#define EVENT_DED_TX_RAM_DED_ERR 7
#define EVENT_DED_RX_RAM_DED_ERR 8
-#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 9
-#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 10
+#define EVENT_DED_PCIE2AXI_RAM_DED_ERR 9
+#define EVENT_DED_AXI2PCIE_RAM_DED_ERR 10
#define EVENT_LOCAL_DMA_END_ENGINE_0 11
#define EVENT_LOCAL_DMA_END_ENGINE_1 12
#define EVENT_LOCAL_DMA_ERROR_ENGINE_0 13
--
2.25.1
next prev parent reply other threads:[~2022-12-21 16:26 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-21 16:26 [PATCH v2 0/9] PCI: microchip: Partition address translations daire.mcnamara
2022-12-21 16:26 ` daire.mcnamara [this message]
2022-12-21 16:26 ` [PATCH v2 2/9] PCI: microchip: Align register, offset, and mask names with hw docs daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 3/9] PCI: microchip: Enable event handlers to access bridge and ctrl ptrs daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 4/9] PCI: microchip: Clean up initialisation of interrupts daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 5/9] PCI: microchip: Gather MSI information from hardware config registers daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 6/9] PCI: microchip: Re-partition code between probe() and init() daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 7/9] PCI: microchip: Partition outbound address translation daire.mcnamara
2022-12-21 16:26 ` [PATCH v2 8/9] PCI: microchip: Partition inbound " daire.mcnamara
2022-12-22 5:30 ` kernel test robot
2022-12-30 19:52 ` Bjorn Helgaas
2022-12-21 16:26 ` [PATCH v2 9/9] riscv: dts: microchip: add parent ranges and dma-ranges for IKRD v2022.09 daire.mcnamara
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