[RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means

[Conor Dooley <conor@kernel.org>]

From: Conor Dooley <conor.dooley@microchip.com>

C'est la vie, the spec folks reserve the ability to make incompatible
changes between major versions of an extension. Their idea of backwards
compatibility appears driven by the hardware perspective - it's
backwards compatible if a later version is a subset of the existing
extension. IOW, if you supported `x` in vN, you still support `x` in
vN+1.
However in software terms, code that was built for the vN's `x`
extension may not work with the new definition.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index db5253a2a74a..405915b04d69 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -91,6 +91,9 @@ properties:
       Notably, riscv,isa was defined prior to the creation of the
       Zicsr and Zifencei extensions and thus "i" implies
       "zicsr_zifencei".
+      For the sake of backwards compatibility, an unversioned
+      extension means that the hart/platform is capable of
+      supporting version 1.0.0 of the extension.
 
       While the isa strings in ISA specification are case
       insensitive, letters in the riscv,isa string must be all
-- 
2.39.2