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From: Conor Dooley <conor@kernel.org>
To: palmer@dabbelt.com
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Andrew Jones <ajones@ventanamicro.com>,
	Sunil V L <sunilvl@ventanamicro.com>,
	Yangyu Chen <cyy@cyyself.name>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: [PATCH v3 3/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing
Date: Wed,  7 Jun 2023 21:28:27 +0100	[thread overview]
Message-ID: <20230607-guts-blurry-67e711acf328@spud> (raw)
In-Reply-To: <20230607-audacity-overhaul-82bb867a825f@spud>

From: Conor Dooley <conor.dooley@microchip.com>

Since riscv_fill_hwcap() now only iterates over possible cpus, the
basic validation of whether riscv,isa contains "rv<width>" can be moved
to riscv_early_of_processor_hartid().

Further, "ima" support is required by the kernel, so reject any CPU not
fitting the bill.

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/kernel/cpu.c        |  8 +++++---
 arch/riscv/kernel/cpufeature.c | 12 ++++++------
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 8025de06edb7..dfb4a2a61050 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -65,10 +65,12 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
 		pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart);
 		return -ENODEV;
 	}
-	if (tolower(isa[0]) != 'r' || tolower(isa[1]) != 'v') {
-		pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa);
+
+	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7))
+		return -ENODEV;
+
+	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7))
 		return -ENODEV;
-	}
 
 	return 0;
 }
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index c8635211fc18..c3851c8cfa9c 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -148,12 +148,12 @@ void __init riscv_fill_hwcap(void)
 			}
 		}
 
-		if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4))
-			continue;
-
-		if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4))
-			continue;
-
+		/*
+		 * For all possible cpus, we have already validated in
+		 * the boot process that they at least contain "rv" and
+		 * whichever of "32"/"64" this kernel supports, and so this
+		 * section can be skipped.
+		 */
 		isa += 4;
 
 		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
-- 
2.39.2


  parent reply	other threads:[~2023-06-07 20:29 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-07 20:28 [PATCH v3 0/7] ISA string parser cleanups Conor Dooley
2023-06-07 20:28 ` [PATCH v3 1/7] RISC-V: simplify register width check in ISA string parsing Conor Dooley
2023-06-12  7:07   ` Sunil V L
2023-06-07 20:28 ` [PATCH v3 2/7] RISC-V: split early & late of_node to hartid mapping Conor Dooley
2023-06-12  7:31   ` Sunil V L
2023-06-07 20:28 ` Conor Dooley [this message]
2023-06-12  7:33   ` [PATCH v3 3/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing Sunil V L
2023-06-07 20:28 ` [PATCH v3 4/7] RISC-V: rework comments in ISA string parser Conor Dooley
2023-06-07 20:28 ` [PATCH v3 5/7] RISC-V: remove decrement/increment dance " Conor Dooley
2023-06-12  7:52   ` Sunil V L
2023-06-07 20:28 ` [PATCH v3 6/7] dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support Conor Dooley
2023-06-14 23:02   ` Rob Herring
2023-06-07 20:28 ` [PATCH v3 7/7] RISC-V: always report presence of extensions formerly part of the base ISA Conor Dooley
2023-06-25 23:17 ` [PATCH v3 0/7] ISA string parser cleanups Palmer Dabbelt
2023-06-25 23:20 ` patchwork-bot+linux-riscv

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