* [PATCH V2 0/3] clk: sprd: Add reset controller driver for ums512
@ 2023-12-15 11:41 Zhifeng Tang
2023-12-15 11:41 ` [PATCH V2 1/3] dt-bindings: reset: Add reset controller bindings for Unisoc's ums512 Zhifeng Tang
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Zhifeng Tang @ 2023-12-15 11:41 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang,
Philipp Zabel
Cc: linux-clk, devicetree, linux-kernel, Zhifeng Tang, Wenming Wu
From: "zhifeng.tang" <zhifeng.tang@unisoc.com>
Add reset controller driver for ums512,The reset register has
the same base address as the gate register.
Changes in v2:
- The binding files are combined into one patch
zhifeng.tang (3):
dt-bindings: reset: Add reset controller bindings for Unisoc's ums512
clk: sprd: Add reset controller driver for ums512
arm64: dts: sprd: Add reset controller driver for UMS512
.../bindings/clock/sprd,ums512-clk.yaml | 3 +
arch/arm64/boot/dts/sprd/ums512.dtsi | 9 +
drivers/clk/sprd/Makefile | 1 +
drivers/clk/sprd/common.c | 1 +
drivers/clk/sprd/common.h | 2 +
drivers/clk/sprd/reset.c | 78 ++++++
drivers/clk/sprd/reset.h | 30 +++
drivers/clk/sprd/ums512-clk.c | 240 ++++++++++++++++++
include/dt-bindings/reset/sprd,ums512-reset.h | 203 +++++++++++++++
9 files changed, 567 insertions(+)
create mode 100644 drivers/clk/sprd/reset.c
create mode 100644 drivers/clk/sprd/reset.h
create mode 100644 include/dt-bindings/reset/sprd,ums512-reset.h
--
2.17.1
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH V2 1/3] dt-bindings: reset: Add reset controller bindings for Unisoc's ums512 2023-12-15 11:41 [PATCH V2 0/3] clk: sprd: Add reset controller driver for ums512 Zhifeng Tang @ 2023-12-15 11:41 ` Zhifeng Tang 2023-12-16 12:40 ` Conor Dooley 2023-12-15 11:41 ` [PATCH V2 2/3] clk: sprd: Add reset controller driver for ums512 Zhifeng Tang 2023-12-15 11:41 ` [PATCH V2 3/3] arm64: dts: sprd: Add reset controller driver for UMS512 Zhifeng Tang 2 siblings, 1 reply; 5+ messages in thread From: Zhifeng Tang @ 2023-12-15 11:41 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang, Philipp Zabel Cc: linux-clk, devicetree, linux-kernel, Zhifeng Tang, Wenming Wu From: "zhifeng.tang" <zhifeng.tang@unisoc.com> Add reset controller bindings to clock bindings for Unisoc's ums512. Signed-off-by: zhifeng.tang <zhifeng.tang@unisoc.com> --- .../bindings/clock/sprd,ums512-clk.yaml | 3 + include/dt-bindings/reset/sprd,ums512-reset.h | 203 ++++++++++++++++++ 2 files changed, 206 insertions(+) create mode 100644 include/dt-bindings/reset/sprd,ums512-reset.h diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml index 43d2b6c31357..6b0892d637fe 100644 --- a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml @@ -34,6 +34,9 @@ properties: "#clock-cells": const: 1 + "#reset-cells": + const: 1 + clocks: minItems: 1 maxItems: 4 diff --git a/include/dt-bindings/reset/sprd,ums512-reset.h b/include/dt-bindings/reset/sprd,ums512-reset.h new file mode 100644 index 000000000000..d7ec3dd7c291 --- /dev/null +++ b/include/dt-bindings/reset/sprd,ums512-reset.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2022, Unisoc Inc. + */ + +#ifndef __DT_BINDINGS_SPRD_UMS512_RESET_H +#define __DT_BINDINGS_SPRD_UMS512_RESET_H + +/* PMU APB resets */ +#define RESET_PMU_APB_WTLCP_SOFT_RST 0 +#define RESET_PMU_APB_PUBCP_SOFT_RST 1 +#define RESET_PMU_APB_WTLCP_DSP_SOFT_RST 2 +#define RESET_PMU_APB_MM_SOFT_RST 3 +#define RESET_PMU_APB_GPU_SOFT_RST 4 +#define RESET_PMU_APB_AP_SOFT_RST 5 +#define RESET_PMU_APB_PUB_SOFT_RST 6 +#define RESET_PMU_APB_APCPU_SOFT_RST 7 +#define RESET_PMU_APB_SP_SYS_SOFT_RST 8 +#define RESET_PMU_APB_AUDCP_SYS_SOFT_RST 9 +#define RESET_PMU_APB_AUDCP_AUDDSP_SOFT_RST 10 +#define RESET_PMU_APB_CDMA_SOFT_RST 11 +#define RESET_PMU_APB_WTLCP_AON_SOFT_RST 12 +#define RESET_PMU_APB_WCDMA_AON_SOFT_RST 13 +#define RESET_PMU_APB_WTLCP_LDSP_SOFT_RST 14 +#define RESET_PMU_APB_WTLCP_TGDSP_SOFT_RST 15 +#define RESET_PMU_APB_AP_VSP_SOFT_RST 16 +#define RESET_PMU_APB_AP_VDSP_SOFT_RST 17 +#define RESET_PMU_APB_APCPU_CORE0_MODE_ST_SOFT_RST 18 +#define RESET_PMU_APB_APCPU_CORE1_MODE_ST_SOFT_RST 19 +#define RESET_PMU_APB_APCPU_CORE2_MODE_ST_SOFT_RST 20 +#define RESET_PMU_APB_APCPU_CORE3_MODE_ST_SOFT_RST 21 +#define RESET_PMU_APB_APCPU_CORE4_MODE_ST_SOFT_RST 22 +#define RESET_PMU_APB_APCPU_CORE5_MODE_ST_SOFT_RST 23 +#define RESET_PMU_APB_APCPU_CORE6_MODE_ST_SOFT_RST 24 +#define RESET_PMU_APB_APCPU_CORE7_MODE_ST_SOFT_RST 25 +#define RESET_PMU_APB_APCPU_CLUSTER_MODE_ST_SOFT_RST 26 + +/* AP APB resets */ +#define RESET_AP_APB_SIM0_SOFT_RST 0 +#define RESET_AP_APB_IIS0_SOFT_RST 1 +#define RESET_AP_APB_IIS1_SOFT_RST 2 +#define RESET_AP_APB_IIS2_SOFT_RST 3 +#define RESET_AP_APB_SPI0_SOFT_RST 4 +#define RESET_AP_APB_SPI1_SOFT_RST 5 +#define RESET_AP_APB_SPI2_SOFT_RST 6 +#define RESET_AP_APB_SPI3_SOFT_RST 7 +#define RESET_AP_APB_I2C0_SOFT_RST 8 +#define RESET_AP_APB_I2C1_SOFT_RST 9 +#define RESET_AP_APB_I2C2_SOFT_RST 10 +#define RESET_AP_APB_I2C3_SOFT_RST 11 +#define RESET_AP_APB_I2C4_SOFT_RST 12 +#define RESET_AP_APB_UART0_SOFT_RST 13 +#define RESET_AP_APB_UART1_SOFT_RST 14 +#define RESET_AP_APB_UART2_SOFT_RST 15 +#define RESET_AP_APB_SDIO0_SOFT_RST 16 +#define RESET_AP_APB_SDIO1_SOFT_RST 17 +#define RESET_AP_APB_SDIO2_SOFT_RST 18 +#define RESET_AP_APB_EMMC_SOFT_RST 19 +#define RESET_AP_APB_CE_SEC_SOFT_RST 20 +#define RESET_AP_APB_CE_PUB_SOFT_RST 21 +#define RESET_AP_APB_AP_DVFS_SOFT_RST 22 + +/* AP AHB resets */ +#define RESET_AP_AHB_DSI_SOFT_RST 0 +#define RESET_AP_AHB_DISPC_SOFT_RST 1 +#define RESET_AP_AHB_VDSP_IDMA_VAU_SOFT_RST 2 +#define RESET_AP_AHB_VDSP_MSTD_VAU_SOFT_RST 3 +#define RESET_AP_AHB_VDSP_MSTI_VAU_SOFT_RST 4 +#define RESET_AP_AHB_VDMA_VAU_SOFT_RST 5 +#define RESET_AP_AHB_IPI_SOFT_RST 6 +#define RESET_AP_AHB_VDMA_SOFT_RST 7 +#define RESET_AP_AHB_DMA_SOFT_RST 8 +#define RESET_AP_AHB_VDSP_SOFT_RST 9 +#define RESET_AP_AHB_VDSP_DEBUG_SOFT_RST 10 +#define RESET_AP_AHB_VSP_GLOBAL_SOFT_RST 11 +#define RESET_AP_AHB_VPP_SOFT_RST 12 +#define RESET_AP_AHB_VSP_SOFT_RST 13 +#define RESET_AP_AHB_DISPC_VAU_SOFT_RST 14 + +/* AON APB resets */ +#define RESET_AON_APB_RC100M_CAL_SOFT_RST 0 +#define RESET_AON_APB_RFTI_SOFT_RST 1 +#define RESET_AON_APB_DCXO_LC_SOFT_RST 2 +#define RESET_AON_APB_BB_CAL_SOFT_RST 3 +#define RESET_AON_APB_MSPI0_SOFT_RST 4 +#define RESET_AON_APB_MSPI1_SOFT_RST 5 +#define RESET_AON_APB_DAP_MTX_SOFT_RST 6 +#define RESET_AON_APB_LVDSDIS_SOFT_RST 7 +#define RESET_AON_APB_SERDES_DPHY_SOFT_RST 8 +#define RESET_AON_APB_SERDES_DPHY_APB_SOFT_RST 9 +#define RESET_AON_APB_AP_EMMC_SOFT_RST 10 +#define RESET_AON_APB_AP_SDIO0_SOFT_RST 11 +#define RESET_AON_APB_AP_SDIO1_SOFT_RST 12 +#define RESET_AON_APB_AP_SDIO2_SOFT_RST 13 +#define RESET_AON_APB_PUBCP_SDIO0_SOFT_RST 14 +#define RESET_AON_APB_EFUSE_SOFT_RST 15 +#define RESET_AON_APB_GPIO_SOFT_RST 16 +#define RESET_AON_APB_MBOX_SOFT_RST 17 +#define RESET_AON_APB_KPD_SOFT_RST 18 +#define RESET_AON_APB_AON_SYST_SOFT_RST 19 +#define RESET_AON_APB_AP_SYST_SOFT_RST 20 +#define RESET_AON_APB_AON_TMR_SOFT_RST 21 +#define RESET_AON_APB_DVFS_TOP_SOFT_RST 22 +#define RESET_AON_APB_OTG_UTMI_SOFT_RST 23 +#define RESET_AON_APB_OTG_PHY_SOFT_RST 24 +#define RESET_AON_APB_SPLK_SOFT_RST 25 +#define RESET_AON_APB_PIN_SOFT_RST 26 +#define RESET_AON_APB_ANA_SOFT_RST 27 +#define RESET_AON_APB_CKG_SOFT_RST 28 +#define RESET_AON_APB_ETC_SOFT_RST 29 +#define RESET_AON_APB_APCPU_TS0_SOFT_RST 30 +#define RESET_AON_APB_APB_BUSMON_SOFT_RST 31 +#define RESET_AON_APB_AON_IIS_SOFT_RST 32 +#define RESET_AON_APB_SCC_SOFT_RST 33 +#define RESET_AON_APB_THM0_SOFT_RST 34 +#define RESET_AON_APB_THM1_SOFT_RST 35 +#define RESET_AON_APB_THM2_SOFT_RST 36 +#define RESET_AON_APB_AP_SIM_AON_TOP_SOFT_RST 37 +#define RESET_AON_APB_PUBCP_SIM0_AON_TOP_SOFT_RST 38 +#define RESET_AON_APB_PUBCP_SIM1_AON_TOP_SOFT_RST 39 +#define RESET_AON_APB_PUBCP_SIM2_AON_TOP_SOFT_RST 40 +#define RESET_AON_APB_I2C_SOFT_RST 41 +#define RESET_AON_APB_PMU_SOFT_RST 42 +#define RESET_AON_APB_ADI_SOFT_RST 43 +#define RESET_AON_APB_EIC_SOFT_RST 44 +#define RESET_AON_APB_AP_INTC0_SOFT_RST 45 +#define RESET_AON_APB_AP_INTC1_SOFT_RST 46 +#define RESET_AON_APB_AP_INTC2_SOFT_RST 47 +#define RESET_AON_APB_AP_INTC3_SOFT_RST 48 +#define RESET_AON_APB_AP_INTC4_SOFT_RST 49 +#define RESET_AON_APB_AP_INTC5_SOFT_RST 50 +#define RESET_AON_APB_AUDCP_INTC_SOFT_RST 51 +#define RESET_AON_APB_PUBCP_INTC_SOFT_RST 52 +#define RESET_AON_APB_WTLCP_TGDSP_INTC_SOFT_RST 53 +#define RESET_AON_APB_WTLCP_LDSP_INTC_SOFT_RST 54 +#define RESET_AON_APB_WTLCP_INTC_SOFT_RST 55 +#define RESET_AON_APB_AP_TMR0_SOFT_RST 56 +#define RESET_AON_APB_AP_TMR1_SOFT_RST 57 +#define RESET_AON_APB_AP_TMR2_SOFT_RST 58 +#define RESET_AON_APB_PWM0_SOFT_RST 59 +#define RESET_AON_APB_PWM1_SOFT_RST 60 +#define RESET_AON_APB_PWM2_SOFT_RST 61 +#define RESET_AON_APB_PWM3_SOFT_RST 62 +#define RESET_AON_APB_AP_WDG_SOFT_RST 63 +#define RESET_AON_APB_APCPU_WDG_SOFT_RST 64 +#define RESET_AON_APB_SERDES_SOFT_RST 65 +#define RESET_AON_APB_DJTAG_SOFT_RST 66 + +/* AUDCP APB resets */ +#define RESET_AUDCP_APB_WDG_SOFT_RST 0 +#define RESET_AUDCP_APB_TMR0_SOFT_RST 1 +#define RESET_AUDCP_APB_TMR1_SOFT_RST 2 + +/* AUDCP AHB resets */ +#define RESET_AUDCP_AHB_VBC_24M_SOFT_RST 0 +#define RESET_AUDCP_AHB_DMA_AP_SOFT_RST 1 +#define RESET_AUDCP_AHB_SRC48K_SOFT_RST 2 +#define RESET_AUDCP_AHB_MCDT_SOFT_RST 3 +#define RESET_AUDCP_AHB_VBCIFD_SOFT_RST 4 +#define RESET_AUDCP_AHB_VBC_SOFT_RST 5 +#define RESET_AUDCP_AHB_SPINLOCK_SOFT_RST 6 +#define RESET_AUDCP_AHB_DMA_CP_SOFT_RST 7 +#define RESET_AUDCP_AHB_IIS0_SOFT_RST 8 +#define RESET_AUDCP_AHB_IIS1_SOFT_RST 9 +#define RESET_AUDCP_AHB_IIS2_SOFT_RST 10 +#define RESET_AUDCP_AHB_UART_SOFT_RST 11 +#define RESET_AUDCP_AHB_AUD_SOFT_RST 12 +#define RESET_AUDCP_AHB_DVFS_SOFT_RST 13 + +/* GPU APB resets */ +#define RESET_GPU_APB_GPU_CORE_SOFT_RST 0 +#define RESET_GPU_APB_SYS_SOFT_RST_REQ_CORE 1 + +/* MM AHB resets */ +#define RESET_MM_AHB_CKG_SOFT_RST 0 +#define RESET_MM_AHB_JPG_SOFT_RST 1 +#define RESET_MM_AHB_DCAM_AXI_SOFT_RST 2 +#define RESET_MM_AHB_DCAM2_SOFT_RST 3 +#define RESET_MM_AHB_DCAM1_SOFT_RST 4 +#define RESET_MM_AHB_DCAM0_SOFT_RST 5 +#define RESET_MM_AHB_DCAM_VAU_SOFT_RST 6 +#define RESET_MM_AHB_MIPI_CSI2_SOFT_RST 7 +#define RESET_MM_AHB_MIPI_CSI1_SOFT_RST 8 +#define RESET_MM_AHB_MIPI_CSI0_SOFT_RST 9 +#define RESET_MM_AHB_ISP_SOFT_RST 10 +#define RESET_MM_AHB_ISP_VAU_SOFT_RST 11 +#define RESET_MM_AHB_ISP_AHB_SOFT_RST 12 +#define RESET_MM_AHB_CPP_DMA_SOFT_RST 13 +#define RESET_MM_AHB_CPP_PATH1_SOFT_RST 14 +#define RESET_MM_AHB_CPP_PATH0_SOFT_RST 15 +#define RESET_MM_AHB_CPP_SOFT_RST 16 +#define RESET_MM_AHB_MM_MAIN_SOFT_RST 17 +#define RESET_MM_AHB_CPP_SOFT_RST_MASK 18 +#define RESET_MM_AHB_JPG_SOFT_RST_MASK 19 +#define RESET_MM_AHB_JPG_VAU_SOFT_RST 20 +#define RESET_MM_AHB_CPP_VAU_SOFT_RST 21 +#define RESET_MM_AHB_FD_VAU_SOFT_RST 22 +#define RESET_MM_AHB_DCAM_ALL_SOFT_RST 23 +#define RESET_MM_AHB_DVFS_SOFT_RST 24 +#define RESET_MM_AHB_FD_SOFT_RST 25 +#define RESET_MM_AHB_FD_SOFT_RST_MASK 26 + +#endif /* __DT_BINDINGS_SPRD_UMS512_RESET_H */ -- 2.17.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH V2 1/3] dt-bindings: reset: Add reset controller bindings for Unisoc's ums512 2023-12-15 11:41 ` [PATCH V2 1/3] dt-bindings: reset: Add reset controller bindings for Unisoc's ums512 Zhifeng Tang @ 2023-12-16 12:40 ` Conor Dooley 0 siblings, 0 replies; 5+ messages in thread From: Conor Dooley @ 2023-12-16 12:40 UTC (permalink / raw) To: Zhifeng Tang Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang, Philipp Zabel, linux-clk, devicetree, linux-kernel, Zhifeng Tang, Wenming Wu [-- Attachment #1: Type: text/plain, Size: 10252 bytes --] On Fri, Dec 15, 2023 at 07:41:27PM +0800, Zhifeng Tang wrote: > From: "zhifeng.tang" <zhifeng.tang@unisoc.com> > > Add reset controller bindings to clock bindings for Unisoc's ums512. I guess I replied to v1 and v2 was sent within the time period I am capable of clearing my queue. Same comments apply here. > > Signed-off-by: zhifeng.tang <zhifeng.tang@unisoc.com> > --- > .../bindings/clock/sprd,ums512-clk.yaml | 3 + > include/dt-bindings/reset/sprd,ums512-reset.h | 203 ++++++++++++++++++ > 2 files changed, 206 insertions(+) > create mode 100644 include/dt-bindings/reset/sprd,ums512-reset.h > > diff --git a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml > index 43d2b6c31357..6b0892d637fe 100644 > --- a/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml > +++ b/Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml > @@ -34,6 +34,9 @@ properties: > "#clock-cells": > const: 1 > > + "#reset-cells": > + const: 1 > + > clocks: > minItems: 1 > maxItems: 4 > diff --git a/include/dt-bindings/reset/sprd,ums512-reset.h b/include/dt-bindings/reset/sprd,ums512-reset.h > new file mode 100644 > index 000000000000..d7ec3dd7c291 > --- /dev/null > +++ b/include/dt-bindings/reset/sprd,ums512-reset.h > @@ -0,0 +1,203 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ > +/* > + * Copyright (C) 2022, Unisoc Inc. > + */ > + > +#ifndef __DT_BINDINGS_SPRD_UMS512_RESET_H > +#define __DT_BINDINGS_SPRD_UMS512_RESET_H > + > +/* PMU APB resets */ > +#define RESET_PMU_APB_WTLCP_SOFT_RST 0 > +#define RESET_PMU_APB_PUBCP_SOFT_RST 1 > +#define RESET_PMU_APB_WTLCP_DSP_SOFT_RST 2 > +#define RESET_PMU_APB_MM_SOFT_RST 3 > +#define RESET_PMU_APB_GPU_SOFT_RST 4 > +#define RESET_PMU_APB_AP_SOFT_RST 5 > +#define RESET_PMU_APB_PUB_SOFT_RST 6 > +#define RESET_PMU_APB_APCPU_SOFT_RST 7 > +#define RESET_PMU_APB_SP_SYS_SOFT_RST 8 > +#define RESET_PMU_APB_AUDCP_SYS_SOFT_RST 9 > +#define RESET_PMU_APB_AUDCP_AUDDSP_SOFT_RST 10 > +#define RESET_PMU_APB_CDMA_SOFT_RST 11 > +#define RESET_PMU_APB_WTLCP_AON_SOFT_RST 12 > +#define RESET_PMU_APB_WCDMA_AON_SOFT_RST 13 > +#define RESET_PMU_APB_WTLCP_LDSP_SOFT_RST 14 > +#define RESET_PMU_APB_WTLCP_TGDSP_SOFT_RST 15 > +#define RESET_PMU_APB_AP_VSP_SOFT_RST 16 > +#define RESET_PMU_APB_AP_VDSP_SOFT_RST 17 > +#define RESET_PMU_APB_APCPU_CORE0_MODE_ST_SOFT_RST 18 > +#define RESET_PMU_APB_APCPU_CORE1_MODE_ST_SOFT_RST 19 > +#define RESET_PMU_APB_APCPU_CORE2_MODE_ST_SOFT_RST 20 > +#define RESET_PMU_APB_APCPU_CORE3_MODE_ST_SOFT_RST 21 > +#define RESET_PMU_APB_APCPU_CORE4_MODE_ST_SOFT_RST 22 > +#define RESET_PMU_APB_APCPU_CORE5_MODE_ST_SOFT_RST 23 > +#define RESET_PMU_APB_APCPU_CORE6_MODE_ST_SOFT_RST 24 > +#define RESET_PMU_APB_APCPU_CORE7_MODE_ST_SOFT_RST 25 > +#define RESET_PMU_APB_APCPU_CLUSTER_MODE_ST_SOFT_RST 26 > + > +/* AP APB resets */ > +#define RESET_AP_APB_SIM0_SOFT_RST 0 > +#define RESET_AP_APB_IIS0_SOFT_RST 1 > +#define RESET_AP_APB_IIS1_SOFT_RST 2 > +#define RESET_AP_APB_IIS2_SOFT_RST 3 > +#define RESET_AP_APB_SPI0_SOFT_RST 4 > +#define RESET_AP_APB_SPI1_SOFT_RST 5 > +#define RESET_AP_APB_SPI2_SOFT_RST 6 > +#define RESET_AP_APB_SPI3_SOFT_RST 7 > +#define RESET_AP_APB_I2C0_SOFT_RST 8 > +#define RESET_AP_APB_I2C1_SOFT_RST 9 > +#define RESET_AP_APB_I2C2_SOFT_RST 10 > +#define RESET_AP_APB_I2C3_SOFT_RST 11 > +#define RESET_AP_APB_I2C4_SOFT_RST 12 > +#define RESET_AP_APB_UART0_SOFT_RST 13 > +#define RESET_AP_APB_UART1_SOFT_RST 14 > +#define RESET_AP_APB_UART2_SOFT_RST 15 > +#define RESET_AP_APB_SDIO0_SOFT_RST 16 > +#define RESET_AP_APB_SDIO1_SOFT_RST 17 > +#define RESET_AP_APB_SDIO2_SOFT_RST 18 > +#define RESET_AP_APB_EMMC_SOFT_RST 19 > +#define RESET_AP_APB_CE_SEC_SOFT_RST 20 > +#define RESET_AP_APB_CE_PUB_SOFT_RST 21 > +#define RESET_AP_APB_AP_DVFS_SOFT_RST 22 > + > +/* AP AHB resets */ > +#define RESET_AP_AHB_DSI_SOFT_RST 0 > +#define RESET_AP_AHB_DISPC_SOFT_RST 1 > +#define RESET_AP_AHB_VDSP_IDMA_VAU_SOFT_RST 2 > +#define RESET_AP_AHB_VDSP_MSTD_VAU_SOFT_RST 3 > +#define RESET_AP_AHB_VDSP_MSTI_VAU_SOFT_RST 4 > +#define RESET_AP_AHB_VDMA_VAU_SOFT_RST 5 > +#define RESET_AP_AHB_IPI_SOFT_RST 6 > +#define RESET_AP_AHB_VDMA_SOFT_RST 7 > +#define RESET_AP_AHB_DMA_SOFT_RST 8 > +#define RESET_AP_AHB_VDSP_SOFT_RST 9 > +#define RESET_AP_AHB_VDSP_DEBUG_SOFT_RST 10 > +#define RESET_AP_AHB_VSP_GLOBAL_SOFT_RST 11 > +#define RESET_AP_AHB_VPP_SOFT_RST 12 > +#define RESET_AP_AHB_VSP_SOFT_RST 13 > +#define RESET_AP_AHB_DISPC_VAU_SOFT_RST 14 > + > +/* AON APB resets */ > +#define RESET_AON_APB_RC100M_CAL_SOFT_RST 0 > +#define RESET_AON_APB_RFTI_SOFT_RST 1 > +#define RESET_AON_APB_DCXO_LC_SOFT_RST 2 > +#define RESET_AON_APB_BB_CAL_SOFT_RST 3 > +#define RESET_AON_APB_MSPI0_SOFT_RST 4 > +#define RESET_AON_APB_MSPI1_SOFT_RST 5 > +#define RESET_AON_APB_DAP_MTX_SOFT_RST 6 > +#define RESET_AON_APB_LVDSDIS_SOFT_RST 7 > +#define RESET_AON_APB_SERDES_DPHY_SOFT_RST 8 > +#define RESET_AON_APB_SERDES_DPHY_APB_SOFT_RST 9 > +#define RESET_AON_APB_AP_EMMC_SOFT_RST 10 > +#define RESET_AON_APB_AP_SDIO0_SOFT_RST 11 > +#define RESET_AON_APB_AP_SDIO1_SOFT_RST 12 > +#define RESET_AON_APB_AP_SDIO2_SOFT_RST 13 > +#define RESET_AON_APB_PUBCP_SDIO0_SOFT_RST 14 > +#define RESET_AON_APB_EFUSE_SOFT_RST 15 > +#define RESET_AON_APB_GPIO_SOFT_RST 16 > +#define RESET_AON_APB_MBOX_SOFT_RST 17 > +#define RESET_AON_APB_KPD_SOFT_RST 18 > +#define RESET_AON_APB_AON_SYST_SOFT_RST 19 > +#define RESET_AON_APB_AP_SYST_SOFT_RST 20 > +#define RESET_AON_APB_AON_TMR_SOFT_RST 21 > +#define RESET_AON_APB_DVFS_TOP_SOFT_RST 22 > +#define RESET_AON_APB_OTG_UTMI_SOFT_RST 23 > +#define RESET_AON_APB_OTG_PHY_SOFT_RST 24 > +#define RESET_AON_APB_SPLK_SOFT_RST 25 > +#define RESET_AON_APB_PIN_SOFT_RST 26 > +#define RESET_AON_APB_ANA_SOFT_RST 27 > +#define RESET_AON_APB_CKG_SOFT_RST 28 > +#define RESET_AON_APB_ETC_SOFT_RST 29 > +#define RESET_AON_APB_APCPU_TS0_SOFT_RST 30 > +#define RESET_AON_APB_APB_BUSMON_SOFT_RST 31 > +#define RESET_AON_APB_AON_IIS_SOFT_RST 32 > +#define RESET_AON_APB_SCC_SOFT_RST 33 > +#define RESET_AON_APB_THM0_SOFT_RST 34 > +#define RESET_AON_APB_THM1_SOFT_RST 35 > +#define RESET_AON_APB_THM2_SOFT_RST 36 > +#define RESET_AON_APB_AP_SIM_AON_TOP_SOFT_RST 37 > +#define RESET_AON_APB_PUBCP_SIM0_AON_TOP_SOFT_RST 38 > +#define RESET_AON_APB_PUBCP_SIM1_AON_TOP_SOFT_RST 39 > +#define RESET_AON_APB_PUBCP_SIM2_AON_TOP_SOFT_RST 40 > +#define RESET_AON_APB_I2C_SOFT_RST 41 > +#define RESET_AON_APB_PMU_SOFT_RST 42 > +#define RESET_AON_APB_ADI_SOFT_RST 43 > +#define RESET_AON_APB_EIC_SOFT_RST 44 > +#define RESET_AON_APB_AP_INTC0_SOFT_RST 45 > +#define RESET_AON_APB_AP_INTC1_SOFT_RST 46 > +#define RESET_AON_APB_AP_INTC2_SOFT_RST 47 > +#define RESET_AON_APB_AP_INTC3_SOFT_RST 48 > +#define RESET_AON_APB_AP_INTC4_SOFT_RST 49 > +#define RESET_AON_APB_AP_INTC5_SOFT_RST 50 > +#define RESET_AON_APB_AUDCP_INTC_SOFT_RST 51 > +#define RESET_AON_APB_PUBCP_INTC_SOFT_RST 52 > +#define RESET_AON_APB_WTLCP_TGDSP_INTC_SOFT_RST 53 > +#define RESET_AON_APB_WTLCP_LDSP_INTC_SOFT_RST 54 > +#define RESET_AON_APB_WTLCP_INTC_SOFT_RST 55 > +#define RESET_AON_APB_AP_TMR0_SOFT_RST 56 > +#define RESET_AON_APB_AP_TMR1_SOFT_RST 57 > +#define RESET_AON_APB_AP_TMR2_SOFT_RST 58 > +#define RESET_AON_APB_PWM0_SOFT_RST 59 > +#define RESET_AON_APB_PWM1_SOFT_RST 60 > +#define RESET_AON_APB_PWM2_SOFT_RST 61 > +#define RESET_AON_APB_PWM3_SOFT_RST 62 > +#define RESET_AON_APB_AP_WDG_SOFT_RST 63 > +#define RESET_AON_APB_APCPU_WDG_SOFT_RST 64 > +#define RESET_AON_APB_SERDES_SOFT_RST 65 > +#define RESET_AON_APB_DJTAG_SOFT_RST 66 > + > +/* AUDCP APB resets */ > +#define RESET_AUDCP_APB_WDG_SOFT_RST 0 > +#define RESET_AUDCP_APB_TMR0_SOFT_RST 1 > +#define RESET_AUDCP_APB_TMR1_SOFT_RST 2 > + > +/* AUDCP AHB resets */ > +#define RESET_AUDCP_AHB_VBC_24M_SOFT_RST 0 > +#define RESET_AUDCP_AHB_DMA_AP_SOFT_RST 1 > +#define RESET_AUDCP_AHB_SRC48K_SOFT_RST 2 > +#define RESET_AUDCP_AHB_MCDT_SOFT_RST 3 > +#define RESET_AUDCP_AHB_VBCIFD_SOFT_RST 4 > +#define RESET_AUDCP_AHB_VBC_SOFT_RST 5 > +#define RESET_AUDCP_AHB_SPINLOCK_SOFT_RST 6 > +#define RESET_AUDCP_AHB_DMA_CP_SOFT_RST 7 > +#define RESET_AUDCP_AHB_IIS0_SOFT_RST 8 > +#define RESET_AUDCP_AHB_IIS1_SOFT_RST 9 > +#define RESET_AUDCP_AHB_IIS2_SOFT_RST 10 > +#define RESET_AUDCP_AHB_UART_SOFT_RST 11 > +#define RESET_AUDCP_AHB_AUD_SOFT_RST 12 > +#define RESET_AUDCP_AHB_DVFS_SOFT_RST 13 > + > +/* GPU APB resets */ > +#define RESET_GPU_APB_GPU_CORE_SOFT_RST 0 > +#define RESET_GPU_APB_SYS_SOFT_RST_REQ_CORE 1 > + > +/* MM AHB resets */ > +#define RESET_MM_AHB_CKG_SOFT_RST 0 > +#define RESET_MM_AHB_JPG_SOFT_RST 1 > +#define RESET_MM_AHB_DCAM_AXI_SOFT_RST 2 > +#define RESET_MM_AHB_DCAM2_SOFT_RST 3 > +#define RESET_MM_AHB_DCAM1_SOFT_RST 4 > +#define RESET_MM_AHB_DCAM0_SOFT_RST 5 > +#define RESET_MM_AHB_DCAM_VAU_SOFT_RST 6 > +#define RESET_MM_AHB_MIPI_CSI2_SOFT_RST 7 > +#define RESET_MM_AHB_MIPI_CSI1_SOFT_RST 8 > +#define RESET_MM_AHB_MIPI_CSI0_SOFT_RST 9 > +#define RESET_MM_AHB_ISP_SOFT_RST 10 > +#define RESET_MM_AHB_ISP_VAU_SOFT_RST 11 > +#define RESET_MM_AHB_ISP_AHB_SOFT_RST 12 > +#define RESET_MM_AHB_CPP_DMA_SOFT_RST 13 > +#define RESET_MM_AHB_CPP_PATH1_SOFT_RST 14 > +#define RESET_MM_AHB_CPP_PATH0_SOFT_RST 15 > +#define RESET_MM_AHB_CPP_SOFT_RST 16 > +#define RESET_MM_AHB_MM_MAIN_SOFT_RST 17 > +#define RESET_MM_AHB_CPP_SOFT_RST_MASK 18 > +#define RESET_MM_AHB_JPG_SOFT_RST_MASK 19 > +#define RESET_MM_AHB_JPG_VAU_SOFT_RST 20 > +#define RESET_MM_AHB_CPP_VAU_SOFT_RST 21 > +#define RESET_MM_AHB_FD_VAU_SOFT_RST 22 > +#define RESET_MM_AHB_DCAM_ALL_SOFT_RST 23 > +#define RESET_MM_AHB_DVFS_SOFT_RST 24 > +#define RESET_MM_AHB_FD_SOFT_RST 25 > +#define RESET_MM_AHB_FD_SOFT_RST_MASK 26 > + > +#endif /* __DT_BINDINGS_SPRD_UMS512_RESET_H */ > -- > 2.17.1 > > [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH V2 2/3] clk: sprd: Add reset controller driver for ums512 2023-12-15 11:41 [PATCH V2 0/3] clk: sprd: Add reset controller driver for ums512 Zhifeng Tang 2023-12-15 11:41 ` [PATCH V2 1/3] dt-bindings: reset: Add reset controller bindings for Unisoc's ums512 Zhifeng Tang @ 2023-12-15 11:41 ` Zhifeng Tang 2023-12-15 11:41 ` [PATCH V2 3/3] arm64: dts: sprd: Add reset controller driver for UMS512 Zhifeng Tang 2 siblings, 0 replies; 5+ messages in thread From: Zhifeng Tang @ 2023-12-15 11:41 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang, Philipp Zabel Cc: linux-clk, devicetree, linux-kernel, Zhifeng Tang, Wenming Wu From: "zhifeng.tang" <zhifeng.tang@unisoc.com> Add reset controller driver for ums512,The reset register has the same base address as the gate register. Signed-off-by: zhifeng.tang <zhifeng.tang@unisoc.com> --- drivers/clk/sprd/Makefile | 1 + drivers/clk/sprd/common.c | 1 + drivers/clk/sprd/common.h | 2 + drivers/clk/sprd/reset.c | 78 +++++++++++ drivers/clk/sprd/reset.h | 30 +++++ drivers/clk/sprd/ums512-clk.c | 240 ++++++++++++++++++++++++++++++++++ 6 files changed, 352 insertions(+) create mode 100644 drivers/clk/sprd/reset.c create mode 100644 drivers/clk/sprd/reset.h diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile index f25b2c3904fb..72f6ecf8291e 100644 --- a/drivers/clk/sprd/Makefile +++ b/drivers/clk/sprd/Makefile @@ -7,6 +7,7 @@ clk-sprd-y += mux.o clk-sprd-y += div.o clk-sprd-y += composite.o clk-sprd-y += pll.o +clk-sprd-y += reset.o ## SoC support obj-$(CONFIG_SPRD_SC9860_CLK) += sc9860-clk.o diff --git a/drivers/clk/sprd/common.c b/drivers/clk/sprd/common.c index 762f0961f17f..4ddec6348447 100644 --- a/drivers/clk/sprd/common.c +++ b/drivers/clk/sprd/common.c @@ -75,6 +75,7 @@ int sprd_clk_regmap_init(struct platform_device *pdev, } sprd_clk_set_regmap(desc, regmap); + platform_set_drvdata(pdev, regmap); return 0; } diff --git a/drivers/clk/sprd/common.h b/drivers/clk/sprd/common.h index 1d077b39cef6..1ac39af68497 100644 --- a/drivers/clk/sprd/common.h +++ b/drivers/clk/sprd/common.h @@ -24,6 +24,8 @@ struct sprd_clk_desc { struct sprd_clk_common **clk_clks; unsigned long num_clk_clks; struct clk_hw_onecell_data *hw_clks; + struct sprd_reset_map *resets; + unsigned long num_resets; }; static inline struct sprd_clk_common * diff --git a/drivers/clk/sprd/reset.c b/drivers/clk/sprd/reset.c new file mode 100644 index 000000000000..92d19465b531 --- /dev/null +++ b/drivers/clk/sprd/reset.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Spreadtrum reset clock driver +// +// Copyright (C) 2022 Spreadtrum, Inc. +// Author: Zhifeng Tang <zhifeng.tang@unisoc.com> + +#include <linux/delay.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#include "reset.h" + +static inline struct sprd_reset *to_sprd_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct sprd_reset, rcdev); +} + +static int sprd_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct sprd_reset *reset = to_sprd_reset(rcdev); + const struct sprd_reset_map *map = &reset->reset_map[id]; + unsigned int offset = map->sc_offset; + unsigned long flags; + unsigned int val; + + if (map->sc) { + regmap_write(reset->regmap, map->reg + offset, map->mask); + } else { + spin_lock_irqsave(&reset->lock, flags); + regmap_read(reset->regmap, map->reg, &val); + val |= map->mask; + regmap_write(reset->regmap, map->reg, val); + spin_unlock_irqrestore(&reset->lock, flags); + } + + return 0; +} + +static int sprd_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct sprd_reset *reset = to_sprd_reset(rcdev); + const struct sprd_reset_map *map = &reset->reset_map[id]; + unsigned int offset = map->sc_offset * 2; + unsigned long flags; + unsigned int val; + + if (map->sc) { + regmap_write(reset->regmap, map->reg + offset, map->mask); + } else { + spin_lock_irqsave(&reset->lock, flags); + regmap_read(reset->regmap, map->reg, &val); + val &= ~map->mask; + regmap_write(reset->regmap, map->reg, val); + spin_unlock_irqrestore(&reset->lock, flags); + } + + return 0; +} + +static int sprd_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + sprd_reset_assert(rcdev, id); + udelay(1); + sprd_reset_deassert(rcdev, id); + + return 0; +} + +const struct reset_control_ops sprd_reset_ops = { + .assert = sprd_reset_assert, + .deassert = sprd_reset_deassert, + .reset = sprd_reset_reset, +}; +EXPORT_SYMBOL_GPL(sprd_reset_ops); diff --git a/drivers/clk/sprd/reset.h b/drivers/clk/sprd/reset.h new file mode 100644 index 000000000000..155330b42775 --- /dev/null +++ b/drivers/clk/sprd/reset.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +// +// Spreadtrum reset clock driver +// +// Copyright (C) 2022 Spreadtrum, Inc. +// Author: Zhifeng Tang <zhifeng.tang@unisoc.com> + +#ifndef _SPRD_RESET_H_ +#define _SPRD_RESET_H_ + +#include <linux/reset-controller.h> +#include <linux/spinlock.h> + +struct sprd_reset_map { + u32 reg; + u32 mask; + bool sc; + u32 sc_offset; +}; + +struct sprd_reset { + struct reset_controller_dev rcdev; + const struct sprd_reset_map *reset_map; + struct regmap *regmap; + spinlock_t lock; +}; + +extern const struct reset_control_ops sprd_reset_ops; + +#endif /* _SPRD_RESET_H_ */ diff --git a/drivers/clk/sprd/ums512-clk.c b/drivers/clk/sprd/ums512-clk.c index 9384ecc6c741..cebc83608f0a 100644 --- a/drivers/clk/sprd/ums512-clk.c +++ b/drivers/clk/sprd/ums512-clk.c @@ -15,6 +15,7 @@ #include <linux/slab.h> #include <dt-bindings/clock/sprd,ums512-clk.h> +#include <dt-bindings/reset/sprd,ums512-reset.h> #include "common.h" #include "composite.h" @@ -22,6 +23,7 @@ #include "gate.h" #include "mux.h" #include "pll.h" +#include "reset.h" #define UMS512_MUX_FLAG \ (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT) @@ -105,10 +107,42 @@ static struct clk_hw_onecell_data ums512_pmu_gate_hws = { .num = CLK_PMU_GATE_NUM, }; +static struct sprd_reset_map ums512_pmu_apb_resets[] = { + [RESET_PMU_APB_WTLCP_SOFT_RST] = { 0x00b0, BIT(0), true, 0x1000 }, + [RESET_PMU_APB_PUBCP_SOFT_RST] = { 0x00b0, BIT(1), true, 0x1000 }, + [RESET_PMU_APB_WTLCP_DSP_SOFT_RST] = { 0x00b0, BIT(2), true, 0x1000 }, + [RESET_PMU_APB_MM_SOFT_RST] = { 0x00b0, BIT(3), true, 0x1000 }, + [RESET_PMU_APB_GPU_SOFT_RST] = { 0x00b0, BIT(4), true, 0x1000 }, + [RESET_PMU_APB_AP_SOFT_RST] = { 0x00b0, BIT(5), true, 0x1000 }, + [RESET_PMU_APB_PUB_SOFT_RST] = { 0x00b0, BIT(6), true, 0x1000 }, + [RESET_PMU_APB_APCPU_SOFT_RST] = { 0x00b0, BIT(7), true, 0x1000 }, + [RESET_PMU_APB_SP_SYS_SOFT_RST] = { 0x00b0, BIT(8), true, 0x1000 }, + [RESET_PMU_APB_AUDCP_SYS_SOFT_RST] = { 0x00b0, BIT(9), true, 0x1000 }, + [RESET_PMU_APB_AUDCP_AUDDSP_SOFT_RST] = { 0x00b0, BIT(10), true, 0x1000 }, + [RESET_PMU_APB_CDMA_SOFT_RST] = { 0x00b0, BIT(11), true, 0x1000 }, + [RESET_PMU_APB_WTLCP_AON_SOFT_RST] = { 0x00b0, BIT(12), true, 0x1000 }, + [RESET_PMU_APB_WCDMA_AON_SOFT_RST] = { 0x00b0, BIT(13), true, 0x1000 }, + [RESET_PMU_APB_WTLCP_LDSP_SOFT_RST] = { 0x00b0, BIT(14), true, 0x1000 }, + [RESET_PMU_APB_WTLCP_TGDSP_SOFT_RST] = { 0x00b0, BIT(15), true, 0x1000 }, + [RESET_PMU_APB_AP_VSP_SOFT_RST] = { 0x00b0, BIT(16), true, 0x1000 }, + [RESET_PMU_APB_AP_VDSP_SOFT_RST] = { 0x00b0, BIT(17), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CORE0_MODE_ST_SOFT_RST] = { 0x00b0, BIT(18), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CORE1_MODE_ST_SOFT_RST] = { 0x00b0, BIT(19), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CORE2_MODE_ST_SOFT_RST] = { 0x00b0, BIT(20), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CORE3_MODE_ST_SOFT_RST] = { 0x00b0, BIT(21), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CORE4_MODE_ST_SOFT_RST] = { 0x00b0, BIT(22), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CORE5_MODE_ST_SOFT_RST] = { 0x00b0, BIT(23), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CORE6_MODE_ST_SOFT_RST] = { 0x00b0, BIT(24), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CORE7_MODE_ST_SOFT_RST] = { 0x00b0, BIT(25), true, 0x1000 }, + [RESET_PMU_APB_APCPU_CLUSTER_MODE_ST_SOFT_RST] = { 0x00b0, BIT(26), true, 0x1000 }, +}; + static struct sprd_clk_desc ums512_pmu_gate_desc = { .clk_clks = ums512_pmu_gate_clks, .num_clk_clks = ARRAY_SIZE(ums512_pmu_gate_clks), .hw_clks = &ums512_pmu_gate_hws, + .resets = ums512_pmu_apb_resets, + .num_resets = ARRAY_SIZE(ums512_pmu_apb_resets), }; /* pll clock at g0 */ @@ -450,10 +484,30 @@ static struct clk_hw_onecell_data ums512_apahb_gate_hws = { .num = CLK_AP_AHB_GATE_NUM, }; +static struct sprd_reset_map ums512_ap_ahb_resets[] = { + [RESET_AP_AHB_DSI_SOFT_RST] = { 0x0004, BIT(0), true, 0x1000 }, + [RESET_AP_AHB_DISPC_SOFT_RST] = { 0x0004, BIT(1), true, 0x1000 }, + [RESET_AP_AHB_VDSP_IDMA_VAU_SOFT_RST] = { 0x0004, BIT(2), true, 0x1000 }, + [RESET_AP_AHB_VDSP_MSTD_VAU_SOFT_RST] = { 0x0004, BIT(3), true, 0x1000 }, + [RESET_AP_AHB_VDSP_MSTI_VAU_SOFT_RST] = { 0x0004, BIT(4), true, 0x1000 }, + [RESET_AP_AHB_VDMA_VAU_SOFT_RST] = { 0x0004, BIT(5), true, 0x1000 }, + [RESET_AP_AHB_IPI_SOFT_RST] = { 0x0004, BIT(6), true, 0x1000 }, + [RESET_AP_AHB_VDMA_SOFT_RST] = { 0x0004, BIT(7), true, 0x1000 }, + [RESET_AP_AHB_DMA_SOFT_RST] = { 0x0004, BIT(8), true, 0x1000 }, + [RESET_AP_AHB_VDSP_SOFT_RST] = { 0x0004, BIT(9), true, 0x1000 }, + [RESET_AP_AHB_VDSP_DEBUG_SOFT_RST] = { 0x0004, BIT(10), true, 0x1000 }, + [RESET_AP_AHB_VSP_GLOBAL_SOFT_RST] = { 0x0004, BIT(11), true, 0x1000 }, + [RESET_AP_AHB_VPP_SOFT_RST] = { 0x0004, BIT(12), true, 0x1000 }, + [RESET_AP_AHB_VSP_SOFT_RST] = { 0x0004, BIT(13), true, 0x1000 }, + [RESET_AP_AHB_DISPC_VAU_SOFT_RST] = { 0x0004, BIT(14), true, 0x1000 }, +}; + static struct sprd_clk_desc ums512_apahb_gate_desc = { .clk_clks = ums512_apahb_gate, .num_clk_clks = ARRAY_SIZE(ums512_apahb_gate), .hw_clks = &ums512_apahb_gate_hws, + .resets = ums512_ap_ahb_resets, + .num_resets = ARRAY_SIZE(ums512_ap_ahb_resets), }; /* ap clks */ @@ -1542,10 +1596,82 @@ static struct clk_hw_onecell_data ums512_aon_gate_hws = { .num = CLK_AON_APB_GATE_NUM, }; +static struct sprd_reset_map ums512_aon_ahb_resets[] = { + [RESET_AON_APB_RC100M_CAL_SOFT_RST] = { 0x000c, BIT(0), true, 0x1000 }, + [RESET_AON_APB_RFTI_SOFT_RST] = { 0x000c, BIT(1), true, 0x1000 }, + [RESET_AON_APB_DCXO_LC_SOFT_RST] = { 0x000c, BIT(2), true, 0x1000 }, + [RESET_AON_APB_BB_CAL_SOFT_RST] = { 0x000c, BIT(3), true, 0x1000 }, + [RESET_AON_APB_MSPI0_SOFT_RST] = { 0x000c, BIT(4), true, 0x1000 }, + [RESET_AON_APB_MSPI1_SOFT_RST] = { 0x000c, BIT(5), true, 0x1000 }, + [RESET_AON_APB_DAP_MTX_SOFT_RST] = { 0x000c, BIT(6), true, 0x1000 }, + [RESET_AON_APB_LVDSDIS_SOFT_RST] = { 0x000c, BIT(7), true, 0x1000 }, + [RESET_AON_APB_SERDES_DPHY_SOFT_RST] = { 0x000c, BIT(8), true, 0x1000 }, + [RESET_AON_APB_SERDES_DPHY_APB_SOFT_RST] = { 0x000c, BIT(9), true, 0x1000 }, + [RESET_AON_APB_AP_EMMC_SOFT_RST] = { 0x000c, BIT(10), true, 0x1000 }, + [RESET_AON_APB_AP_SDIO0_SOFT_RST] = { 0x000c, BIT(11), true, 0x1000 }, + [RESET_AON_APB_AP_SDIO1_SOFT_RST] = { 0x000c, BIT(12), true, 0x1000 }, + [RESET_AON_APB_AP_SDIO2_SOFT_RST] = { 0x000c, BIT(13), true, 0x1000 }, + [RESET_AON_APB_PUBCP_SDIO0_SOFT_RST] = { 0x000c, BIT(14), true, 0x1000 }, + [RESET_AON_APB_EFUSE_SOFT_RST] = { 0x0010, BIT(0), true, 0x1000 }, + [RESET_AON_APB_GPIO_SOFT_RST] = { 0x0010, BIT(1), true, 0x1000 }, + [RESET_AON_APB_MBOX_SOFT_RST] = { 0x0010, BIT(2), true, 0x1000 }, + [RESET_AON_APB_KPD_SOFT_RST] = { 0x0010, BIT(3), true, 0x1000 }, + [RESET_AON_APB_AON_SYST_SOFT_RST] = { 0x0010, BIT(4), true, 0x1000 }, + [RESET_AON_APB_AP_SYST_SOFT_RST] = { 0x0010, BIT(5), true, 0x1000 }, + [RESET_AON_APB_AON_TMR_SOFT_RST] = { 0x0010, BIT(6), true, 0x1000 }, + [RESET_AON_APB_DVFS_TOP_SOFT_RST] = { 0x0010, BIT(7), true, 0x1000 }, + [RESET_AON_APB_OTG_UTMI_SOFT_RST] = { 0x0010, BIT(8), true, 0x1000 }, + [RESET_AON_APB_OTG_PHY_SOFT_RST] = { 0x0010, BIT(9), true, 0x1000 }, + [RESET_AON_APB_SPLK_SOFT_RST] = { 0x0010, BIT(10), true, 0x1000 }, + [RESET_AON_APB_PIN_SOFT_RST] = { 0x0010, BIT(11), true, 0x1000 }, + [RESET_AON_APB_ANA_SOFT_RST] = { 0x0010, BIT(12), true, 0x1000 }, + [RESET_AON_APB_CKG_SOFT_RST] = { 0x0010, BIT(13), true, 0x1000 }, + [RESET_AON_APB_ETC_SOFT_RST] = { 0x0010, BIT(14), true, 0x1000 }, + [RESET_AON_APB_APCPU_TS0_SOFT_RST] = { 0x0010, BIT(17), true, 0x1000 }, + [RESET_AON_APB_APB_BUSMON_SOFT_RST] = { 0x0010, BIT(18), true, 0x1000 }, + [RESET_AON_APB_AON_IIS_SOFT_RST] = { 0x0010, BIT(19), true, 0x1000 }, + [RESET_AON_APB_SCC_SOFT_RST] = { 0x0010, BIT(20), true, 0x1000 }, + [RESET_AON_APB_THM0_SOFT_RST] = { 0x0014, BIT(0), true, 0x1000 }, + [RESET_AON_APB_THM1_SOFT_RST] = { 0x0014, BIT(1), true, 0x1000 }, + [RESET_AON_APB_THM2_SOFT_RST] = { 0x0014, BIT(2), true, 0x1000 }, + [RESET_AON_APB_AP_SIM_AON_TOP_SOFT_RST] = { 0x0014, BIT(3), true, 0x1000 }, + [RESET_AON_APB_PUBCP_SIM0_AON_TOP_SOFT_RST] = { 0x0014, BIT(4), true, 0x1000 }, + [RESET_AON_APB_PUBCP_SIM1_AON_TOP_SOFT_RST] = { 0x0014, BIT(5), true, 0x1000 }, + [RESET_AON_APB_PUBCP_SIM2_AON_TOP_SOFT_RST] = { 0x0014, BIT(6), true, 0x1000 }, + [RESET_AON_APB_I2C_SOFT_RST] = { 0x0014, BIT(7), true, 0x1000 }, + [RESET_AON_APB_PMU_SOFT_RST] = { 0x0014, BIT(8), true, 0x1000 }, + [RESET_AON_APB_ADI_SOFT_RST] = { 0x0014, BIT(9), true, 0x1000 }, + [RESET_AON_APB_EIC_SOFT_RST] = { 0x0014, BIT(10), true, 0x1000 }, + [RESET_AON_APB_AP_INTC0_SOFT_RST] = { 0x0014, BIT(11), true, 0x1000 }, + [RESET_AON_APB_AP_INTC1_SOFT_RST] = { 0x0014, BIT(12), true, 0x1000 }, + [RESET_AON_APB_AP_INTC2_SOFT_RST] = { 0x0014, BIT(13), true, 0x1000 }, + [RESET_AON_APB_AP_INTC3_SOFT_RST] = { 0x0014, BIT(14), true, 0x1000 }, + [RESET_AON_APB_AP_INTC4_SOFT_RST] = { 0x0014, BIT(15), true, 0x1000 }, + [RESET_AON_APB_AP_INTC5_SOFT_RST] = { 0x0014, BIT(16), true, 0x1000 }, + [RESET_AON_APB_AUDCP_INTC_SOFT_RST] = { 0x0014, BIT(17), true, 0x1000 }, + [RESET_AON_APB_PUBCP_INTC_SOFT_RST] = { 0x0014, BIT(18), true, 0x1000 }, + [RESET_AON_APB_WTLCP_TGDSP_INTC_SOFT_RST] = { 0x0014, BIT(19), true, 0x1000 }, + [RESET_AON_APB_WTLCP_LDSP_INTC_SOFT_RST] = { 0x0014, BIT(20), true, 0x1000 }, + [RESET_AON_APB_WTLCP_INTC_SOFT_RST] = { 0x0014, BIT(21), true, 0x1000 }, + [RESET_AON_APB_AP_TMR0_SOFT_RST] = { 0x0014, BIT(22), true, 0x1000 }, + [RESET_AON_APB_AP_TMR1_SOFT_RST] = { 0x0014, BIT(23), true, 0x1000 }, + [RESET_AON_APB_AP_TMR2_SOFT_RST] = { 0x0014, BIT(24), true, 0x1000 }, + [RESET_AON_APB_PWM0_SOFT_RST] = { 0x0014, BIT(25), true, 0x1000 }, + [RESET_AON_APB_PWM1_SOFT_RST] = { 0x0014, BIT(26), true, 0x1000 }, + [RESET_AON_APB_PWM2_SOFT_RST] = { 0x0014, BIT(27), true, 0x1000 }, + [RESET_AON_APB_PWM3_SOFT_RST] = { 0x0014, BIT(28), true, 0x1000 }, + [RESET_AON_APB_AP_WDG_SOFT_RST] = { 0x0014, BIT(29), true, 0x1000 }, + [RESET_AON_APB_APCPU_WDG_SOFT_RST] = { 0x0014, BIT(30), true, 0x1000 }, + [RESET_AON_APB_SERDES_SOFT_RST] = { 0x0014, BIT(31), true, 0x1000 }, + [RESET_AON_APB_DJTAG_SOFT_RST] = { 0x0130, BIT(10), true, 0x1000 }, +}; + static struct sprd_clk_desc ums512_aon_gate_desc = { .clk_clks = ums512_aon_gate, .num_clk_clks = ARRAY_SIZE(ums512_aon_gate), .hw_clks = &ums512_aon_gate_hws, + .resets = ums512_aon_ahb_resets, + .num_resets = ARRAY_SIZE(ums512_aon_ahb_resets), }; /* audcp apb gates */ @@ -1584,10 +1710,18 @@ static struct clk_hw_onecell_data ums512_audcpapb_gate_hws = { .num = CLK_AUDCP_APB_GATE_NUM, }; +static struct sprd_reset_map ums512_audcp_apb_resets[] = { + [RESET_AUDCP_APB_WDG_SOFT_RST] = { 0x0004, BIT(1), true, 0x100 }, + [RESET_AUDCP_APB_TMR0_SOFT_RST] = { 0x0004, BIT(2), true, 0x100 }, + [RESET_AUDCP_APB_TMR1_SOFT_RST] = { 0x0004, BIT(3), true, 0x100 }, +}; + static const struct sprd_clk_desc ums512_audcpapb_gate_desc = { .clk_clks = ums512_audcpapb_gate, .num_clk_clks = ARRAY_SIZE(ums512_audcpapb_gate), .hw_clks = &ums512_audcpapb_gate_hws, + .resets = ums512_audcp_apb_resets, + .num_resets = ARRAY_SIZE(ums512_audcp_apb_resets), }; /* audcp ahb gates */ @@ -1696,10 +1830,29 @@ static struct clk_hw_onecell_data ums512_audcpahb_gate_hws = { .num = CLK_AUDCP_AHB_GATE_NUM, }; +static struct sprd_reset_map ums512_audcp_ahb_resets[] = { + [RESET_AUDCP_AHB_VBC_24M_SOFT_RST] = { 0x0008, BIT(0), true, 0x100 }, + [RESET_AUDCP_AHB_DMA_AP_SOFT_RST] = { 0x0008, BIT(1), true, 0x100 }, + [RESET_AUDCP_AHB_SRC48K_SOFT_RST] = { 0x0008, BIT(5), true, 0x100 }, + [RESET_AUDCP_AHB_MCDT_SOFT_RST] = { 0x0008, BIT(7), true, 0x100 }, + [RESET_AUDCP_AHB_VBCIFD_SOFT_RST] = { 0x0008, BIT(8), true, 0x100 }, + [RESET_AUDCP_AHB_VBC_SOFT_RST] = { 0x0008, BIT(9), true, 0x100 }, + [RESET_AUDCP_AHB_SPINLOCK_SOFT_RST] = { 0x0008, BIT(10), true, 0x100 }, + [RESET_AUDCP_AHB_DMA_CP_SOFT_RST] = { 0x0008, BIT(11), true, 0x100 }, + [RESET_AUDCP_AHB_IIS0_SOFT_RST] = { 0x0008, BIT(12), true, 0x100 }, + [RESET_AUDCP_AHB_IIS1_SOFT_RST] = { 0x0008, BIT(13), true, 0x100 }, + [RESET_AUDCP_AHB_IIS2_SOFT_RST] = { 0x0008, BIT(14), true, 0x100 }, + [RESET_AUDCP_AHB_UART_SOFT_RST] = { 0x0008, BIT(16), true, 0x100 }, + [RESET_AUDCP_AHB_AUD_SOFT_RST] = { 0x0008, BIT(25), true, 0x100 }, + [RESET_AUDCP_AHB_DVFS_SOFT_RST] = { 0x0008, BIT(26), true, 0x100 }, +}; + static const struct sprd_clk_desc ums512_audcpahb_gate_desc = { .clk_clks = ums512_audcpahb_gate, .num_clk_clks = ARRAY_SIZE(ums512_audcpahb_gate), .hw_clks = &ums512_audcpahb_gate_hws, + .resets = ums512_audcp_ahb_resets, + .num_resets = ARRAY_SIZE(ums512_audcp_ahb_resets), }; /* gpu clocks */ @@ -1752,10 +1905,17 @@ static struct clk_hw_onecell_data ums512_gpu_clk_hws = { .num = CLK_GPU_CLK_NUM, }; +static struct sprd_reset_map ums512_gpu_apb_resets[] = { + [RESET_GPU_APB_GPU_CORE_SOFT_RST] = { 0x0000, BIT(0), true, 0x1000 }, + [RESET_GPU_APB_SYS_SOFT_RST_REQ_CORE] = { 0x0000, BIT(1), true, 0x1000 }, +}; + static struct sprd_clk_desc ums512_gpu_clk_desc = { .clk_clks = ums512_gpu_clk, .num_clk_clks = ARRAY_SIZE(ums512_gpu_clk), .hw_clks = &ums512_gpu_clk_hws, + .resets = ums512_gpu_apb_resets, + .num_resets = ARRAY_SIZE(ums512_gpu_apb_resets), }; /* mm clocks */ @@ -1994,10 +2154,42 @@ static struct clk_hw_onecell_data ums512_mm_gate_clk_hws = { .num = CLK_MM_GATE_CLK_NUM, }; +static struct sprd_reset_map ums512_mm_ahb_resets[] = { + [RESET_MM_AHB_CKG_SOFT_RST] = { 0x0004, BIT(0), true, 0x1000 }, + [RESET_MM_AHB_JPG_SOFT_RST] = { 0x0004, BIT(1), true, 0x1000 }, + [RESET_MM_AHB_DCAM_AXI_SOFT_RST] = { 0x0004, BIT(2), true, 0x1000 }, + [RESET_MM_AHB_DCAM2_SOFT_RST] = { 0x0004, BIT(3), true, 0x1000 }, + [RESET_MM_AHB_DCAM1_SOFT_RST] = { 0x0004, BIT(4), true, 0x1000 }, + [RESET_MM_AHB_DCAM0_SOFT_RST] = { 0x0004, BIT(5), true, 0x1000 }, + [RESET_MM_AHB_DCAM_VAU_SOFT_RST] = { 0x0004, BIT(6), true, 0x1000 }, + [RESET_MM_AHB_MIPI_CSI2_SOFT_RST] = { 0x0004, BIT(7), true, 0x1000 }, + [RESET_MM_AHB_MIPI_CSI1_SOFT_RST] = { 0x0004, BIT(8), true, 0x1000 }, + [RESET_MM_AHB_MIPI_CSI0_SOFT_RST] = { 0x0004, BIT(9), true, 0x1000 }, + [RESET_MM_AHB_ISP_SOFT_RST] = { 0x0004, BIT(10), true, 0x1000 }, + [RESET_MM_AHB_ISP_VAU_SOFT_RST] = { 0x0004, BIT(11), true, 0x1000 }, + [RESET_MM_AHB_ISP_AHB_SOFT_RST] = { 0x0004, BIT(12), true, 0x1000 }, + [RESET_MM_AHB_CPP_DMA_SOFT_RST] = { 0x0004, BIT(13), true, 0x1000 }, + [RESET_MM_AHB_CPP_PATH1_SOFT_RST] = { 0x0004, BIT(14), true, 0x1000 }, + [RESET_MM_AHB_CPP_PATH0_SOFT_RST] = { 0x0004, BIT(15), true, 0x1000 }, + [RESET_MM_AHB_CPP_SOFT_RST] = { 0x0004, BIT(16), true, 0x1000 }, + [RESET_MM_AHB_MM_MAIN_SOFT_RST] = { 0x0004, BIT(17), true, 0x1000 }, + [RESET_MM_AHB_CPP_SOFT_RST_MASK] = { 0x0004, BIT(18), true, 0x1000 }, + [RESET_MM_AHB_JPG_SOFT_RST_MASK] = { 0x0004, BIT(19), true, 0x1000 }, + [RESET_MM_AHB_JPG_VAU_SOFT_RST] = { 0x0004, BIT(20), true, 0x1000 }, + [RESET_MM_AHB_CPP_VAU_SOFT_RST] = { 0x0004, BIT(21), true, 0x1000 }, + [RESET_MM_AHB_FD_VAU_SOFT_RST] = { 0x0004, BIT(22), true, 0x1000 }, + [RESET_MM_AHB_DCAM_ALL_SOFT_RST] = { 0x0004, BIT(23), true, 0x1000 }, + [RESET_MM_AHB_DVFS_SOFT_RST] = { 0x0004, BIT(24), true, 0x1000 }, + [RESET_MM_AHB_FD_SOFT_RST] = { 0x0004, BIT(26), true, 0x1000 }, + [RESET_MM_AHB_FD_SOFT_RST_MASK] = { 0x0004, BIT(27), true, 0x1000 }, +}; + static struct sprd_clk_desc ums512_mm_gate_clk_desc = { .clk_clks = ums512_mm_gate_clk, .num_clk_clks = ARRAY_SIZE(ums512_mm_gate_clk), .hw_clks = &ums512_mm_gate_clk_hws, + .resets = ums512_mm_ahb_resets, + .num_resets = ARRAY_SIZE(ums512_mm_ahb_resets), }; /* ap apb gates */ @@ -2132,10 +2324,38 @@ static struct clk_hw_onecell_data ums512_apapb_gate_hws = { .num = CLK_AP_APB_GATE_NUM, }; +static struct sprd_reset_map ums512_ap_apb_resets[] = { + [RESET_AP_APB_SIM0_SOFT_RST] = { 0x0004, BIT(0), true, 0x1000 }, + [RESET_AP_APB_IIS0_SOFT_RST] = { 0x0004, BIT(1), true, 0x1000 }, + [RESET_AP_APB_IIS1_SOFT_RST] = { 0x0004, BIT(2), true, 0x1000 }, + [RESET_AP_APB_IIS2_SOFT_RST] = { 0x0004, BIT(3), true, 0x1000 }, + [RESET_AP_APB_SPI0_SOFT_RST] = { 0x0004, BIT(4), true, 0x1000 }, + [RESET_AP_APB_SPI1_SOFT_RST] = { 0x0004, BIT(5), true, 0x1000 }, + [RESET_AP_APB_SPI2_SOFT_RST] = { 0x0004, BIT(6), true, 0x1000 }, + [RESET_AP_APB_SPI3_SOFT_RST] = { 0x0004, BIT(7), true, 0x1000 }, + [RESET_AP_APB_I2C0_SOFT_RST] = { 0x0004, BIT(8), true, 0x1000 }, + [RESET_AP_APB_I2C1_SOFT_RST] = { 0x0004, BIT(9), true, 0x1000 }, + [RESET_AP_APB_I2C2_SOFT_RST] = { 0x0004, BIT(10), true, 0x1000 }, + [RESET_AP_APB_I2C3_SOFT_RST] = { 0x0004, BIT(11), true, 0x1000 }, + [RESET_AP_APB_I2C4_SOFT_RST] = { 0x0004, BIT(12), true, 0x1000 }, + [RESET_AP_APB_UART0_SOFT_RST] = { 0x0004, BIT(13), true, 0x1000 }, + [RESET_AP_APB_UART1_SOFT_RST] = { 0x0004, BIT(14), true, 0x1000 }, + [RESET_AP_APB_UART2_SOFT_RST] = { 0x0004, BIT(15), true, 0x1000 }, + [RESET_AP_APB_SDIO0_SOFT_RST] = { 0x0004, BIT(16), true, 0x1000 }, + [RESET_AP_APB_SDIO1_SOFT_RST] = { 0x0004, BIT(17), true, 0x1000 }, + [RESET_AP_APB_SDIO2_SOFT_RST] = { 0x0004, BIT(18), true, 0x1000 }, + [RESET_AP_APB_EMMC_SOFT_RST] = { 0x0004, BIT(19), true, 0x1000 }, + [RESET_AP_APB_CE_SEC_SOFT_RST] = { 0x0004, BIT(20), true, 0x1000 }, + [RESET_AP_APB_CE_PUB_SOFT_RST] = { 0x0004, BIT(21), true, 0x1000 }, + [RESET_AP_APB_AP_DVFS_SOFT_RST] = { 0x0004, BIT(22), true, 0x1000 }, +}; + static struct sprd_clk_desc ums512_apapb_gate_desc = { .clk_clks = ums512_apapb_gate, .num_clk_clks = ARRAY_SIZE(ums512_apapb_gate), .hw_clks = &ums512_apapb_gate_hws, + .resets = ums512_ap_apb_resets, + .num_resets = ARRAY_SIZE(ums512_ap_apb_resets), }; static const struct of_device_id sprd_ums512_clk_ids[] = { @@ -2176,6 +2396,7 @@ MODULE_DEVICE_TABLE(of, sprd_ums512_clk_ids); static int ums512_clk_probe(struct platform_device *pdev) { const struct sprd_clk_desc *desc; + struct sprd_reset *reset; int ret; desc = device_get_match_data(&pdev->dev); @@ -2186,6 +2407,25 @@ static int ums512_clk_probe(struct platform_device *pdev) if (ret) return ret; + if (desc->num_resets > 0) { + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + spin_lock_init(&reset->lock); + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.ops = &sprd_reset_ops; + reset->rcdev.nr_resets = desc->num_resets; + reset->reset_map = desc->resets; + reset->regmap = platform_get_drvdata(pdev); + + ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev); + if (ret) { + dev_err(&pdev->dev, "Failed to register reset controller\n"); + return ret; + } + } + return sprd_clk_probe(&pdev->dev, desc->hw_clks); } -- 2.17.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH V2 3/3] arm64: dts: sprd: Add reset controller driver for UMS512 2023-12-15 11:41 [PATCH V2 0/3] clk: sprd: Add reset controller driver for ums512 Zhifeng Tang 2023-12-15 11:41 ` [PATCH V2 1/3] dt-bindings: reset: Add reset controller bindings for Unisoc's ums512 Zhifeng Tang 2023-12-15 11:41 ` [PATCH V2 2/3] clk: sprd: Add reset controller driver for ums512 Zhifeng Tang @ 2023-12-15 11:41 ` Zhifeng Tang 2 siblings, 0 replies; 5+ messages in thread From: Zhifeng Tang @ 2023-12-15 11:41 UTC (permalink / raw) To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Orson Zhai, Baolin Wang, Chunyan Zhang, Philipp Zabel Cc: linux-clk, devicetree, linux-kernel, Zhifeng Tang, Wenming Wu From: "zhifeng.tang" <zhifeng.tang@unisoc.com> The reset register has the same base address as the gate register. Signed-off-by: zhifeng.tang <zhifeng.tang@unisoc.com> --- arch/arm64/boot/dts/sprd/ums512.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/sprd/ums512.dtsi b/arch/arm64/boot/dts/sprd/ums512.dtsi index 024be594c47d..08d0adf6624c 100644 --- a/arch/arm64/boot/dts/sprd/ums512.dtsi +++ b/arch/arm64/boot/dts/sprd/ums512.dtsi @@ -7,6 +7,7 @@ #include <dt-bindings/clock/sprd,ums512-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/sprd,ums512-reset.h> / { interrupt-parent = <&gic>; @@ -182,6 +183,7 @@ clocks = <&ext_26m>; clock-names = "ext-26m"; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -316,6 +318,7 @@ clocks = <&ext_26m>; clock-names = "ext-26m"; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -333,6 +336,7 @@ clocks = <&ext_26m>; clock-names = "ext-26m"; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -348,6 +352,7 @@ compatible = "sprd,ums512-audcpapb-gate"; reg = <0x0 0x300>; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -363,6 +368,7 @@ compatible = "sprd,ums512-audcpahb-gate"; reg = <0x0 0x300>; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -380,6 +386,7 @@ clock-names = "ext-26m"; reg = <0x0 0x100>; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -401,6 +408,7 @@ compatible = "sprd,ums512-mm-gate-clk"; reg = <0x0 0x3000>; #clock-cells = <1>; + #reset-cells = <1>; }; }; @@ -416,6 +424,7 @@ compatible = "sprd,ums512-apapb-gate"; reg = <0x0 0x3000>; #clock-cells = <1>; + #reset-cells = <1>; }; }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-12-16 12:40 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-12-15 11:41 [PATCH V2 0/3] clk: sprd: Add reset controller driver for ums512 Zhifeng Tang 2023-12-15 11:41 ` [PATCH V2 1/3] dt-bindings: reset: Add reset controller bindings for Unisoc's ums512 Zhifeng Tang 2023-12-16 12:40 ` Conor Dooley 2023-12-15 11:41 ` [PATCH V2 2/3] clk: sprd: Add reset controller driver for ums512 Zhifeng Tang 2023-12-15 11:41 ` [PATCH V2 3/3] arm64: dts: sprd: Add reset controller driver for UMS512 Zhifeng Tang
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