[PATCH 0/3] Renesas RZ/G2L family and RZ/G3S add missing IRQC interrupts

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* [PATCH 0/3] Renesas RZ/G2L family and RZ/G3S add missing IRQC interrupts
@ 2024-02-02  9:39 Prabhakar
  2024-02-02  9:39 ` [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts Prabhakar
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Prabhakar @ 2024-02-02  9:39 UTC (permalink / raw)
  To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Geert Uytterhoeven, Magnus Damm
  Cc: devicetree, linux-renesas-soc, linux-kernel, Prabhakar, Biju Das,
	Claudiu Beznea, Lad Prabhakar

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series aims to add the missing bus-error and eccram error
interrupts for RZ/G2L family and RZ/G3S SoC.

Cheers,
Prabhakar

Lad Prabhakar (3):
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update
    interrupts
  arm64: dts: renesas: rz-g2l-family: Add missing interrupts from IRQC
    IP block
  arm64: dts: renesas: r9a08g045: Add missing interrupts of IRQC node

 .../renesas,rzg2l-irqc.yaml                   | 44 +++++++++++++++----
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi   | 12 ++++-
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi    | 22 +++++++++-
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi    | 22 +++++++++-
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi    |  8 +++-
 5 files changed, 93 insertions(+), 15 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
  2024-02-02  9:39 [PATCH 0/3] Renesas RZ/G2L family and RZ/G3S add missing IRQC interrupts Prabhakar
@ 2024-02-02  9:39 ` Prabhakar
  2024-02-02 17:07   ` Conor Dooley
  2024-02-02  9:39 ` [PATCH 2/3] arm64: dts: renesas: rz-g2l-family: Add missing interrupts from IRQC IP block Prabhakar
  2024-02-02  9:39 ` [PATCH 3/3] arm64: dts: renesas: r9a08g045: Add missing interrupts of IRQC node Prabhakar
  2 siblings, 1 reply; 6+ messages in thread
From: Prabhakar @ 2024-02-02  9:39 UTC (permalink / raw)
  To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Geert Uytterhoeven, Magnus Damm
  Cc: devicetree, linux-renesas-soc, linux-kernel, Prabhakar, Biju Das,
	Claudiu Beznea, Lad Prabhakar

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

RZ/{G2L, G2LC}, RZ/G2UL, RZ/V2L and RZ/G3S SoCs have ECCRAM0/1 interrupts,
reflect the same in the DT binding doc.

RZ/G3S SoC has ECCRAM0/1 interrupts combined into single interrupts so
we just use the below to represent them:
- ec7tie1-0
- ec7tie2-0
- ec7tiovf-0

Additionally mark 'interrupt-names' property as required for all the SoCs
and update the example node in the binding doc.

Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../renesas,rzg2l-irqc.yaml                   | 44 +++++++++++++++----
 1 file changed, 35 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index d3b5aec0a3f7..0bc9c604a2d7 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -44,7 +44,7 @@ properties:
     maxItems: 1
 
   interrupts:
-    minItems: 41
+    minItems: 45
     items:
       - description: NMI interrupt
       - description: IRQ0 interrupt
@@ -88,9 +88,15 @@ properties:
       - description: GPIO interrupt, TINT30
       - description: GPIO interrupt, TINT31
       - description: Bus error interrupt
+      - description: ECCRAM0 1bit error interrupt
+      - description: ECCRAM0 2bit error interrupt
+      - description: ECCRAM0 error overflow interrupt
+      - description: ECCRAM1 1bit error interrupt
+      - description: ECCRAM1 2bit error interrupt
+      - description: ECCRAM1 error overflow interrupt
 
   interrupt-names:
-    minItems: 41
+    minItems: 45
     items:
       - const: nmi
       - const: irq0
@@ -134,6 +140,12 @@ properties:
       - const: tint30
       - const: tint31
       - const: bus-err
+      - const: ec7tie1-0
+      - const: ec7tie2-0
+      - const: ec7tiovf-0
+      - const: ec7tie1-1
+      - const: ec7tie2-1
+      - const: ec7tiovf-1
 
   clocks:
     maxItems: 2
@@ -156,6 +168,7 @@ required:
   - interrupt-controller
   - reg
   - interrupts
+  - interrupt-names
   - clocks
   - clock-names
   - power-domains
@@ -169,16 +182,19 @@ allOf:
         compatible:
           contains:
             enum:
-              - renesas,r9a07g043u-irqc
               - renesas,r9a08g045-irqc
     then:
       properties:
         interrupts:
-          minItems: 42
+          maxItems: 45
         interrupt-names:
-          minItems: 42
-      required:
-        - interrupt-names
+          maxItems: 45
+    else:
+      properties:
+        interrupts:
+          minItems: 48
+        interrupt-names:
+          minItems: 48
 
 unevaluatedProperties: false
 
@@ -233,7 +249,14 @@ examples:
                      <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
                      <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
-                     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+                     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+                     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
         interrupt-names = "nmi",
                           "irq0", "irq1", "irq2", "irq3",
                           "irq4", "irq5", "irq6", "irq7",
@@ -244,7 +267,10 @@ examples:
                           "tint16", "tint17", "tint18", "tint19",
                           "tint20", "tint21", "tint22", "tint23",
                           "tint24", "tint25", "tint26", "tint27",
-                          "tint28", "tint29", "tint30", "tint31";
+                          "tint28", "tint29", "tint30", "tint31",
+                          "bus-err", "ec7tie1-0", "ec7tie2-0",
+                          "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+                          "ec7tiovf-1";
         clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
                  <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
         clock-names = "clk", "pclk";
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
  2024-02-02  9:39 ` [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts Prabhakar
@ 2024-02-02 17:07   ` Conor Dooley
  2024-02-03 15:27     ` Lad, Prabhakar
  0 siblings, 1 reply; 6+ messages in thread
From: Conor Dooley @ 2024-02-02 17:07 UTC (permalink / raw)
  To: Prabhakar
  Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Geert Uytterhoeven, Magnus Damm, devicetree, linux-renesas-soc,
	linux-kernel, Biju Das, Claudiu Beznea, Lad Prabhakar

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On Fri, Feb 02, 2024 at 09:39:05AM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> RZ/{G2L, G2LC}, RZ/G2UL, RZ/V2L and RZ/G3S SoCs have ECCRAM0/1 interrupts,
> reflect the same in the DT binding doc.

Renesas' naming scheme really does not help here, but using the
shorthands in the commit message when the diff uses the long form names
is not the easiest thing to follow. (:

> 
> RZ/G3S SoC has ECCRAM0/1 interrupts combined into single interrupts so
> we just use the below to represent them:
> - ec7tie1-0
> - ec7tie2-0
> - ec7tiovf-0

I think this information would be good in the itemised description,
since that claims these interrupt are only for ECCRAM0.


> Additionally mark 'interrupt-names' property as required for all the SoCs
> and update the example node in the binding doc.

Why? You've not given a reason for doing this, so it just seems
gratuitous.

Thanks,
Conor.

> 
> Fixes: 96fed779d3d4 ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
> Fixes: 1cf0697a24ef ("dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G3S")
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../renesas,rzg2l-irqc.yaml                   | 44 +++++++++++++++----
>  1 file changed, 35 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> index d3b5aec0a3f7..0bc9c604a2d7 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -44,7 +44,7 @@ properties:
>      maxItems: 1
>  
>    interrupts:
> -    minItems: 41
> +    minItems: 45
>      items:
>        - description: NMI interrupt
>        - description: IRQ0 interrupt
> @@ -88,9 +88,15 @@ properties:
>        - description: GPIO interrupt, TINT30
>        - description: GPIO interrupt, TINT31
>        - description: Bus error interrupt
> +      - description: ECCRAM0 1bit error interrupt
> +      - description: ECCRAM0 2bit error interrupt
> +      - description: ECCRAM0 error overflow interrupt
> +      - description: ECCRAM1 1bit error interrupt
> +      - description: ECCRAM1 2bit error interrupt
> +      - description: ECCRAM1 error overflow interrupt
>  
>    interrupt-names:
> -    minItems: 41
> +    minItems: 45
>      items:
>        - const: nmi
>        - const: irq0
> @@ -134,6 +140,12 @@ properties:
>        - const: tint30
>        - const: tint31
>        - const: bus-err
> +      - const: ec7tie1-0
> +      - const: ec7tie2-0
> +      - const: ec7tiovf-0
> +      - const: ec7tie1-1
> +      - const: ec7tie2-1
> +      - const: ec7tiovf-1
>  
>    clocks:
>      maxItems: 2
> @@ -156,6 +168,7 @@ required:
>    - interrupt-controller
>    - reg
>    - interrupts
> +  - interrupt-names
>    - clocks
>    - clock-names
>    - power-domains
> @@ -169,16 +182,19 @@ allOf:
>          compatible:
>            contains:
>              enum:
> -              - renesas,r9a07g043u-irqc
>                - renesas,r9a08g045-irqc
>      then:
>        properties:
>          interrupts:
> -          minItems: 42
> +          maxItems: 45
>          interrupt-names:
> -          minItems: 42
> -      required:
> -        - interrupt-names
> +          maxItems: 45
> +    else:
> +      properties:
> +        interrupts:
> +          minItems: 48
> +        interrupt-names:
> +          minItems: 48
>  
>  unevaluatedProperties: false
>  
> @@ -233,7 +249,14 @@ examples:
>                       <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
>                       <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
>                       <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
> -                     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
> +                     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
> +                     <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
>          interrupt-names = "nmi",
>                            "irq0", "irq1", "irq2", "irq3",
>                            "irq4", "irq5", "irq6", "irq7",
> @@ -244,7 +267,10 @@ examples:
>                            "tint16", "tint17", "tint18", "tint19",
>                            "tint20", "tint21", "tint22", "tint23",
>                            "tint24", "tint25", "tint26", "tint27",
> -                          "tint28", "tint29", "tint30", "tint31";
> +                          "tint28", "tint29", "tint30", "tint31",
> +                          "bus-err", "ec7tie1-0", "ec7tie2-0",
> +                          "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
> +                          "ec7tiovf-1";
>          clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
>                   <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
>          clock-names = "clk", "pclk";
> -- 
> 2.34.1
> 

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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts
  2024-02-02 17:07   ` Conor Dooley
@ 2024-02-03 15:27     ` Lad, Prabhakar
  0 siblings, 0 replies; 6+ messages in thread
From: Lad, Prabhakar @ 2024-02-03 15:27 UTC (permalink / raw)
  To: Conor Dooley
  Cc: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Geert Uytterhoeven, Magnus Damm, devicetree, linux-renesas-soc,
	linux-kernel, Biju Das, Claudiu Beznea, Lad Prabhakar

Hi Conor,

Thank you for the review.

On Fri, Feb 2, 2024 at 5:07 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Feb 02, 2024 at 09:39:05AM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > RZ/{G2L, G2LC}, RZ/G2UL, RZ/V2L and RZ/G3S SoCs have ECCRAM0/1 interrupts,
> > reflect the same in the DT binding doc.
>
> Renesas' naming scheme really does not help here, but using the
> shorthands in the commit message when the diff uses the long form names
> is not the easiest thing to follow. (:
>
Sure I'll elabore the SoCs according to the binding doc so that it's more clear.
> >
> > RZ/G3S SoC has ECCRAM0/1 interrupts combined into single interrupts so
> > we just use the below to represent them:
> > - ec7tie1-0
> > - ec7tie2-0
> > - ec7tiovf-0
>
> I think this information would be good in the itemised description,
> since that claims these interrupt are only for ECCRAM0.
>
Sure 'll update as below:

+      - const: ec7tie1-0   # For RZ/G3S SoC ECCRAM0/1 interrupts combined
+      - const: ec7tie2-0   # For RZ/G3S SoC ECCRAM0/1 interrupts combined
+      - const: ec7tiovf-0  # For RZ/G3S SoC ECCRAM0/1 interrupts combined

>
> > Additionally mark 'interrupt-names' property as required for all the SoCs
> > and update the example node in the binding doc.
>
> Why? You've not given a reason for doing this, so it just seems
> gratuitous.
>
Previous assumption was just the RZ/G2UL and RZ/G3S had the bus-err
and eccram error interrupts, but where as in actual all the above SoCs
have this interrupt so making interrupt-names as required so we can
parse them based on names.

Cheers,
Prabhakar

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/3] arm64: dts: renesas: rz-g2l-family: Add missing interrupts from IRQC IP block
  2024-02-02  9:39 [PATCH 0/3] Renesas RZ/G2L family and RZ/G3S add missing IRQC interrupts Prabhakar
  2024-02-02  9:39 ` [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts Prabhakar
@ 2024-02-02  9:39 ` Prabhakar
  2024-02-02  9:39 ` [PATCH 3/3] arm64: dts: renesas: r9a08g045: Add missing interrupts of IRQC node Prabhakar
  2 siblings, 0 replies; 6+ messages in thread
From: Prabhakar @ 2024-02-02  9:39 UTC (permalink / raw)
  To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Geert Uytterhoeven, Magnus Damm
  Cc: devicetree, linux-renesas-soc, linux-kernel, Prabhakar, Biju Das,
	Claudiu Beznea, Lad Prabhakar

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The IRQC IP block supports Bus error and ECCRAM interrupts. Update the
IRQC node with the missing interrupts, and additionally, include the
'interrupt-names' property in the IRQC node.

Fixes: 5edc51af5b30 ("arm64: dts: renesas: r9a07g044: Add IRQC node")
Fixes: 48ab6eddd8bb ("arm64: dts: renesas: r9a07g043u: Add IRQC node")
Fixes: 379478ab09e0 ("arm64: dts: renesas: r9a07g054: Add IRQC node")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 12 +++++++++--
 arch/arm64/boot/dts/renesas/r9a07g044.dtsi  | 22 ++++++++++++++++++++-
 arch/arm64/boot/dts/renesas/r9a07g054.dtsi  | 22 ++++++++++++++++++++-
 3 files changed, 52 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 01d08ebb4a78..964b0a475eee 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -178,7 +178,13 @@ irqc: interrupt-controller@110a0000 {
 			     <SOC_PERIPHERAL_IRQ(473) IRQ_TYPE_LEVEL_HIGH>,
 			     <SOC_PERIPHERAL_IRQ(474) IRQ_TYPE_LEVEL_HIGH>,
 			     <SOC_PERIPHERAL_IRQ(475) IRQ_TYPE_LEVEL_HIGH>,
-			     <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>;
+			     <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_EDGE_RISING>,
+			     <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_EDGE_RISING>,
+			     <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_EDGE_RISING>,
+			     <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_EDGE_RISING>,
+			     <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_EDGE_RISING>,
+			     <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_EDGE_RISING>,
+			     <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_EDGE_RISING>;
 		interrupt-names = "nmi",
 				  "irq0", "irq1", "irq2", "irq3",
 				  "irq4", "irq5", "irq6", "irq7",
@@ -190,7 +196,9 @@ irqc: interrupt-controller@110a0000 {
 				  "tint20", "tint21", "tint22", "tint23",
 				  "tint24", "tint25", "tint26", "tint27",
 				  "tint28", "tint29", "tint30", "tint31",
-				  "bus-err";
+				  "bus-err", "ec7tie1-0", "ec7tie2-0",
+				  "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+				  "ec7tiovf-1";
 		clocks = <&cpg CPG_MOD R9A07G043_IA55_CLK>,
 			<&cpg CPG_MOD R9A07G043_IA55_PCLK>;
 		clock-names = "clk", "pclk";
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 66f68fc2b241..081d8f49db87 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -905,7 +905,27 @@ irqc: interrupt-controller@110a0000 {
 				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
+					  "irq4", "irq5", "irq6", "irq7",
+					  "tint0", "tint1", "tint2", "tint3",
+					  "tint4", "tint5", "tint6", "tint7",
+					  "tint8", "tint9", "tint10", "tint11",
+					  "tint12", "tint13", "tint14", "tint15",
+					  "tint16", "tint17", "tint18", "tint19",
+					  "tint20", "tint21", "tint22", "tint23",
+					  "tint24", "tint25", "tint26", "tint27",
+					  "tint28", "tint29", "tint30", "tint31",
+					  "bus-err", "ec7tie1-0", "ec7tie2-0",
+					  "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+					  "ec7tiovf-1";
 			clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
 				 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
 			clock-names = "clk", "pclk";
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 1f1d481dc783..0d327464d2ba 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -912,7 +912,27 @@ irqc: interrupt-controller@110a0000 {
 				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
+					  "irq4", "irq5", "irq6", "irq7",
+					  "tint0", "tint1", "tint2", "tint3",
+					  "tint4", "tint5", "tint6", "tint7",
+					  "tint8", "tint9", "tint10", "tint11",
+					  "tint12", "tint13", "tint14", "tint15",
+					  "tint16", "tint17", "tint18", "tint19",
+					  "tint20", "tint21", "tint22", "tint23",
+					  "tint24", "tint25", "tint26", "tint27",
+					  "tint28", "tint29", "tint30", "tint31",
+					  "bus-err", "ec7tie1-0", "ec7tie2-0",
+					  "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
+					  "ec7tiovf-1";
 			clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
 				 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
 			clock-names = "clk", "pclk";
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

* [PATCH 3/3] arm64: dts: renesas: r9a08g045: Add missing interrupts of IRQC node
  2024-02-02  9:39 [PATCH 0/3] Renesas RZ/G2L family and RZ/G3S add missing IRQC interrupts Prabhakar
  2024-02-02  9:39 ` [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts Prabhakar
  2024-02-02  9:39 ` [PATCH 2/3] arm64: dts: renesas: rz-g2l-family: Add missing interrupts from IRQC IP block Prabhakar
@ 2024-02-02  9:39 ` Prabhakar
  2 siblings, 0 replies; 6+ messages in thread
From: Prabhakar @ 2024-02-02  9:39 UTC (permalink / raw)
  To: Thomas Gleixner, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
	Geert Uytterhoeven, Magnus Damm
  Cc: devicetree, linux-renesas-soc, linux-kernel, Prabhakar, Biju Das,
	Claudiu Beznea, Lad Prabhakar

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The IRQC block on RZ/G3S supports ECCRAM error interrupts too, add those
interrupts in the IRQC node.

Fixes: 837918aa3fdd ("arm64: dts: renesas: r9a08g045: Add IA55 interrupt controller node")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index dfee878c0f49..4aaffd1753c8 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -152,7 +152,10 @@ irqc: interrupt-controller@11050000 {
 				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "nmi",
 					  "irq0", "irq1", "irq2", "irq3",
 					  "irq4", "irq5", "irq6", "irq7",
@@ -164,7 +167,8 @@ irqc: interrupt-controller@11050000 {
 					  "tint20", "tint21", "tint22", "tint23",
 					  "tint24", "tint25", "tint26", "tint27",
 					  "tint28", "tint29", "tint30", "tint31",
-					  "bus-err";
+					  "bus-err", "ec7tie1-0", "ec7tie2-0",
+					  "ec7tiovf-0";
 			clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
 				 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
 			clock-names = "clk", "pclk";
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2024-02-03 15:28 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-02-02  9:39 [PATCH 0/3] Renesas RZ/G2L family and RZ/G3S add missing IRQC interrupts Prabhakar
2024-02-02  9:39 ` [PATCH 1/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update interrupts Prabhakar
2024-02-02 17:07   ` Conor Dooley
2024-02-03 15:27     ` Lad, Prabhakar
2024-02-02  9:39 ` [PATCH 2/3] arm64: dts: renesas: rz-g2l-family: Add missing interrupts from IRQC IP block Prabhakar
2024-02-02  9:39 ` [PATCH 3/3] arm64: dts: renesas: r9a08g045: Add missing interrupts of IRQC node Prabhakar

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