* [PATCH v2 1/2] cache: Add StarFive StarLink cache management for StarFive JH8100
2024-04-23 7:26 [PATCH v2 0/2] Add StarFive's JH8100 StarLink Cache Controller Joshua Yeong
@ 2024-04-23 7:26 ` Joshua Yeong
2024-04-23 15:54 ` Conor Dooley
2024-04-23 7:26 ` [PATCH v2 2/2] dt-bindings: cache: Add docs for StarFive Starlink cache controller Joshua Yeong
1 sibling, 1 reply; 6+ messages in thread
From: Joshua Yeong @ 2024-04-23 7:26 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, conor, paul.walmsley, palmer, aou,
joshua.yeong, leyfoon.tan, jeeheng.sia
Cc: devicetree, linux-kernel, linux-riscv
Add StarFive Starlink cache management driver for
JH8100 SoC. This driver enables RISC-V
non-standard cache operation on JH8100 that does
not support Zicbom extension instructions.
Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
---
drivers/cache/Kconfig | 9 ++
drivers/cache/Makefile | 1 +
drivers/cache/starfive_starlink_cache.c | 132 ++++++++++++++++++++++++
3 files changed, 142 insertions(+)
create mode 100644 drivers/cache/starfive_starlink_cache.c
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index 9345ce4976d7..9181cd391f53 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -14,4 +14,13 @@ config SIFIVE_CCACHE
help
Support for the composable cache controller on SiFive platforms.
+config STARFIVE_STARLINK_CACHE
+ bool "StarFive StarLink Cache controller"
+ depends on RISCV
+ depends on ARCH_STARFIVE
+ select RISCV_DMA_NONCOHERENT
+ select RISCV_NONSTANDARD_CACHE_OPS
+ help
+ Support for the StarLink cache controller on StarFive platforms.
+
endmenu
diff --git a/drivers/cache/Makefile b/drivers/cache/Makefile
index 7657cff3bd6c..8ff8b47ac3f7 100644
--- a/drivers/cache/Makefile
+++ b/drivers/cache/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_AX45MP_L2_CACHE) += ax45mp_cache.o
obj-$(CONFIG_SIFIVE_CCACHE) += sifive_ccache.o
+obj-$(CONFIG_STARFIVE_STARLINK_CACHE) += starfive_starlink_cache.o
diff --git a/drivers/cache/starfive_starlink_cache.c b/drivers/cache/starfive_starlink_cache.c
new file mode 100644
index 000000000000..96fd6a4f4c08
--- /dev/null
+++ b/drivers/cache/starfive_starlink_cache.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Non-coherent cache functions for StarFive's Starlink cache controller
+ *
+ * Copyright (C) 2024 Shanghai StarFive Technology Co., Ltd.
+ *
+ * Author: Joshua Yeong <joshua.yeong@starfivetech.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cacheflush.h>
+#include <linux/iopoll.h>
+#include <linux/of_address.h>
+
+#include <asm/dma-noncoherent.h>
+
+#define STARLINK_CACHE_FLUSH_START_ADDR 0x0
+#define STARLINK_CACHE_FLUSH_END_ADDR 0x8
+#define STARLINK_CACHE_FLUSH_CTL 0x10
+#define STARLINK_CACHE_CACHE_ALIGN 0x40
+
+#define STARLINK_CACHE_ADDRESS_RANGE_MASK GENMASK(39, 0)
+#define STARLINK_CACHE_FLUSH_CTL_MODE_MASK GENMASK(2, 1)
+#define STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK BIT(0)
+
+#define STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE 0
+#define STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE 1
+#define STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED 2
+#define STARLINK_CACHE_FLUSH_TIMEOUT_US 5000000
+
+struct starlink_cache_priv {
+ void __iomem *base_addr;
+};
+
+static struct starlink_cache_priv starlink_cache_priv;
+
+static void starlink_cache_flush_complete(void)
+{
+ volatile void __iomem *_ctl = starlink_cache_priv.base_addr +
+ STARLINK_CACHE_FLUSH_CTL;
+ u64 v;
+
+ if (readq_poll_timeout_atomic((_ctl), v,
+ !(v & STARLINK_CACHE_FLUSH_CTL_ENABLE_MASK), 1,
+ STARLINK_CACHE_FLUSH_TIMEOUT_US))
+ WARN(1, "StarFive Starlink cache flush operation timeout\n");
+}
+
+static void starlink_cache_dma_cache_wback(phys_addr_t paddr, unsigned long size)
+{
+ writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_START_ADDR);
+ writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_END_ADDR);
+
+ mb();
+ writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
+ STARLINK_CACHE_FLUSH_CTL_CLEAN_SHARED),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_CTL);
+
+ starlink_cache_flush_complete();
+}
+
+static void starlink_cache_dma_cache_invalidate(phys_addr_t paddr, unsigned long size)
+{
+ writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_START_ADDR);
+ writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_END_ADDR);
+
+ mb();
+ writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
+ STARLINK_CACHE_FLUSH_CTL_MAKE_INVALIDATE),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_CTL);
+
+ starlink_cache_flush_complete();
+}
+
+static void starlink_cache_dma_cache_wback_inv(phys_addr_t paddr, unsigned long size)
+{
+ writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_START_ADDR);
+ writeq(FIELD_PREP(STARLINK_CACHE_ADDRESS_RANGE_MASK, paddr + size),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_END_ADDR);
+
+ mb();
+ writeq(FIELD_PREP(STARLINK_CACHE_FLUSH_CTL_MODE_MASK,
+ STARLINK_CACHE_FLUSH_CTL_CLEAN_INVALIDATE),
+ starlink_cache_priv.base_addr + STARLINK_CACHE_FLUSH_CTL);
+
+ starlink_cache_flush_complete();
+}
+
+static const struct riscv_nonstd_cache_ops starlink_cache_ops = {
+ .wback = &starlink_cache_dma_cache_wback,
+ .inv = &starlink_cache_dma_cache_invalidate,
+ .wback_inv = &starlink_cache_dma_cache_wback_inv,
+};
+
+static const struct of_device_id starlink_cache_ids[] = {
+ { .compatible = "starfive,jh8100-starlink-cache" },
+ { /* sentinel */ }
+};
+
+static int __init starlink_cache_init(void)
+{
+ struct device_node *np;
+ u32 block_size = 0;
+
+ np = of_find_matching_node(NULL, starlink_cache_ids);
+ if (!of_device_is_available(np))
+ return -ENODEV;
+
+ of_property_read_u32(np, "cache-block-size", &block_size);
+
+ if (!block_size)
+ return -ENODEV;
+
+ if (block_size & STARLINK_CACHE_CACHE_ALIGN)
+ return -ENODEV;
+
+ starlink_cache_priv.base_addr = of_iomap(np, 0);
+ if (!starlink_cache_priv.base_addr)
+ return -ENOMEM;
+
+ riscv_cbom_block_size = block_size;
+ riscv_noncoherent_supported();
+ riscv_noncoherent_register_cache_ops(&starlink_cache_ops);
+
+ return 0;
+}
+early_initcall(starlink_cache_init);
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH v2 2/2] dt-bindings: cache: Add docs for StarFive Starlink cache controller
2024-04-23 7:26 [PATCH v2 0/2] Add StarFive's JH8100 StarLink Cache Controller Joshua Yeong
2024-04-23 7:26 ` [PATCH v2 1/2] cache: Add StarFive StarLink cache management for StarFive JH8100 Joshua Yeong
@ 2024-04-23 7:26 ` Joshua Yeong
2024-04-23 10:30 ` Rob Herring
2024-04-23 15:41 ` Conor Dooley
1 sibling, 2 replies; 6+ messages in thread
From: Joshua Yeong @ 2024-04-23 7:26 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, conor, paul.walmsley, palmer, aou,
joshua.yeong, leyfoon.tan, jeeheng.sia
Cc: devicetree, linux-kernel, linux-riscv
Add DT binding documentation used by StarFive's
JH8100 SoC Starlink cache controller.
Signed-off-by: Joshua Yeong <joshua.yeong@starfivetech.com>
---
.../cache/starfive,jh8100-starlink-cache.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
diff --git a/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
new file mode 100644
index 000000000000..a8f39baca6cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/starfive,starlink-500-cache.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive StarLink-500 Cache Controller
+
+maintainers:
+ - Joshua Yeong <joshua.yeong@starfivetech.com>
+
+description:
+ StarFive's JH8100 StarLink Cache Controller manages the L3 cache shared
+ between clusters of CPU cores. The cache driver enables RISC-V non-standard
+ cache management as an alternative to instructions in the RISC-V Zicbom
+ extension.
+
+allOf:
+ - $ref: /schemas/cache-controller.yaml#
+
+# We need a select here so we don't match all nodes with 'cache'
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jh8100-starlink-cache
+
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: starfive,jh8100-starlink-cache
+ - const: cache
+
+ reg:
+ maxItems: 1
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - cache-block-size
+ - cache-level
+ - cache-sets
+ - cache-size
+ - cache-unified
+
+examples:
+ - |
+ cache-controller@15000000 {
+ compatible = "starfive,jh8100-starlink-cache", "cache";
+ reg = <0x15000000 0x278>;
+ cache-block-size = <64>;
+ cache-level = <3>;
+ cache-sets = <8192>;
+ cache-size = <0x400000>;
+ cache-unified;
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread