[PATCH 0/4] Add CPG support for RZ/V2H(P) SoC

[PATCH 0/4] Add CPG support for RZ/V2H(P) SoC

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series aims to add the CPG support for the Renesas RZ/V2H(P) SoC.

A separate CPG core driver is added as compared to the RZ/G2L as the
RZ/V2H(P) SoC varies in terms of features and registers.

Cheers,
Prabhakar

Lad Prabhakar (4):
  dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG driver
  dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions
  clk: renesas: Add RZ/V2H CPG core wrapper driver
  clk: renesas: Add RZ/V2H(P) CPG helper driver

 .../bindings/clock/renesas,rzv2h-cpg.yaml     |  78 ++
 drivers/clk/renesas/Kconfig                   |   5 +
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/r9a09g057-cpg.c           | 112 +++
 drivers/clk/renesas/rzv2h-cpg.c               | 677 ++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h               | 151 ++++
 include/dt-bindings/clock/r9a09g057-cpg.h     | 644 +++++++++++++++++
 7 files changed, 1668 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
 create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c
 create mode 100644 drivers/clk/renesas/rzv2h-cpg.c
 create mode 100644 drivers/clk/renesas/rzv2h-cpg.h
 create mode 100644 include/dt-bindings/clock/r9a09g057-cpg.h

-- 
2.34.1

[PATCH 1/4] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG driver

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document the device tree bindings of the Renesas RZ/V2H(P) SoC
Clock Pulse Generator (CPG).

CPG block handles the below operations:
- Handles the generation and control of clock signals for the IP modules
- The generation and control of resets
- Control over booting
- Low power consumption and the power supply domains

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../bindings/clock/renesas,rzv2h-cpg.yaml     | 78 +++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
new file mode 100644
index 000000000000..baa0f2a5b6f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
+
+maintainers:
+  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+
+description: |
+  On Renesas RZ/V2H(P) SoC's, the CPG (Clock Pulse Generator) handles the generation
+  and control of clock signals for the IP modules, the generation and control of resets,
+  and control over booting, low power consumption and the power supply domains.
+
+properties:
+  compatible:
+    const: renesas,r9a09g057-cpg
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    description:
+      Clock source to CPG can be either from external clock input (EXCLK) or
+      crystal oscillator (XIN/XOUT).
+    const: extal
+
+  '#clock-cells':
+    description: |
+      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
+        and a core clock reference, as defined in
+        <dt-bindings/clock/r9a09g057-cpg.h>,
+      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
+        a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
+    const: 2
+
+  '#power-domain-cells':
+    description:
+      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
+      can be power-managed through Module Standby should refer to the CPG device
+      node in their "power-domains" property, as documented by the generic PM
+      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
+      The power domain specifiers defined in <dt-bindings/clock/r9a09g057-cpg.h> could
+      be used to reference individual CPG power domains.
+
+  '#reset-cells':
+    description:
+      The single reset specifier cell must be the module number, as defined in
+      <dt-bindings/clock/r9a09g057-cpg.h>.
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - '#power-domain-cells'
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    cpg: clock-controller@10420000 {
+            compatible = "renesas,r9a09g057-cpg";
+            reg = <0x10420000 0x10000>;
+            clocks = <&extal_clk>;
+            clock-names = "extal";
+            #clock-cells = <2>;
+            #power-domain-cells = <0>;
+            #reset-cells = <1>;
+    };
-- 
2.34.1

Re: [PATCH 1/4] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG driver

[Conor Dooley]

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On Fri, May 24, 2024 at 09:27:57AM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Document the device tree bindings of the Renesas RZ/V2H(P) SoC
> Clock Pulse Generator (CPG).
> 
> CPG block handles the below operations:
> - Handles the generation and control of clock signals for the IP modules
> - The generation and control of resets
> - Control over booting
> - Low power consumption and the power supply domains
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../bindings/clock/renesas,rzv2h-cpg.yaml     | 78 +++++++++++++++++++
>  1 file changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> new file mode 100644
> index 000000000000..baa0f2a5b6f9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
> +
> +maintainers:
> +  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +
> +description: |
> +  On Renesas RZ/V2H(P) SoC's, the CPG (Clock Pulse Generator) handles the generation
> +  and control of clock signals for the IP modules, the generation and control of resets,
> +  and control over booting, low power consumption and the power supply domains.
> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g057-cpg
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    description:
> +      Clock source to CPG can be either from external clock input (EXCLK) or
> +      crystal oscillator (XIN/XOUT).

I think this description should be in clocks, not clock names.

> +    const: extal
> +
> +  '#clock-cells':
> +    description: |
> +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> +        and a core clock reference, as defined in
> +        <dt-bindings/clock/r9a09g057-cpg.h>,
> +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> +        a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.

Can you please explain the difference and why it matters? Why isn't the
unique number for a given clock sufficient?

Thanks,
Conor.

> +    const: 2
> +
> +  '#power-domain-cells':
> +    description:
> +      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
> +      can be power-managed through Module Standby should refer to the CPG device
> +      node in their "power-domains" property, as documented by the generic PM
> +      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
> +      The power domain specifiers defined in <dt-bindings/clock/r9a09g057-cpg.h> could
> +      be used to reference individual CPG power domains.
> +
> +  '#reset-cells':
> +    description:
> +      The single reset specifier cell must be the module number, as defined in
> +      <dt-bindings/clock/r9a09g057-cpg.h>.
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - '#power-domain-cells'
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    cpg: clock-controller@10420000 {
> +            compatible = "renesas,r9a09g057-cpg";
> +            reg = <0x10420000 0x10000>;
> +            clocks = <&extal_clk>;
> +            clock-names = "extal";
> +            #clock-cells = <2>;
> +            #power-domain-cells = <0>;
> +            #reset-cells = <1>;
> +    };
> -- 
> 2.34.1
> 

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Re: [PATCH 1/4] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG driver

[Geert Uytterhoeven]

Hi Prabhakar,

Thanks for your patch!

Please drop "driver" from the one-line summary.

On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Document the device tree bindings of the Renesas RZ/V2H(P) SoC

s/of/for/

> Clock Pulse Generator (CPG).
>
> CPG block handles the below operations:
> - Handles the generation and control of clock signals for the IP modules

Please drop "Handles the"

> - The generation and control of resets

Please drop "The".

> - Control over booting
> - Low power consumption and the power supply domains

Please drop "the".

>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
> +
> +maintainers:
> +  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> +
> +description: |
> +  On Renesas RZ/V2H(P) SoC's, the CPG (Clock Pulse Generator) handles the generation

SoCs

> +  and control of clock signals for the IP modules, the generation and control of resets,
> +  and control over booting, low power consumption and the power supply domains.

Please drop "the".

> +
> +properties:
> +  compatible:
> +    const: renesas,r9a09g057-cpg
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    description:
> +      Clock source to CPG can be either from external clock input (EXCLK) or
> +      crystal oscillator (XIN/XOUT).
> +    const: extal

According to Figure 4.4-1 ("CPG Functional Block Diagram"), there are 3
(RTC, audio, main).

> +
> +  '#clock-cells':
> +    description: |
> +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> +        and a core clock reference, as defined in
> +        <dt-bindings/clock/r9a09g057-cpg.h>,
> +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> +        a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
> +    const: 2

I understand this will be changed to 1, the clock number?

> +  '#power-domain-cells':
> +    description:
> +      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
> +      can be power-managed through Module Standby should refer to the CPG device
> +      node in their "power-domains" property, as documented by the generic PM
> +      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
> +      The power domain specifiers defined in <dt-bindings/clock/r9a09g057-cpg.h> could
> +      be used to reference individual CPG power domains.

The latter suggests "const: 1".
But the example below uses zero, as does the code?

> +
> +  '#reset-cells':
> +    description:
> +      The single reset specifier cell must be the module number, as defined in

reset number (or index).

> +      <dt-bindings/clock/r9a09g057-cpg.h>.
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - '#clock-cells'
> +  - '#power-domain-cells'
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    cpg: clock-controller@10420000 {
> +            compatible = "renesas,r9a09g057-cpg";
> +            reg = <0x10420000 0x10000>;
> +            clocks = <&extal_clk>;
> +            clock-names = "extal";
> +            #clock-cells = <2>;
> +            #power-domain-cells = <0>;
> +            #reset-cells = <1>;
> +    };

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/4] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG driver

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, Jun 4, 2024 at 5:49 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document the device tree bindings of the Renesas RZ/V2H(P) SoC
> > Clock Pulse Generator (CPG).
> >
> > CPG block handles the below operations:
> > - Handles the generation and control of clock signals for the IP modules
> > - The generation and control of resets
> > - Control over booting
> > - Low power consumption and the power supply domains
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> > +
> > +  '#clock-cells':
> > +    description: |
> > +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> > +        and a core clock reference, as defined in
> > +        <dt-bindings/clock/r9a09g057-cpg.h>,
> > +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> > +        a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
> > +    const: 2
>
> I understand this will be changed to 1, the clock number?

We typically come up with our own definitions in header files if there
are no suitable module numbers listed in the hardware documentation.

For RZ/V2H, you could use a combination (e.g. concatenation) of the
column (register) and row (bit) numbers from Tables 4.4-14-19
("Specifications of the CPG_CLKON_m Registers") and Tables 4.4-22-25
("Specifications of the CPG_RST_m Registers") as the clock resp. reset
number, like is done on R-Car Gen2+ SoCs (see MOD_CLK_PACK() for
conversion from sparse to packed module numbers).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/4] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG driver

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Wed, Jun 5, 2024 at 10:42 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Tue, Jun 4, 2024 at 5:49 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Document the device tree bindings of the Renesas RZ/V2H(P) SoC
> > > Clock Pulse Generator (CPG).
> > >
> > > CPG block handles the below operations:
> > > - Handles the generation and control of clock signals for the IP modules
> > > - The generation and control of resets
> > > - Control over booting
> > > - Low power consumption and the power supply domains
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> > > +
> > > +  '#clock-cells':
> > > +    description: |
> > > +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> > > +        and a core clock reference, as defined in
> > > +        <dt-bindings/clock/r9a09g057-cpg.h>,
> > > +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> > > +        a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
> > > +    const: 2
> >
> > I understand this will be changed to 1, the clock number?
>
> We typically come up with our own definitions in header files if there
> are no suitable module numbers listed in the hardware documentation.
>
Agreed.

> For RZ/V2H, you could use a combination (e.g. concatenation) of the
> column (register) and row (bit) numbers from Tables 4.4-14-19
> ("Specifications of the CPG_CLKON_m Registers") and Tables 4.4-22-25
> ("Specifications of the CPG_RST_m Registers") as the clock resp. reset
> number, like is done on R-Car Gen2+ SoCs (see MOD_CLK_PACK() for
> conversion from sparse to packed module numbers).
>
Thanks for the pointer.

I'll model as per your suggestion (this way we can avoid adding any
macros for module clocks) and dont have to worry about reserved bits.

Cheers,
Prabhakar

Re: [PATCH 1/4] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG driver

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Tue, Jun 4, 2024 at 4:50 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> Please drop "driver" from the one-line summary.
>
OK, I will drop it.

> On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Document the device tree bindings of the Renesas RZ/V2H(P) SoC
>
> s/of/for/
>
OK.

> > Clock Pulse Generator (CPG).
> >
> > CPG block handles the below operations:
> > - Handles the generation and control of clock signals for the IP modules
>
> Please drop "Handles the"
>
OK.

> > - The generation and control of resets
>
> Please drop "The".
>
OK.

> > - Control over booting
> > - Low power consumption and the power supply domains
>
> Please drop "the".
>
OK.

> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
> > @@ -0,0 +1,78 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
> > +
> > +maintainers:
> > +  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > +
> > +description: |
> > +  On Renesas RZ/V2H(P) SoC's, the CPG (Clock Pulse Generator) handles the generation
>
> SoCs
>
OK.

> > +  and control of clock signals for the IP modules, the generation and control of resets,
> > +  and control over booting, low power consumption and the power supply domains.
>
> Please drop "the".
>
OK.

> > +
> > +properties:
> > +  compatible:
> > +    const: renesas,r9a09g057-cpg
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  clock-names:
> > +    description:
> > +      Clock source to CPG can be either from external clock input (EXCLK) or
> > +      crystal oscillator (XIN/XOUT).
> > +    const: extal
>
> According to Figure 4.4-1 ("CPG Functional Block Diagram"), there are 3
> (RTC, audio, main).
>
Agreed, I will add the below:
- QEXTAL
- RTXIN
- AUDIO_EXTAL
- AUDIO_CLKB
- AUDIO_CLKC

> > +
> > +  '#clock-cells':
> > +    description: |
> > +      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> > +        and a core clock reference, as defined in
> > +        <dt-bindings/clock/r9a09g057-cpg.h>,
> > +      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> > +        a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
> > +    const: 2
>
> I understand this will be changed to 1, the clock number?
>
I'll keep this '2'. I will introduce core clocks (clocks which cannot
be controlled by  CLKON_m register) for example,
- SYS_0_PCLK
- CA55_0_CORE_CLK[x]
- IOTOP_0_SHCLK.

> > +  '#power-domain-cells':
> > +    description:
> > +      SoC devices that are part of the CPG/Module Standby Mode Clock Domain and
> > +      can be power-managed through Module Standby should refer to the CPG device
> > +      node in their "power-domains" property, as documented by the generic PM
> > +      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
> > +      The power domain specifiers defined in <dt-bindings/clock/r9a09g057-cpg.h> could
> > +      be used to reference individual CPG power domains.
>
> The latter suggests "const: 1".
> But the example below uses zero, as does the code?
>
This should be '0' indeed.

> > +
> > +  '#reset-cells':
> > +    description:
> > +      The single reset specifier cell must be the module number, as defined in
>
> reset number (or index).
>
OK.

Cheers,
Prabhakar

[PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
(CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
Hardware User's Manual (Rev.1.01, Feb. 2024).

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 include/dt-bindings/clock/r9a09g057-cpg.h | 644 ++++++++++++++++++++++
 1 file changed, 644 insertions(+)
 create mode 100644 include/dt-bindings/clock/r9a09g057-cpg.h

diff --git a/include/dt-bindings/clock/r9a09g057-cpg.h b/include/dt-bindings/clock/r9a09g057-cpg.h
new file mode 100644
index 000000000000..01b9eadcf031
--- /dev/null
+++ b/include/dt-bindings/clock/r9a09g057-cpg.h
@@ -0,0 +1,644 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* Clock list */
+#define R9A09G057_SYS_0_PCLK				0
+#define R9A09G057_DMAC_0_ACLK				1
+#define R9A09G057_DMAC_1_ACLK				2
+#define R9A09G057_DMAC_2_ACLK				3
+#define R9A09G057_DMAC_3_ACLK				4
+#define R9A09G057_DMAC_4_ACLK				5
+#define R9A09G057_ICU_0_PCLK_I				6
+#define R9A09G057_CRC_0_CLK_CRC				7
+#define R9A09G057_CA55_0_CORE_CLK0			8
+#define R9A09G057_CA55_0_CORE_CLK1			9
+#define R9A09G057_CA55_0_CORE_CLK2			10
+#define R9A09G057_CA55_0_CORE_CLK3			11
+#define R9A09G057_CA55_0_SCLK				12
+#define R9A09G057_CA55_0_PCLK				13
+#define R9A09G057_CA55_0_ATCLK				14
+#define R9A09G057_CA55_0_GICCLK				15
+#define R9A09G057_CA55_0_PERIPHCLK			16
+#define R9A09G057_CA55_0_ACLK				17
+#define R9A09G057_CA55_0_TSCLK				18
+#define R9A09G057_CR8_0_CLK				19
+#define R9A09G057_CR8_0_PERIPHCLK			20
+#define R9A09G057_CR8_0_ACLK				21
+#define R9A09G057_CR8_0_ATCLK0				22
+#define R9A09G057_CR8_0_TSCLK				23
+#define R9A09G057_CR8_0_DBGCLK				24
+#define R9A09G057_CM33_CLK0				25
+#define R9A09G057_CM33_CLK1				26
+#define R9A09G057_GIC_0_GICCLK				27
+#define R9A09G057_SRAM_0_ACLK				28
+#define R9A09G057_SRAM_1_ACLK				29
+#define R9A09G057_SRAM_2_ACLK				30
+#define R9A09G057_SRAM_3_ACLK				31
+#define R9A09G057_SRAM_4_ACLK				32
+#define R9A09G057_SRAM_5_ACLK				33
+#define R9A09G057_SRAM_6_ACLK				34
+#define R9A09G057_SRAM_7_ACLK				35
+#define R9A09G057_SRAM_8_ACLK				36
+#define R9A09G057_SRAM_9_ACLK				37
+#define R9A09G057_SRAM_10_ACLK				38
+#define R9A09G057_SRAM_11_ACLK				39
+#define R9A09G057_BTROM_0_ACLK				40
+#define R9A09G057_CST_0_CS_CLK				41
+#define R9A09G057_CST_0_TS_CLK				42
+#define R9A09G057_CST_0_APB_SB_CLK			43
+#define R9A09G057_CST_0_APB_CA55_CLK			44
+#define R9A09G057_CST_0_APB_CR8_CLK			45
+#define R9A09G057_CST_0_APB_CM33_CLK			46
+#define R9A09G057_CST_0_AHB_CM33_CLK			47
+#define R9A09G057_CST_0_AHB_ATH_CLK			48
+#define R9A09G057_CST_0_ATB_CA55_CLK			49
+#define R9A09G057_CST_0_ATB_CR8_CLK			50
+#define R9A09G057_CST_0_ATB_CM33_CLK			51
+#define R9A09G057_CST_0_ATB_CST_CLK			52
+#define R9A09G057_CST_0_SWCLKTCK			53
+#define R9A09G057_CST_0_AXI_ETR_CLK			54
+#define R9A09G057_CST_0_AXI_SB_CLK			55
+#define R9A09G057_SYC_0_CNT_CLK				56
+#define R9A09G057_MHU_0_PCLK				57
+#define R9A09G057_GPT_0_PCLK_SFR			58
+#define R9A09G057_GPT_0_CLKS_GPT			59
+#define R9A09G057_GPT_1_PCLK_SFR			60
+#define R9A09G057_GPT_1_CLKS_GPT			61
+#define R9A09G057_POEGA_0_PCLK				62
+#define R9A09G057_POEGB_0_PCLK				63
+#define R9A09G057_POEGC_0_PCLK				64
+#define R9A09G057_POEGD_0_PCLK				65
+#define R9A09G057_POEGA_1_PCLK				66
+#define R9A09G057_POEGB_1_PCLK				67
+#define R9A09G057_POEGC_1_PCLK				68
+#define R9A09G057_POEGD_1_PCLK				69
+#define R9A09G057_CMTW_0_CLKM				70
+#define R9A09G057_CMTW_1_CLKM				71
+#define R9A09G057_CMTW_2_CLKM				72
+#define R9A09G057_CMTW_3_CLKM				73
+#define R9A09G057_CMTW_4_CLKM				74
+#define R9A09G057_CMTW_5_CLKM				75
+#define R9A09G057_CMTW_6_CLKM				76
+#define R9A09G057_CMTW_7_CLKM				77
+#define R9A09G057_GTM_0_PCLK				78
+#define R9A09G057_GTM_1_PCLK				79
+#define R9A09G057_GTM_2_PCLK				80
+#define R9A09G057_GTM_3_PCLK				81
+#define R9A09G057_GTM_4_PCLK				82
+#define R9A09G057_GTM_5_PCLK				83
+#define R9A09G057_GTM_6_PCLK				84
+#define R9A09G057_GTM_7_PCLK				85
+#define R9A09G057_WDT_0_CLKP				86
+#define R9A09G057_WDT_0_CLK_LOCO			87
+#define R9A09G057_WDT_1_CLKP				88
+#define R9A09G057_WDT_1_CLK_LOCO			89
+#define R9A09G057_WDT_2_CLKP				90
+#define R9A09G057_WDT_2_CLK_LOCO			91
+#define R9A09G057_WDT_3_CLKP				92
+#define R9A09G057_WDT_3_CLK_LOCO			93
+#define R9A09G057_RTC_0_CLK_RTC				94
+#define R9A09G057_RSPI_0_PCLK				95
+#define R9A09G057_RSPI_0_PCLK_SFR			96
+#define R9A09G057_RSPI_0_TCLK				97
+#define R9A09G057_RSPI_1_PCLK				98
+#define R9A09G057_RSPI_1_PCLK_SFR			99
+#define R9A09G057_RSPI_1_TCLK				100
+#define R9A09G057_RSPI_2_PCLK				101
+#define R9A09G057_RSPI_2_PCLK_SFR			102
+#define R9A09G057_RSPI_2_TCLK				103
+#define R9A09G057_RSCI_0_PCLK				104
+#define R9A09G057_RSCI_0_PCLK_SFR			105
+#define R9A09G057_RSCI_0_TCLK				106
+#define R9A09G057_RSCI_0_PS_PS3_N			107
+#define R9A09G057_RSCI_0_PS_PS2_N			108
+#define R9A09G057_RSCI_0_PS_PS1_N			109
+#define R9A09G057_RSCI_1_PCLK				110
+#define R9A09G057_RSCI_1_PCLK_SFR			111
+#define R9A09G057_RSCI_1_TCLK				112
+#define R9A09G057_RSCI_1_PS_PS3_N			113
+#define R9A09G057_RSCI_1_PS_PS2_N			114
+#define R9A09G057_RSCI_1_PS_PS1_N			115
+#define R9A09G057_RSCI_2_PCLK				116
+#define R9A09G057_RSCI_2_PCLK_SFR			117
+#define R9A09G057_RSCI_2_TCLK				118
+#define R9A09G057_RSCI_2_PS_PS3_N			119
+#define R9A09G057_RSCI_2_PS_PS2_N			120
+#define R9A09G057_RSCI_2_PS_PS1_N			121
+#define R9A09G057_RSCI_3_PCLK				122
+#define R9A09G057_RSCI_3_PCLK_SFR			123
+#define R9A09G057_RSCI_3_TCLK				124
+#define R9A09G057_RSCI_3_PS_PS3_N			125
+#define R9A09G057_RSCI_3_PS_PS2_N			126
+#define R9A09G057_RSCI_3_PS_PS1_N			127
+#define R9A09G057_RSCI_4_PCLK				128
+#define R9A09G057_RSCI_4_PCLK_SFR			129
+#define R9A09G057_RSCI_4_TCLK				130
+#define R9A09G057_RSCI_4_PS_PS3_N			131
+#define R9A09G057_RSCI_4_PS_PS2_N			132
+#define R9A09G057_RSCI_4_PS_PS1_N			133
+#define R9A09G057_RSCI_5_PCLK				134
+#define R9A09G057_RSCI_5_PCLK_SFR			135
+#define R9A09G057_RSCI_5_TCLK				136
+#define R9A09G057_RSCI_5_PS_PS3_N			137
+#define R9A09G057_RSCI_5_PS_PS2_N			138
+#define R9A09G057_RSCI_5_PS_PS1_N			139
+#define R9A09G057_RSCI_6_PCLK				140
+#define R9A09G057_RSCI_6_PCLK_SFR			141
+#define R9A09G057_RSCI_6_TCLK				142
+#define R9A09G057_RSCI_6_PS_PS3_N			143
+#define R9A09G057_RSCI_6_PS_PS2_N			144
+#define R9A09G057_RSCI_6_PS_PS1_N			145
+#define R9A09G057_RSCI_7_PCLK				146
+#define R9A09G057_RSCI_7_PCLK_SFR			147
+#define R9A09G057_RSCI_7_TCLK				148
+#define R9A09G057_RSCI_7_PS_PS3_N			149
+#define R9A09G057_RSCI_7_PS_PS2_N			150
+#define R9A09G057_RSCI_7_PS_PS1_N			151
+#define R9A09G057_RSCI_8_PCLK				152
+#define R9A09G057_RSCI_8_PCLK_SFR			153
+#define R9A09G057_RSCI_8_TCLK				154
+#define R9A09G057_RSCI_8_PS_PS3_N			155
+#define R9A09G057_RSCI_8_PS_PS2_N			156
+#define R9A09G057_RSCI_8_PS_PS1_N			157
+#define R9A09G057_RSCI_9_PCLK				158
+#define R9A09G057_RSCI_9_PCLK_SFR			159
+#define R9A09G057_RSCI_9_TCLK				160
+#define R9A09G057_RSCI_9_PS_PS3_N			161
+#define R9A09G057_RSCI_9_PS_PS2_N			162
+#define R9A09G057_RSCI_9_PS_PS1_N			163
+#define R9A09G057_SCIF_0_CLK_PCK			164
+#define R9A09G057_I3C_0_PCLKRW				165
+#define R9A09G057_I3C_0_PCLK				166
+#define R9A09G057_I3C_0_TCLK				167
+#define R9A09G057_RIIC_8_CKM				168
+#define R9A09G057_RIIC_0_CKM				169
+#define R9A09G057_RIIC_1_CKM				170
+#define R9A09G057_RIIC_2_CKM				171
+#define R9A09G057_RIIC_3_CKM				172
+#define R9A09G057_RIIC_4_CKM				173
+#define R9A09G057_RIIC_5_CKM				174
+#define R9A09G057_RIIC_6_CKM				175
+#define R9A09G057_RIIC_7_CKM				176
+#define R9A09G057_CANFD_0_PCLK				177
+#define R9A09G057_CANFD_0_CLK_RAM			178
+#define R9A09G057_CANFD_0_CLKC				179
+#define R9A09G057_SPI_HCLK				180
+#define R9A09G057_SPI_ACLK				181
+#define R9A09G057_SPI_CLK_SPI				182
+#define R9A09G057_SPI_CLK_SPIX2				183
+#define R9A09G057_IOTOP_0_SHCLK				184
+#define R9A09G057_SDHI_0_IMCLK				185
+#define R9A09G057_SDHI_0_IMCLK2				186
+#define R9A09G057_SDHI_0_CLK_HS				187
+#define R9A09G057_SDHI_0_ACLK				188
+#define R9A09G057_SDHI_1_IMCLK				189
+#define R9A09G057_SDHI_1_IMCLK2				190
+#define R9A09G057_SDHI_1_CLK_HS				191
+#define R9A09G057_SDHI_1_ACLK				192
+#define R9A09G057_SDHI_2_IMCLK				193
+#define R9A09G057_SDHI_2_IMCLK2				194
+#define R9A09G057_SDHI_2_CLK_HS				195
+#define R9A09G057_SDHI_2_ACLK				196
+#define R9A09G057_USB30_CLK_RESERVED0			197
+#define R9A09G057_USB30_CLK_RESERVED1			198
+#define R9A09G057_USB30_CLK_RESERVED2			199
+#define R9A09G057_USB30_CLK_RESERVED3			200
+#define R9A09G057_USB31_CLK_RESERVED0			201
+#define R9A09G057_USB31_CLK_RESERVED1			202
+#define R9A09G057_USB31_CLK_RESERVED2			203
+#define R9A09G057_USB31_CLK_RESERVED3			204
+#define R9A09G057_USB20_CLK_RESERVED0			205
+#define R9A09G057_USB21_CLK_RESERVED0			206
+#define R9A09G057_USB20_USB21_CLK_RESERVED0		207
+#define R9A09G057_USB20_CLK_RESERVED1			208
+#define R9A09G057_USB21_CLK_RESERVED1			209
+#define R9A09G057_USB20_CLK_RESERVED2			210
+#define R9A09G057_USB21_CLK_RESERVED2			211
+#define R9A09G057_GBETH0_CLK_RESERVED0			212
+#define R9A09G057_GBETH0_CLK_RESERVED1			213
+#define R9A09G057_GBETH0_CLK_RESERVED2			214
+#define R9A09G057_GBETH0_CLK_RESERVED3			215
+#define R9A09G057_GBETH0_CLK_RESERVED4			216
+#define R9A09G057_GBETH0_CLK_RESERVED5			217
+#define R9A09G057_GBETH0_CLK_RESERVED6			218
+#define R9A09G057_GBETH1_CLK_RESERVED0			219
+#define R9A09G057_GBETH1_CLK_RESERVED1			220
+#define R9A09G057_GBETH1_CLK_RESERVED2			221
+#define R9A09G057_GBETH1_CLK_RESERVED3			222
+#define R9A09G057_GBETH1_CLK_RESERVED4			223
+#define R9A09G057_GBETH1_CLK_RESERVED5			224
+#define R9A09G057_GBETH1_CLK_RESERVED6			225
+#define R9A09G057_PCIE_0_ACLK				226
+#define R9A09G057_PCIE_0_CLK_PMU			227
+#define R9A09G057_DDR0_CLK_RESERVED0			228
+#define R9A09G057_DDR0_CLK_RESERVED1			229
+#define R9A09G057_DDR0_CLK_RESERVED2			230
+#define R9A09G057_DDR0_CLK_RESERVED3			231
+#define R9A09G057_DDR0_CLK_RESERVED4			232
+#define R9A09G057_DDR0_CLK_RESERVED5			233
+#define R9A09G057_DDR0_CLK_RESERVED6			234
+#define R9A09G057_DDR1_CLK_RESERVED0			235
+#define R9A09G057_DDR1_CLK_RESERVED1			236
+#define R9A09G057_DDR1_CLK_RESERVED2			237
+#define R9A09G057_DDR1_CLK_RESERVED3			238
+#define R9A09G057_DDR1_CLK_RESERVED4			239
+#define R9A09G057_DDR1_CLK_RESERVED5			240
+#define R9A09G057_DDR1_CLK_RESERVED6			241
+#define R9A09G057_CRU_0_ACLK				242
+#define R9A09G057_CRU_0_VCLK				243
+#define R9A09G057_CRU_0_PCLK				244
+#define R9A09G057_CRU_1_ACLK				245
+#define R9A09G057_CRU_1_VCLK				246
+#define R9A09G057_CRU_1_PCLK				247
+#define R9A09G057_CRU_2_ACLK				248
+#define R9A09G057_CRU_2_VCLK				249
+#define R9A09G057_CRU_2_PCLK				250
+#define R9A09G057_CRU_3_ACLK				251
+#define R9A09G057_CRU_3_VCLK				252
+#define R9A09G057_CRU_3_PCLK				253
+#define R9A09G057_ISP_CLK_RESERVED0			254
+#define R9A09G057_ISP_CLK_RESERVED1			255
+#define R9A09G057_ISP_CLK_RESERVED2			256
+#define R9A09G057_ISP_CLK_RESERVED3			257
+#define R9A09G057_ISU_0_ACLK				258
+#define R9A09G057_ISU_0_PCLK				259
+#define R9A09G057_DSI_0_PCLK				260
+#define R9A09G057_DSI_0_ACLK				261
+#define R9A09G057_DSI_0_VCLK1				262
+#define R9A09G057_DSI_0_LPCLK				263
+#define R9A09G057_DSI_0_PLLREFCLK			264
+#define R9A09G057_LCDC_0_CLK_A				265
+#define R9A09G057_LCDC_0_CLK_P				266
+#define R9A09G057_LCDC_0_CLK_D				267
+#define R9A09G057_GPU_0_CLK				268
+#define R9A09G057_GPU_0_AXI_CLK				269
+#define R9A09G057_GPU_0_ACE_CLK				270
+#define R9A09G057_VCD_0_ACLK				271
+#define R9A09G057_VCD_0_PCLK				272
+#define R9A09G057_SSIF_0_CLK				273
+#define R9A09G057_SCU_0_CLK				274
+#define R9A09G057_SCU_0_CLKX2				275
+#define R9A09G057_DMACPP_0_CLK				276
+#define R9A09G057_ADG_0_CLKS1				277
+#define R9A09G057_ADG_0_CLK_195M			278
+#define R9A09G057_ADG_0_AUDIO_CLKA			279
+#define R9A09G057_ADG_0_AUDIO_CLKB			280
+#define R9A09G057_ADG_0_AUDIO_CLKC			281
+#define R9A09G057_SPDIF_0_CLKP				282
+#define R9A09G057_SPDIF_1_CLKP				283
+#define R9A09G057_SPDIF_2_CLKP				284
+#define R9A09G057_PDM_0_PCLK				285
+#define R9A09G057_PDM_0_PCLK_SFR			286
+#define R9A09G057_PDM_0_CCLK				287
+#define R9A09G057_PDM_1_PCLK				288
+#define R9A09G057_PDM_1_PCLK_SFR			289
+#define R9A09G057_PDM_1_CCLK				290
+#define R9A09G057_ADC_0_PCLK				291
+#define R9A09G057_ADC_0_ADCLK				292
+#define R9A09G057_TSU_0_PCLK				293
+#define R9A09G057_TSU_1_PCLK				294
+#define R9A09G057_OTPC_0_CLKP1D				295
+#define R9A09G057_OTPC_0_PCLK				296
+#define R9A09G057_OTPC_0_SCLK				297
+#define R9A09G057_DRP_0_DCLKIN				298
+#define R9A09G057_DRP_0_ACLK				299
+#define R9A09G057_DRP_0_INITCLK				300
+#define R9A09G057_DRPAI_0_DCLKIN			301
+#define R9A09G057_DRPAI_0_ACLK				302
+#define R9A09G057_DRPAI_0_INITCLK			303
+#define R9A09G057_DRPAI_0_MCLK				304
+#define R9A09G057_RCPU_AXI_CLK200DG_RCP			305
+#define R9A09G057_RCPU_AXI_CLK400DG_ACP			306
+#define R9A09G057_RCPU_AXI_CLK200CF			307
+#define R9A09G057_RCPU_AXI_CLK100CF			308
+#define R9A09G057_RCPU_AXI_CLK50CF			309
+#define R9A09G057_MCPU_AXI_CLK200CG_MCP			310
+#define R9A09G057_MCPU_AXI_CLK100CF_MCP			311
+#define R9A09G057_MCPU_AXI_CLK100CG_MCP			312
+#define R9A09G057_MCPU_AXI_CLK50CG_ADC			313
+#define R9A09G057_MCPU_AXI_CLK50CF_MCP			314
+#define R9A09G057_MCPU_AXI_CLK24			315
+#define R9A09G057_ACPU_AXI_CLK400DG_ACP			316
+#define R9A09G057_ACPU_AXI_CLK200DG_ACP			317
+#define R9A09G057_ACPU_AXI_CLK400DG_DRP			318
+#define R9A09G057_ACPU_AXI_CLK200CG_MCP			319
+#define R9A09G057_ACPU_AXI_CLK200DF			320
+#define R9A09G057_ACPU_AXI_CLK200CF			321
+#define R9A09G057_ACPU_AXI_CLK100DG_ACP			322
+#define R9A09G057_ACPU_AXI_CLK100DF			323
+#define R9A09G057_ACPU_AXI_CLK100CF			324
+#define R9A09G057_ACPU_AXI_CLK24			325
+#define R9A09G057_ACPU_PERI_DDR_AXI_CLK100DG_ACP	326
+#define R9A09G057_VIDEO0_AXI_CLK400DG_ACP		327
+#define R9A09G057_VIDEO0_AXI_CLK400DG_DRP		328
+#define R9A09G057_VIDEO0_AXI_CLK630DG_ISP		329
+#define R9A09G057_ACPU_PERI_VIDEO0_AXI_CLK400DG_ACP	330
+#define R9A09G057_ACPU_PERI_VIDEO0_AXI_CLK100DF		331
+#define R9A09G057_VIDEO1_AXI_CLK400DG_ACP		332
+#define R9A09G057_VIDEO1_AXI_CLK100DG_ACP		333
+#define R9A09G057_VIDEO1_AXI_CLK400DG_DRP		334
+#define R9A09G057_VIDEO1_AXI_CLK400DF			335
+#define R9A09G057_VIDEO1_AXI_CLK630DG_ISU		336
+#define R9A09G057_ACPU_PERI_VIDEO1_AXI_CLK100DG_ACP	337
+#define R9A09G057_ACPU_PERI_VIDEO1_AXI_CLK200DF		338
+#define R9A09G057_ACPU_PERI_VIDEO1_AXI_CLK100DF		339
+#define R9A09G057_DRP_AXI_CLK400DG_DRP			340
+#define R9A09G057_ACPU_PERI_DRP0_AXI_CLK400DG_DRP	341
+#define R9A09G057_ACPU_PERI_DRP1_AXI_CLK400DG_DRP	342
+#define R9A09G057_COM_AXI_CLK400DG_ACP			343
+#define R9A09G057_COM_AXI_CLK200DG_ACP			344
+#define R9A09G057_COM_AXI_CLK400DG_DRP			345
+#define R9A09G057_COM_AXI_CLK200DF			346
+#define R9A09G057_ACPU_PERI_COM0_AXI_CLK400DG_ACP	347
+#define R9A09G057_ACPU_PERI_COM0_AXI_CLK200DG_ACP	348
+#define R9A09G057_ACPU_PERI_COM0_AXI_CLK200DF		349
+#define R9A09G057_ACPU_PERI_COM1_AXI_CLK200DG_ACP	350
+#define R9A09G057_ACPU_PERI_COM1_AXI_CLK200DF		351
+#define R9A09G057_TZCDDR_0_CLK100DG_ACP_PCLK0		352
+#define R9A09G057_TZCDDR_0_CLK100DG_ACP_PCLK1		353
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK0		354
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK1		355
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK2		356
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK3		357
+#define R9A09G057_TZCDDR_0_CLK400DG_ACP_ACLK4		358
+#define R9A09G057_TZCDDR_1_CLK100DG_ACP_PCLK0		359
+#define R9A09G057_TZCDDR_1_CLK100DG_ACP_PCLK1		360
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK0		361
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK1		362
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK2		363
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK3		364
+#define R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK4		365
+
+/* Resets list */
+#define R9A09G057_SYS_0_PRESETN				0
+#define R9A09G057_DMAC_0_ARESETN			1
+#define R9A09G057_DMAC_1_ARESETN			2
+#define R9A09G057_DMAC_2_ARESETN			3
+#define R9A09G057_DMAC_3_ARESETN			4
+#define R9A09G057_DMAC_4_ARESETN			5
+#define R9A09G057_ICU_0_PRESETN_I			6
+#define R9A09G057_CRC_0_RST				7
+#define R9A09G057_CA55_RESET0				8
+#define R9A09G057_CA55_RESET1				9
+#define R9A09G057_CA55_RESET2				10
+#define R9A09G057_CA55_RESET3				11
+#define R9A09G057_CA55_RESET4				12
+#define R9A09G057_CA55_RESET5				13
+#define R9A09G057_CA55_RESET6				14
+#define R9A09G057_CA55_RESET7				15
+#define R9A09G057_CA55_RESET8				16
+#define R9A09G057_CA55_RESET9				17
+#define R9A09G057_CA55_RESET10				18
+#define R9A09G057_CA55_RESET11				19
+#define R9A09G057_CA55_RESET12				20
+#define R9A09G057_CA55_RESET13				21
+#define R9A09G057_CA55_RESET14				22
+#define R9A09G057_CA55_RESET15				23
+#define R9A09G057_CA55_RESET16				24
+#define R9A09G057_CR8_0_NCPURESET1			25
+#define R9A09G057_CR8_0_NCPURESET0			26
+#define R9A09G057_CR8_0_NPERIPHRESET			27
+#define R9A09G057_CR8_0_NSCURESET			28
+#define R9A09G057_CR8_0_NWDRESET1			29
+#define R9A09G057_CR8_0_NWDRESET0			30
+#define R9A09G057_CR8_0_NDBGRESET1			31
+#define R9A09G057_CR8_0_NDBGRESET0			32
+#define R9A09G057_CR8_0_NCTRESET			33
+#define R9A09G057_CR8_0_NETM0RESET			34
+#define R9A09G057_CR8_0_NETM1RESET			35
+#define R9A09G057_CR8_0_NTSRESET			36
+#define R9A09G057_CR8_0_NMISCRESET			37
+#define R9A09G057_CM33_RESET0				38
+#define R9A09G057_CM33_RESET1				39
+#define R9A09G057_CM33_RESET2				40
+#define R9A09G057_GIC_0_GICRESET_N			41
+#define R9A09G057_GIC_0_DBG_GICRESET_N			42
+#define R9A09G057_SRAM_0_ARESETN			43
+#define R9A09G057_SRAM_1_ARESETN			44
+#define R9A09G057_SRAM_2_ARESETN			45
+#define R9A09G057_SRAM_3_ARESETN			46
+#define R9A09G057_SRAM_4_ARESETN			47
+#define R9A09G057_SRAM_5_ARESETN			48
+#define R9A09G057_SRAM_6_ARESETN			49
+#define R9A09G057_SRAM_7_ARESETN			50
+#define R9A09G057_SRAM_8_ARESETN			51
+#define R9A09G057_SRAM_9_ARESETN			52
+#define R9A09G057_SRAM_10_ARESETN			53
+#define R9A09G057_SRAM_11_ARESETN			54
+#define R9A09G057_BTROM_0_ARESETN			55
+#define R9A09G057_CST_0_CS_RESETN			56
+#define R9A09G057_CST_0_TS_RESETN			57
+#define R9A09G057_CST_0_APB_SB_RESETN			58
+#define R9A09G057_CST_0_APB_CA55_RESETN			59
+#define R9A09G057_CST_0_APB_CM33_RESETN			60
+#define R9A09G057_CST_0_APB_CR8_RESETN			61
+#define R9A09G057_CST_0_AHB_CM33_RESETN			62
+#define R9A09G057_CST_0_AHB_ATH_RESETN			63
+#define R9A09G057_CST_0_ATB_CA55_RESETN			64
+#define R9A09G057_CST_0_ATB_CM33_RESETN			65
+#define R9A09G057_CST_0_ATB_CR8_RESETN			66
+#define R9A09G057_CST_0_ATB_CST_RESETN			67
+#define R9A09G057_CST_0_AXI_SB_RESETN			68
+#define R9A09G057_CST_0_AXI_ETR_RESETN			69
+#define R9A09G057_CST_0_NTRST				70
+#define R9A09G057_CST_0_NPOTRST				71
+#define R9A09G057_SYC_0_RESETN				72
+#define R9A09G057_MHU_0_PRESETN				73
+#define R9A09G057_AXI_TZCDDR_0_PRESET0N			74
+#define R9A09G057_AXI_TZCDDR_0_PRESET1N			75
+#define R9A09G057_AXI_TZCDDR_0_ARESET0N			76
+#define R9A09G057_AXI_TZCDDR_0_ARESET1N			77
+#define R9A09G057_AXI_TZCDDR_0_ARESET2N			78
+#define R9A09G057_AXI_TZCDDR_0_ARESET3N			79
+#define R9A09G057_AXI_TZCDDR_0_ARESET4N			80
+#define R9A09G057_AXI_TZCDDR_1_PRESET0N			81
+#define R9A09G057_AXI_TZCDDR_1_PRESET1N			82
+#define R9A09G057_AXI_TZCDDR_1_ARESET0N			83
+#define R9A09G057_AXI_TZCDDR_1_ARESET1N			84
+#define R9A09G057_AXI_TZCDDR_1_ARESET2N			85
+#define R9A09G057_AXI_TZCDDR_1_ARESET3N			86
+#define R9A09G057_AXI_TZCDDR_1_ARESET4N			87
+#define R9A09G057_ACPU_AXI_RESETN			88
+#define R9A09G057_ACPU_PERI_DDR_AXI_RESETN		89
+#define R9A09G057_MCPU_AXI_RESETN			90
+#define R9A09G057_RCPU_AXI_RESETN			91
+#define R9A09G057_VIDEO0_AXI_RESETN			92
+#define R9A09G057_ACPU_PERI_VIDEO0_AXI_RESETN		93
+#define R9A09G057_VIDEO1_AXI_RESETN			94
+#define R9A09G057_ACPU_PERI_VIDEO1_AXI_RESETN		95
+#define R9A09G057_DRP_AXI_RESETN			96
+#define R9A09G057_ACPU_PERI_DRP0_AXI_RESETN		97
+#define R9A09G057_ACPU_PERI_DRP1_AXI_RESETN		98
+#define R9A09G057_COM_AXI_RESETN			99
+#define R9A09G057_ACPU_PERI_COM0_AXI_RESETN		100
+#define R9A09G057_ACPU_PERI_COM1_AXI_RESETN		101
+#define R9A09G057_GPT_0_RST_P_REG			102
+#define R9A09G057_GPT_0_RST_S_REG			103
+#define R9A09G057_GPT_1_RST_P_REG			104
+#define R9A09G057_GPT_1_RST_S_REG			105
+#define R9A09G057_POEGA_0_RST				106
+#define R9A09G057_POEGB_0_RST				107
+#define R9A09G057_POEGC_0_RST				108
+#define R9A09G057_POEGD_0_RST				109
+#define R9A09G057_POEGA_1_RST				110
+#define R9A09G057_POEGB_1_RST				111
+#define R9A09G057_POEGC_1_RST				112
+#define R9A09G057_POEGD_1_RST				113
+#define R9A09G057_CMTW_0_RST_M				114
+#define R9A09G057_CMTW_1_RST_M				115
+#define R9A09G057_CMTW_2_RST_M				116
+#define R9A09G057_CMTW_3_RST_M				117
+#define R9A09G057_CMTW_4_RST_M				118
+#define R9A09G057_CMTW_5_RST_M				119
+#define R9A09G057_CMTW_6_RST_M				120
+#define R9A09G057_CMTW_7_RST_M				121
+#define R9A09G057_GTM_0_PRESETZ				122
+#define R9A09G057_GTM_1_PRESETZ				123
+#define R9A09G057_GTM_2_PRESETZ				124
+#define R9A09G057_GTM_3_PRESETZ				125
+#define R9A09G057_GTM_4_PRESETZ				126
+#define R9A09G057_GTM_5_PRESETZ				127
+#define R9A09G057_GTM_6_PRESETZ				128
+#define R9A09G057_GTM_7_PRESETZ				129
+#define R9A09G057_WDT_0_RESET				130
+#define R9A09G057_WDT_1_RESET				131
+#define R9A09G057_WDT_2_RESET				132
+#define R9A09G057_WDT_3_RESET				133
+#define R9A09G057_RTC_0_RST_RTC				134
+#define R9A09G057_RTC_0_RST_RTC_V			135
+#define R9A09G057_RSPI_0_PRESETN			136
+#define R9A09G057_RSPI_0_TRESETN			137
+#define R9A09G057_RSPI_1_PRESETN			138
+#define R9A09G057_RSPI_1_TRESETN			139
+#define R9A09G057_RSPI_2_PRESETN			140
+#define R9A09G057_RSPI_2_TRESETN			141
+#define R9A09G057_RSCI_0_PRESETN			142
+#define R9A09G057_RSCI_0_TRESETN			143
+#define R9A09G057_RSCI_1_PRESETN			144
+#define R9A09G057_RSCI_1_TRESETN			145
+#define R9A09G057_RSCI_2_PRESETN			146
+#define R9A09G057_RSCI_2_TRESETN			147
+#define R9A09G057_RSCI_3_PRESETN			148
+#define R9A09G057_RSCI_3_TRESETN			149
+#define R9A09G057_RSCI_4_PRESETN			150
+#define R9A09G057_RSCI_4_TRESETN			151
+#define R9A09G057_RSCI_5_PRESETN			152
+#define R9A09G057_RSCI_5_TRESETN			153
+#define R9A09G057_RSCI_6_PRESETN			154
+#define R9A09G057_RSCI_6_TRESETN			155
+#define R9A09G057_RSCI_7_PRESETN			156
+#define R9A09G057_RSCI_7_TRESETN			157
+#define R9A09G057_RSCI_8_PRESETN			158
+#define R9A09G057_RSCI_8_TRESETN			159
+#define R9A09G057_RSCI_9_PRESETN			160
+#define R9A09G057_RSCI_9_TRESETN			161
+#define R9A09G057_SCIF_0_RST_SYSTEM_N			162
+#define R9A09G057_I3C_0_PRESETN				163
+#define R9A09G057_I3C_0_TRESETN				164
+#define R9A09G057_RIIC_8_MRST				165
+#define R9A09G057_RIIC_0_MRST				166
+#define R9A09G057_RIIC_1_MRST				167
+#define R9A09G057_RIIC_2_MRST				168
+#define R9A09G057_RIIC_3_MRST				169
+#define R9A09G057_RIIC_4_MRST				170
+#define R9A09G057_RIIC_5_MRST				171
+#define R9A09G057_RIIC_6_MRST				172
+#define R9A09G057_RIIC_7_MRST				173
+#define R9A09G057_CANFD_0_RSTP_N			174
+#define R9A09G057_CANFD_0_RSTC_N			175
+#define R9A09G057_SPI_HRESETN				176
+#define R9A09G057_SPI_ARESETN				177
+#define R9A09G057_IOTOP_0_RESETN			178
+#define R9A09G057_IOTOP_0_ERROR_RESETN			179
+#define R9A09G057_SDHI_0_IXRST				180
+#define R9A09G057_SDHI_1_IXRST				181
+#define R9A09G057_SDHI_2_IXRST				182
+#define R9A09G057_USB30_RST_RESERVED0			183
+#define R9A09G057_USB31_RST_RESERVED0			184
+#define R9A09G057_USB20_RST_RESERVED0			185
+#define R9A09G057_USB21_RST_RESERVED0			186
+#define R9A09G057_USB20_USB21_RST_RESERVED0		187
+#define R9A09G057_USB20_USB21_RST_RESERVED1		188
+#define R9A09G057_GBETH0_RST_RESERVED0			189
+#define R9A09G057_GBETH1_RST_RESERVED0			190
+#define R9A09G057_PCIE_0_ARESETN			191
+#define R9A09G057_DDR0_RST_RESERVED0			192
+#define R9A09G057_DDR0_RST_RESERVED1			193
+#define R9A09G057_DDR0_RST_RESERVED2			194
+#define R9A09G057_DDR0_RST_RESERVED3			195
+#define R9A09G057_DDR0_RST_RESERVED4			196
+#define R9A09G057_DDR0_RST_RESERVED5			197
+#define R9A09G057_DDR0_RST_RESERVED6			198
+#define R9A09G057_DDR0_RST_RESERVED7			199
+#define R9A09G057_DDR0_RST_RESERVED8			200
+#define R9A09G057_DDR0_RST_RESERVED9			201
+#define R9A09G057_DDR1_RST_RESERVED0			202
+#define R9A09G057_DDR1_RST_RESERVED1			203
+#define R9A09G057_DDR1_RST_RESERVED2			204
+#define R9A09G057_DDR1_RST_RESERVED3			205
+#define R9A09G057_DDR1_RST_RESERVED4			206
+#define R9A09G057_DDR1_RST_RESERVED5			207
+#define R9A09G057_DDR1_RST_RESERVED6			208
+#define R9A09G057_DDR1_RST_RESERVED7			209
+#define R9A09G057_DDR1_RST_RESERVED8			210
+#define R9A09G057_DDR1_RST_RESERVED9			211
+#define R9A09G057_CRU_0_PRESETN				212
+#define R9A09G057_CRU_0_ARESETN				213
+#define R9A09G057_CRU_0_S_RESETN			214
+#define R9A09G057_CRU_1_PRESETN				215
+#define R9A09G057_CRU_1_ARESETN				216
+#define R9A09G057_CRU_1_S_RESETN			217
+#define R9A09G057_CRU_2_PRESETN				218
+#define R9A09G057_CRU_2_ARESETN				219
+#define R9A09G057_CRU_2_S_RESETN			220
+#define R9A09G057_CRU_3_PRESETN				221
+#define R9A09G057_CRU_3_ARESETN				222
+#define R9A09G057_CRU_3_S_RESETN			223
+#define R9A09G057_ISP_RST_RESERVED0			224
+#define R9A09G057_ISP_RST_RESERVED1			225
+#define R9A09G057_ISP_RST_RESERVED2			226
+#define R9A09G057_ISP_RST_RESERVED3			227
+#define R9A09G057_ISU_0_ARESETN				228
+#define R9A09G057_ISU_0_PRESETN				229
+#define R9A09G057_DSI_0_PRESETN				230
+#define R9A09G057_DSI_0_ARESETN				231
+#define R9A09G057_LCDC_0_RESET_N			232
+#define R9A09G057_GPU_0_RESETN				233
+#define R9A09G057_GPU_0_AXI_RESETN			234
+#define R9A09G057_GPU_0_ACE_RESETN			235
+#define R9A09G057_VCD_0_RESETN				236
+#define R9A09G057_SSIF_0_ASYNC_RESET_SSI		237
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI0		238
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI1		239
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI2		240
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI3		241
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI4		242
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI5		243
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI6		244
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI7		245
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI8		246
+#define R9A09G057_SSIF_0_SYNC_RESET_SSI9		247
+#define R9A09G057_DMACPP_0_ARST				248
+#define R9A09G057_SCU_0_RESET_SRU			249
+#define R9A09G057_ADG_0_RST_RESET_ADG			250
+#define R9A09G057_SPDIF_0_RST				251
+#define R9A09G057_SPDIF_1_RST				252
+#define R9A09G057_SPDIF_2_RST				253
+#define R9A09G057_PDM_0_PRESETN				254
+#define R9A09G057_PDM_0_CRESETN				255
+#define R9A09G057_PDM_1_PRESETN				256
+#define R9A09G057_PDM_1_CRESETN				257
+#define R9A09G057_ADC_0_ADRST_N				258
+#define R9A09G057_TSU_0_PRESETN				259
+#define R9A09G057_TSU_1_PRESETN				260
+#define R9A09G057_OTPC_0_RESET_N			261
+#define R9A09G057_DRP_0_ARESETN				262
+#define R9A09G057_DRPAI_0_ARESETN			263
+
+#endif /* __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ */
-- 
2.34.1

Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Conor Dooley]

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On Fri, May 24, 2024 at 09:27:58AM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> Hardware User's Manual (Rev.1.01, Feb. 2024).
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Geert Uytterhoeven]

Hi Prabhakar,

On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> Hardware User's Manual (Rev.1.01, Feb. 2024).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a09g057-cpg.h
> @@ -0,0 +1,644 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* Clock list */

No distinction between Core and Module clocks?

> +#define R9A09G057_SYS_0_PCLK                           0
> +#define R9A09G057_DMAC_0_ACLK                          1
> +#define R9A09G057_DMAC_1_ACLK                          2
> +#define R9A09G057_DMAC_2_ACLK                          3

[...]

> +/* Resets list */

[...]

No power domain specifiers, as mentioned in PATCH 1/4?

> +
> +#endif /* __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ */

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Mon, May 27, 2024 at 10:18 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> > (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> > in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> > Hardware User's Manual (Rev.1.01, Feb. 2024).
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a09g057-cpg.h
> > @@ -0,0 +1,644 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2024 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* Clock list */
>
> No distinction between Core and Module clocks?
>
I was in two minds here. Would you prefer clocks with no CGC support
to be listed as core clocks?

> > +#define R9A09G057_SYS_0_PCLK                           0
> > +#define R9A09G057_DMAC_0_ACLK                          1
> > +#define R9A09G057_DMAC_1_ACLK                          2
> > +#define R9A09G057_DMAC_2_ACLK                          3
>
> [...]
>
> > +/* Resets list */
>
> [...]
>
> No power domain specifiers, as mentioned in PATCH 1/4?
>
OK, I'll add the power domains in this patch.

Cheers,
Prabhakar

Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Geert Uytterhoeven]

Hi Prabhakar,

On Wed, May 29, 2024 at 11:10 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, May 27, 2024 at 10:18 AM Geert Uytterhoeven
> <geert@linux-m68k.org> wrote:
> > On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> > > (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> > > in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> > > Hardware User's Manual (Rev.1.01, Feb. 2024).
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/r9a09g057-cpg.h
> > > @@ -0,0 +1,644 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > + *
> > > + * Copyright (C) 2024 Renesas Electronics Corp.
> > > + */
> > > +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > > +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > > +
> > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > +
> > > +/* Clock list */
> >
> > No distinction between Core and Module clocks?
> >
> I was in two minds here. Would you prefer clocks with no CGC support
> to be listed as core clocks?

What's CGC support? (Obviously I need some more reading before
I can tackle the rest of this series :-)

My comments are due to the bindings saying:

  '#clock-cells':
    description: |
      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
        and a core clock reference, as defined in
        <dt-bindings/clock/r9a09g057-cpg.h>,
      - For module clocks, the two clock specifier cells must be "CPG_MOD" and
        a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
    const: 2

while the header file does not make it obvious whether a clock needs
CPG_CORE or CPG_MOD.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Lad, Prabhakar]

Hi Geert,

On Thu, May 30, 2024 at 8:12 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Wed, May 29, 2024 at 11:10 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Mon, May 27, 2024 at 10:18 AM Geert Uytterhoeven
> > <geert@linux-m68k.org> wrote:
> > > On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> > > > (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> > > > in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> > > > Hardware User's Manual (Rev.1.01, Feb. 2024).
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > > --- /dev/null
> > > > +++ b/include/dt-bindings/clock/r9a09g057-cpg.h
> > > > @@ -0,0 +1,644 @@
> > > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > + *
> > > > + * Copyright (C) 2024 Renesas Electronics Corp.
> > > > + */
> > > > +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > > > +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > > > +
> > > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > > +
> > > > +/* Clock list */
> > >
> > > No distinction between Core and Module clocks?
> > >
> > I was in two minds here. Would you prefer clocks with no CGC support
> > to be listed as core clocks?
>
> What's CGC support? (Obviously I need some more reading before
> I can tackle the rest of this series :-)
>
I meant the clocks which cannot be controlled by the CPG_CLKON_m
register. Shall I add them as CORE clocks?

> My comments are due to the bindings saying:
>
>   '#clock-cells':
>     description: |
>       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
>         and a core clock reference, as defined in
>         <dt-bindings/clock/r9a09g057-cpg.h>,
>       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
>         a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
>     const: 2
>
> while the header file does not make it obvious whether a clock needs
> CPG_CORE or CPG_MOD.
>
I was intending to drop the CPG_CORE description in the next version.

Cheers,
Prabhakar

Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Geert Uytterhoeven]

Hi Prabhakar,

On Thu, May 30, 2024 at 12:00 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, May 30, 2024 at 8:12 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, May 29, 2024 at 11:10 PM Lad, Prabhakar
> > <prabhakar.csengg@gmail.com> wrote:
> > > On Mon, May 27, 2024 at 10:18 AM Geert Uytterhoeven
> > > <geert@linux-m68k.org> wrote:
> > > > On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> > > > > (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> > > > > in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> > > > > Hardware User's Manual (Rev.1.01, Feb. 2024).
> > > > >
> > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > > --- /dev/null
> > > > > +++ b/include/dt-bindings/clock/r9a09g057-cpg.h
> > > > > @@ -0,0 +1,644 @@
> > > > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > + *
> > > > > + * Copyright (C) 2024 Renesas Electronics Corp.
> > > > > + */
> > > > > +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > > > > +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > > > > +
> > > > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > > > +
> > > > > +/* Clock list */
> > > >
> > > > No distinction between Core and Module clocks?
> > > >
> > > I was in two minds here. Would you prefer clocks with no CGC support
> > > to be listed as core clocks?
> >
> > What's CGC support? (Obviously I need some more reading before
> > I can tackle the rest of this series :-)
> >
> I meant the clocks which cannot be controlled by the CPG_CLKON_m
> register. Shall I add them as CORE clocks?

If you don't need to refer to these clocks from DT, there is no need to add
them to the bindings header file.

> > My comments are due to the bindings saying:
> >
> >   '#clock-cells':
> >     description: |
> >       - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
> >         and a core clock reference, as defined in
> >         <dt-bindings/clock/r9a09g057-cpg.h>,
> >       - For module clocks, the two clock specifier cells must be "CPG_MOD" and
> >         a module number, as defined in <dt-bindings/clock/r9a09g057-cpg.h>.
> >     const: 2
> >
> > while the header file does not make it obvious whether a clock needs
> > CPG_CORE or CPG_MOD.
> >
> I was intending to drop the CPG_CORE description in the next version.

OK.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Geert Uytterhoeven]

Hi Prabhakar,

Thanks for your patch!

On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> Hardware User's Manual (Rev.1.01, Feb. 2024).

Hmm, I must have a slightly different Rev. 1.01 ;-)

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a09g057-cpg.h

For new binding headers, please include the vendor prefix, i.e.
"include/dt-bindings/clock/renesas,r9a09g057-cpg.h".

> @@ -0,0 +1,644 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2024 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* Clock list */

[...]

> +#define R9A09G057_USB30_CLK_RESERVED0                  197
> +#define R9A09G057_USB30_CLK_RESERVED1                  198
> +#define R9A09G057_USB30_CLK_RESERVED2                  199
> +#define R9A09G057_USB30_CLK_RESERVED3                  200

R9A09G057_USB3_0_ACLK
R9A09G057_USB3_0_PCLK_USBTST
R9A09G057_USB3_0_REF_ALT_CLK_p
R9A09G057_USB3_0_CLKCORE

> +#define R9A09G057_USB31_CLK_RESERVED0                  201
> +#define R9A09G057_USB31_CLK_RESERVED1                  202
> +#define R9A09G057_USB31_CLK_RESERVED2                  203
> +#define R9A09G057_USB31_CLK_RESERVED3                  204

R9A09G057_USB3_0_ACLK
R9A09G057_USB3_0_PCLK_USBTST
R9A09G057_USB3_0_REF_ALT_CLK_p
R9A09G057_USB3_0_CLKCORE

> +#define R9A09G057_USB20_CLK_RESERVED0                  205

R9A09G057_USB2_0_U2H0_HCLK

> +#define R9A09G057_USB21_CLK_RESERVED0                  206

R9A09G057_USB2_0_U2H1_HCLK

> +#define R9A09G057_USB20_USB21_CLK_RESERVED0            207

R9A09G057_USB2_0_U2P_EXR_CPUCLK

> +#define R9A09G057_USB20_CLK_RESERVED1                  208

R9A09G057_USB2_0_PCLK_USBTST0

> +#define R9A09G057_USB21_CLK_RESERVED1                  209

R9A09G057_USB2_0_PCLK_USBTST1

> +#define R9A09G057_USB20_CLK_RESERVED2                  210

R9A09G057_USB2_0_CLKCORE0

> +#define R9A09G057_USB21_CLK_RESERVED2                  211

R9A09G057_USB2_0_CLKCORE1

> +#define R9A09G057_GBETH0_CLK_RESERVED0                 212
> +#define R9A09G057_GBETH0_CLK_RESERVED1                 213
> +#define R9A09G057_GBETH0_CLK_RESERVED2                 214
> +#define R9A09G057_GBETH0_CLK_RESERVED3                 215
> +#define R9A09G057_GBETH0_CLK_RESERVED4                 216
> +#define R9A09G057_GBETH0_CLK_RESERVED5                 217
> +#define R9A09G057_GBETH0_CLK_RESERVED6                 218

R9A09G057_GBETH_0_CLK_TX_I
R9A09G057_GBETH_0_CLK_RX_I
R9A09G057_GBETH_0_CLK_TX_180_I
R9A09G057_GBETH_0_CLK_RX_180_I
R9A09G057_GBETH_0_CLK_PTP_REF_I
R9A09G057_GBETH_0_ACLK_CSR_I
R9A09G057_GBETH_0_ACLK_I

> +#define R9A09G057_GBETH1_CLK_RESERVED0                 219
> +#define R9A09G057_GBETH1_CLK_RESERVED1                 220
> +#define R9A09G057_GBETH1_CLK_RESERVED2                 221
> +#define R9A09G057_GBETH1_CLK_RESERVED3                 222
> +#define R9A09G057_GBETH1_CLK_RESERVED4                 223
> +#define R9A09G057_GBETH1_CLK_RESERVED5                 224
> +#define R9A09G057_GBETH1_CLK_RESERVED6                 225

R9A09G057_GBETH_1_CLK_TX_I
R9A09G057_GBETH_1_CLK_RX_I
R9A09G057_GBETH_1_CLK_TX_180_I
R9A09G057_GBETH_1_CLK_RX_180_I
R9A09G057_GBETH_1_CLK_PTP_REF_I
R9A09G057_GBETH_1_ACLK_CSR_I
R9A09G057_GBETH_1_ACLK_I

> +#define R9A09G057_PCIE_0_ACLK                          226
> +#define R9A09G057_PCIE_0_CLK_PMU                       227
> +#define R9A09G057_DDR0_CLK_RESERVED0                   228
> +#define R9A09G057_DDR0_CLK_RESERVED1                   229
> +#define R9A09G057_DDR0_CLK_RESERVED2                   230
> +#define R9A09G057_DDR0_CLK_RESERVED3                   231
> +#define R9A09G057_DDR0_CLK_RESERVED4                   232
> +#define R9A09G057_DDR0_CLK_RESERVED5                   233
> +#define R9A09G057_DDR0_CLK_RESERVED6                   234

R9A09G057_DDR_0_DFICLK
R9A09G057_DDR_0_AXI0_ACLK
R9A09G057_DDR_0_AXI1_ACLK
R9A09G057_DDR_0_AXI2_ACLK
R9A09G057_DDR_0_AXI3_ACLK
R9A09G057_DDR_0_AXI4_ACLK
R9A09G057_DDR_0_PCLK

> +#define R9A09G057_DDR1_CLK_RESERVED0                   235
> +#define R9A09G057_DDR1_CLK_RESERVED1                   236
> +#define R9A09G057_DDR1_CLK_RESERVED2                   237
> +#define R9A09G057_DDR1_CLK_RESERVED3                   238
> +#define R9A09G057_DDR1_CLK_RESERVED4                   239
> +#define R9A09G057_DDR1_CLK_RESERVED5                   240
> +#define R9A09G057_DDR1_CLK_RESERVED6                   241

R9A09G057_DDR_1_DFICLK
R9A09G057_DDR_1_AXI0_ACLK
R9A09G057_DDR_1_AXI1_ACLK
R9A09G057_DDR_1_AXI2_ACLK
R9A09G057_DDR_1_AXI3_ACLK
R9A09G057_DDR_1_AXI4_ACLK
R9A09G057_DDR_1_PCLK

> +#define R9A09G057_CRU_0_ACLK                           242
> +#define R9A09G057_CRU_0_VCLK                           243
> +#define R9A09G057_CRU_0_PCLK                           244
> +#define R9A09G057_CRU_1_ACLK                           245
> +#define R9A09G057_CRU_1_VCLK                           246
> +#define R9A09G057_CRU_1_PCLK                           247
> +#define R9A09G057_CRU_2_ACLK                           248
> +#define R9A09G057_CRU_2_VCLK                           249
> +#define R9A09G057_CRU_2_PCLK                           250
> +#define R9A09G057_CRU_3_ACLK                           251
> +#define R9A09G057_CRU_3_VCLK                           252
> +#define R9A09G057_CRU_3_PCLK                           253
> +#define R9A09G057_ISP_CLK_RESERVED0                    254
> +#define R9A09G057_ISP_CLK_RESERVED1                    255
> +#define R9A09G057_ISP_CLK_RESERVED2                    256
> +#define R9A09G057_ISP_CLK_RESERVED3                    257

R9A09G057_ISP_0_REG_ACLK
R9A09G057_ISP_0_PCLK
R9A09G057_ISP_0_VIN_ACLK
R9A09G057_ISP_0_ISP_SCLK

[...]

> +/* Resets list */

[...]

> +#define R9A09G057_USB30_RST_RESERVED0                  183

R9A09G057_USB3_0_ARESETN

> +#define R9A09G057_USB31_RST_RESERVED0                  184

R9A09G057_USB3_1_ARESETN

> +#define R9A09G057_USB20_RST_RESERVED0                  185

R9A09G057_USB2_0_U2H0_HRESETN

> +#define R9A09G057_USB21_RST_RESERVED0                  186

R9A09G057_USB2_0_U2H1_HRESETN

> +#define R9A09G057_USB20_USB21_RST_RESERVED0            187

R9A09G057_USB2_0_U2P_EXL_SYSRST

> +#define R9A09G057_USB20_USB21_RST_RESERVED1            188

R9A09G057_USB2_0_PRESETN

> +#define R9A09G057_GBETH0_RST_RESERVED0                 189

R9A09G057_GBETH_0_ARESETN_I

> +#define R9A09G057_GBETH1_RST_RESERVED0                 190

R9A09G057_GBETH_1_ARESETN_I

> +#define R9A09G057_PCIE_0_ARESETN                       191
> +#define R9A09G057_DDR0_RST_RESERVED0                   192
> +#define R9A09G057_DDR0_RST_RESERVED1                   193
> +#define R9A09G057_DDR0_RST_RESERVED2                   194
> +#define R9A09G057_DDR0_RST_RESERVED3                   195
> +#define R9A09G057_DDR0_RST_RESERVED4                   196
> +#define R9A09G057_DDR0_RST_RESERVED5                   197
> +#define R9A09G057_DDR0_RST_RESERVED6                   198
> +#define R9A09G057_DDR0_RST_RESERVED7                   199
> +#define R9A09G057_DDR0_RST_RESERVED8                   200
> +#define R9A09G057_DDR0_RST_RESERVED9                   201

R9A09G057_DDR_0_RST_N
R9A09G057_DDR_0_MC_PRESETN
R9A09G057_DDR_0_AXI0_ARESETN
R9A09G057_DDR_0_AXI1_ARESETN
R9A09G057_DDR_0_AXI2_ARESETN
R9A09G057_DDR_0_AXI3_ARESETN
R9A09G057_DDR_0_AXI4_ARESETN
R9A09G057_DDR_0_PHY_PRESETN
R9A09G057_DDR_0_RESET
R9A09G057_DDR_0_PWROKIN

> +#define R9A09G057_DDR1_RST_RESERVED0                   202
> +#define R9A09G057_DDR1_RST_RESERVED1                   203
> +#define R9A09G057_DDR1_RST_RESERVED2                   204
> +#define R9A09G057_DDR1_RST_RESERVED3                   205
> +#define R9A09G057_DDR1_RST_RESERVED4                   206
> +#define R9A09G057_DDR1_RST_RESERVED5                   207
> +#define R9A09G057_DDR1_RST_RESERVED6                   208
> +#define R9A09G057_DDR1_RST_RESERVED7                   209
> +#define R9A09G057_DDR1_RST_RESERVED8                   210
> +#define R9A09G057_DDR1_RST_RESERVED9                   211

R9A09G057_DDR_1_RST_N
R9A09G057_DDR_1_MC_PRESETN
R9A09G057_DDR_1_AXI0_ARESETN
R9A09G057_DDR_1_AXI1_ARESETN
R9A09G057_DDR_1_AXI2_ARESETN
R9A09G057_DDR_1_AXI3_ARESETN
R9A09G057_DDR_1_AXI4_ARESETN
R9A09G057_DDR_1_PHY_PRESETN
R9A09G057_DDR_1_RESET
R9A09G057_DDR_1_PWROKIN

> +#define R9A09G057_CRU_0_PRESETN                                212
> +#define R9A09G057_CRU_0_ARESETN                                213
> +#define R9A09G057_CRU_0_S_RESETN                       214
> +#define R9A09G057_CRU_1_PRESETN                                215
> +#define R9A09G057_CRU_1_ARESETN                                216
> +#define R9A09G057_CRU_1_S_RESETN                       217
> +#define R9A09G057_CRU_2_PRESETN                                218
> +#define R9A09G057_CRU_2_ARESETN                                219
> +#define R9A09G057_CRU_2_S_RESETN                       220
> +#define R9A09G057_CRU_3_PRESETN                                221
> +#define R9A09G057_CRU_3_ARESETN                                222
> +#define R9A09G057_CRU_3_S_RESETN                       223
> +#define R9A09G057_ISP_RST_RESERVED0                    224
> +#define R9A09G057_ISP_RST_RESERVED1                    225
> +#define R9A09G057_ISP_RST_RESERVED2                    226
> +#define R9A09G057_ISP_RST_RESERVED3                    227

R9A09G057_ISP_0_VIN_ARESETN
R9A09G057_ISP_0_REG_ARESETN
R9A09G057_ISP_0_ISP_SRESETN
R9A09G057_ISP_0_PRESETN

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Geert Uytterhoeven]

Hi Prabhakar,

CC Greg

On Tue, Jun 4, 2024 at 5:46 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> > (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> > in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> > Hardware User's Manual (Rev.1.01, Feb. 2024).
>
> Hmm, I must have a slightly different Rev. 1.01 ;-)
>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a09g057-cpg.h

> > +/* Clock list */
>
> [...]
>
> > +#define R9A09G057_USB30_CLK_RESERVED0                  197
> > +#define R9A09G057_USB30_CLK_RESERVED1                  198
> > +#define R9A09G057_USB30_CLK_RESERVED2                  199
> > +#define R9A09G057_USB30_CLK_RESERVED3                  200

[...]

It has been brought to my attention these had been named *RESERVED*
deliberately, to avoid disclosing their meaning.
As these definitions are part of the DT ABI, and the DTS writer has to
relate the names to the actual clocks in the datasheet, and to the names
used in the DT bindings for the consumer devices (if ever upstreamed),
I find it hard to accept these for upstream inclusion as-is.

What do other people think?
Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/4] dt-bindings: clock: Add R9A09G057 CPG Clock and Reset Definitions

[Lad, Prabhakar]

Hi Geert,

On Wed, Jun 5, 2024 at 9:29 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> CC Greg
>
> On Tue, Jun 4, 2024 at 5:46 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> > > (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> > > in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> > > Hardware User's Manual (Rev.1.01, Feb. 2024).
> >
> > Hmm, I must have a slightly different Rev. 1.01 ;-)
> >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/r9a09g057-cpg.h
>
> > > +/* Clock list */
> >
> > [...]
> >
> > > +#define R9A09G057_USB30_CLK_RESERVED0                  197
> > > +#define R9A09G057_USB30_CLK_RESERVED1                  198
> > > +#define R9A09G057_USB30_CLK_RESERVED2                  199
> > > +#define R9A09G057_USB30_CLK_RESERVED3                  200
>
> [...]
>
> It has been brought to my attention these had been named *RESERVED*
> deliberately, to avoid disclosing their meaning.
> As these definitions are part of the DT ABI, and the DTS writer has to
> relate the names to the actual clocks in the datasheet, and to the names
> used in the DT bindings for the consumer devices (if ever upstreamed),
> I find it hard to accept these for upstream inclusion as-is.
>
The other point I want to add is that the macros, which are designated
as reserved, have been included to prevent any breakage of ABI. In the
future, if we plan to add support for these IP blocks, these macros
will be renamed accordingly and utilized in the CPG driver.

Cheers,
Prabhakar

> What do other people think?
> Thanks!
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

[PATCH 3/4] clk: renesas: Add RZ/V2H CPG core wrapper driver

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add CPG core helper wrapper driver for RZ/V2H SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/Kconfig     |   5 +
 drivers/clk/renesas/Makefile    |   1 +
 drivers/clk/renesas/rzv2h-cpg.c | 673 ++++++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h | 149 +++++++
 4 files changed, 828 insertions(+)
 create mode 100644 drivers/clk/renesas/rzv2h-cpg.c
 create mode 100644 drivers/clk/renesas/rzv2h-cpg.h

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index d252150402e8..254203c2cb2e 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -40,6 +40,7 @@ config CLK_RENESAS
 	select CLK_R9A07G054 if ARCH_R9A07G054
 	select CLK_R9A08G045 if ARCH_R9A08G045
 	select CLK_R9A09G011 if ARCH_R9A09G011
+	select CLK_R9A09G057 if ARCH_R9A09G057
 	select CLK_SH73A0 if ARCH_SH73A0
 
 if CLK_RENESAS
@@ -193,6 +194,10 @@ config CLK_R9A09G011
 	bool "RZ/V2M clock support" if COMPILE_TEST
 	select CLK_RZG2L
 
+config CLK_R9A09G057
+	bool "Renesas RZ/V2H(P) clock support" if COMPILE_TEST
+	select RESET_CONTROLLER
+
 config CLK_SH73A0
 	bool "SH-Mobile AG5 clock support" if COMPILE_TEST
 	select CLK_RENESAS_CPG_MSTP
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index f7e18679c3b8..79cc7c4d77c6 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o
 obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o
+obj-$(CONFIG_CLK_R9A09G057)		+= rzv2h-cpg.o
 obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
 
 # Family
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
new file mode 100644
index 000000000000..eb6b7ab86675
--- /dev/null
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/V2H(P) Clock Pulse Generator
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ *
+ * Based on rzg2l-cpg.c
+ *
+ * Copyright (C) 2015 Glider bvba
+ * Copyright (C) 2013 Ideas On Board SPRL
+ * Copyright (C) 2015 Renesas Electronics Corp.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/iopoll.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/reset-controller.h>
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+#include "rzv2h-cpg.h"
+
+#ifdef DEBUG
+#define WARN_DEBUG(x)		WARN_ON(x)
+#else
+#define WARN_DEBUG(x)		do { } while (0)
+#endif
+
+#define KDIV(val)			((s16)FIELD_GET(GENMASK(31, 16), (val)))
+#define MDIV(val)			FIELD_GET(GENMASK(15, 6), (val))
+#define PDIV(val)			FIELD_GET(GENMASK(5, 0), (val))
+#define SDIV(val)			FIELD_GET(GENMASK(2, 0), (val))
+
+/**
+ * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
+ *
+ * @rcdev: Reset controller entity
+ * @dev: CPG device
+ * @base: CPG register block base address
+ * @rmw_lock: protects register accesses
+ * @clks: Array containing all Core and Module Clocks
+ * @num_core_clks: Number of Core Clocks in clks[]
+ * @num_mod_clks: Number of Module Clocks in clks[]
+ * @num_resets: Number of Module Resets in info->resets[]
+ * @info: Pointer to platform data
+ */
+struct rzv2h_cpg_priv {
+	struct reset_controller_dev rcdev;
+	struct device *dev;
+	void __iomem *base;
+	spinlock_t rmw_lock;
+
+	struct clk **clks;
+	unsigned int num_core_clks;
+	unsigned int num_mod_clks;
+	unsigned int num_resets;
+
+	const struct rzv2h_cpg_info *info;
+};
+
+struct pll_clk {
+	struct clk_hw hw;
+	unsigned int conf;
+	unsigned int type;
+	void __iomem *base;
+	struct rzv2h_cpg_priv *priv;
+};
+
+#define to_pll(_hw)	container_of(_hw, struct pll_clk, hw)
+
+static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
+						   unsigned long parent_rate)
+{
+	struct pll_clk *pll_clk = to_pll(hw);
+	struct rzv2h_cpg_priv *priv = pll_clk->priv;
+	const struct rzv2h_cpg_info *info = priv->info;
+	int clk1_off, clk2_off;
+	unsigned int clk1, clk2;
+	u64 rate;
+
+	clk1_off = info->pll_get_clk1_offset(pll_clk->conf);
+	clk2_off = info->pll_get_clk2_offset(pll_clk->conf);
+	if (clk1_off == -EINVAL || clk2_off == -EINVAL)
+		return 0;
+
+	clk1 = readl(priv->base + clk1_off);
+	clk2 = readl(priv->base + clk2_off);
+
+	rate = mul_u64_u32_shr(parent_rate, (MDIV(clk1) << 16) + KDIV(clk1),
+			       16 + SDIV(clk2));
+
+	return DIV_ROUND_CLOSEST_ULL(rate, PDIV(clk1));
+}
+
+static const struct clk_ops rzv2h_cpg_pll_ops = {
+	.recalc_rate = rzv2h_cpg_pll_clk_recalc_rate,
+};
+
+static struct clk * __init
+rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core,
+			   struct clk **clks,
+			   void __iomem *base,
+			   struct rzv2h_cpg_priv *priv,
+			   const struct clk_ops *ops)
+{
+	struct device *dev = priv->dev;
+	struct clk_init_data init;
+	const struct clk *parent;
+	const char *parent_name;
+	struct pll_clk *pll_clk;
+
+	parent = clks[core->parent & 0xffff];
+	if (IS_ERR(parent))
+		return ERR_CAST(parent);
+
+	pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
+	if (!pll_clk)
+		return ERR_PTR(-ENOMEM);
+
+	parent_name = __clk_get_name(parent);
+	init.name = core->name;
+	init.ops = ops;
+	init.flags = 0;
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	pll_clk->hw.init = &init;
+	pll_clk->conf = core->conf;
+	pll_clk->base = base;
+	pll_clk->priv = priv;
+	pll_clk->type = core->type;
+
+	return clk_register(NULL, &pll_clk->hw);
+}
+
+static struct clk
+*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
+			       void *data)
+{
+	unsigned int clkidx = clkspec->args[1];
+	struct rzv2h_cpg_priv *priv = data;
+	struct device *dev = priv->dev;
+	const char *type;
+	struct clk *clk;
+
+	switch (clkspec->args[0]) {
+	case CPG_CORE:
+		type = "core";
+		clk = priv->clks[clkidx];
+		break;
+
+	case CPG_MOD:
+		type = "module";
+		if (clkidx >= priv->num_mod_clks) {
+			dev_err(dev, "Invalid %s clock index %u\n", type,
+				clkidx);
+			return ERR_PTR(-EINVAL);
+		}
+		clk = priv->clks[priv->num_core_clks + clkidx];
+		break;
+
+	default:
+		dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (IS_ERR(clk))
+		dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
+			PTR_ERR(clk));
+	else
+		dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
+			clkspec->args[0], clkspec->args[1], clk,
+			clk_get_rate(clk));
+	return clk;
+}
+
+static void __init
+rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
+			    const struct rzv2h_cpg_info *info,
+			    struct rzv2h_cpg_priv *priv)
+{
+	struct clk *clk = ERR_PTR(-EOPNOTSUPP), *parent;
+	struct device *dev = priv->dev;
+	unsigned int id = core->id, div = core->div;
+	const char *parent_name;
+
+	WARN_DEBUG(id >= priv->num_core_clks);
+	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
+
+	if (!core->name) {
+		/* Skip NULLified clock */
+		return;
+	}
+
+	switch (core->type) {
+	case CLK_TYPE_IN:
+		clk = of_clk_get_by_name(priv->dev->of_node, core->name);
+		break;
+	case CLK_TYPE_FF:
+		WARN_DEBUG(core->parent >= priv->num_core_clks);
+		parent = priv->clks[core->parent];
+		if (IS_ERR(parent)) {
+			clk = parent;
+			goto fail;
+		}
+
+		parent_name = __clk_get_name(parent);
+		clk = clk_register_fixed_factor(NULL, core->name,
+						parent_name, CLK_SET_RATE_PARENT,
+						core->mult, div);
+		break;
+	case CLK_TYPE_PLL:
+		clk = rzv2h_cpg_pll_clk_register(core, priv->clks, priv->base, priv,
+						 &rzv2h_cpg_pll_ops);
+		break;
+	default:
+		goto fail;
+	}
+
+	if (IS_ERR_OR_NULL(clk))
+		goto fail;
+
+	dev_dbg(dev, "Core clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
+	priv->clks[id] = clk;
+	return;
+
+fail:
+	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",
+		core->name, PTR_ERR(clk));
+}
+
+/**
+ * struct mstp_clock - MSTP gating clock
+ *
+ * @hw: handle between common and hardware-specific interfaces
+ * @off: register offset
+ * @bit: ON/MON bit
+ * @monoff: monitor register offset
+ * @monbit: montor bit
+ * @priv: CPG/MSTP private data
+ */
+struct mstp_clock {
+	struct clk_hw hw;
+	u16 off;
+	u8 bit;
+	u16 monoff;
+	u8 monbit;
+	struct rzv2h_cpg_priv *priv;
+};
+
+#define to_mod_clock(_hw) container_of(_hw, struct mstp_clock, hw)
+
+static int rzv2h_mod_clock_endisable(struct clk_hw *hw, bool enable)
+{
+	struct mstp_clock *clock = to_mod_clock(hw);
+	struct rzv2h_cpg_priv *priv = clock->priv;
+	unsigned int reg = clock->off;
+	struct device *dev = priv->dev;
+	u32 bitmask = BIT(clock->bit);
+	u32 value;
+	int error;
+
+	dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", reg, hw->clk,
+		enable ? "ON" : "OFF");
+
+	value = bitmask << 16;
+	if (enable)
+		value |= bitmask;
+
+	writel(value, priv->base + reg);
+
+	if (!enable)
+		return 0;
+
+	reg = clock->monoff;
+	bitmask = BIT(clock->monbit);
+	error = readl_poll_timeout_atomic(priv->base + reg, value,
+					  value & bitmask, 0, 10);
+	if (error)
+		dev_err(dev, "Failed to enable CLK_ON %p\n",
+			priv->base + reg);
+
+	return error;
+}
+
+static int rzv2h_mod_clock_enable(struct clk_hw *hw)
+{
+	return rzv2h_mod_clock_endisable(hw, true);
+}
+
+static void rzv2h_mod_clock_disable(struct clk_hw *hw)
+{
+	rzv2h_mod_clock_endisable(hw, false);
+}
+
+static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw)
+{
+	struct mstp_clock *clock = to_mod_clock(hw);
+	struct rzv2h_cpg_priv *priv = clock->priv;
+	u32 bitmask = BIT(clock->monbit);
+
+	return readl(priv->base + clock->monoff) & bitmask;
+}
+
+static const struct clk_ops rzv2h_mod_clock_ops = {
+	.enable = rzv2h_mod_clock_enable,
+	.disable = rzv2h_mod_clock_disable,
+	.is_enabled = rzv2h_mod_clock_is_enabled,
+};
+
+static void __init
+rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
+			   const struct rzv2h_cpg_info *info,
+			   struct rzv2h_cpg_priv *priv)
+{
+	struct mstp_clock *clock = NULL;
+	struct device *dev = priv->dev;
+	unsigned int id = mod->id;
+	struct clk_init_data init;
+	struct clk *parent, *clk;
+	const char *parent_name;
+	unsigned int i;
+
+	WARN_DEBUG(id < priv->num_core_clks);
+	WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
+	WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
+	WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
+
+	if (!mod->name) {
+		/* Skip NULLified clock */
+		return;
+	}
+
+	parent = priv->clks[mod->parent];
+	if (IS_ERR(parent)) {
+		clk = parent;
+		goto fail;
+	}
+
+	clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
+	if (!clock) {
+		clk = ERR_PTR(-ENOMEM);
+		goto fail;
+	}
+
+	init.name = mod->name;
+	init.ops = &rzv2h_mod_clock_ops;
+	init.flags = CLK_SET_RATE_PARENT;
+	for (i = 0; i < info->num_crit_mod_clks; i++)
+		if (id == info->crit_mod_clks[i]) {
+			dev_dbg(dev, "CPG %s setting CLK_IS_CRITICAL\n",
+				mod->name);
+			init.flags |= CLK_IS_CRITICAL;
+			break;
+		}
+
+	parent_name = __clk_get_name(parent);
+	init.parent_names = &parent_name;
+	init.num_parents = 1;
+
+	clock->off = mod->off;
+	clock->bit = mod->bit;
+	clock->monoff = mod->monoff;
+	clock->monbit = mod->monbit;
+	clock->priv = priv;
+	clock->hw.init = &init;
+
+	clk = clk_register(NULL, &clock->hw);
+	if (IS_ERR(clk))
+		goto fail;
+
+	dev_dbg(dev, "Module clock %pC at %lu Hz\n", clk, clk_get_rate(clk));
+	priv->clks[id] = clk;
+
+	return;
+
+fail:
+	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",
+		mod->name, PTR_ERR(clk));
+}
+
+#define rcdev_to_priv(x)	container_of(x, struct rzv2h_cpg_priv, rcdev)
+
+static int rzv2h_cpg_assert(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
+	const struct rzv2h_cpg_info *info = priv->info;
+	unsigned int reg = info->resets[id].resoff;
+	u32 mask = BIT(info->resets[id].resbit);
+	s8 monbit = info->resets[id].monbit;
+	u32 value = mask << 16;
+
+	dev_dbg(rcdev->dev, "assert id:%ld offset:0x%x\n", id, reg);
+
+	writel(value, priv->base + reg);
+
+	reg = info->resets[id].monoff;
+	mask = BIT(monbit);
+
+	return readl_poll_timeout_atomic(priv->base + reg, value,
+					 value & mask, 10, 200);
+}
+
+static int rzv2h_cpg_deassert(struct reset_controller_dev *rcdev,
+			      unsigned long id)
+{
+	struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
+	const struct rzv2h_cpg_info *info = priv->info;
+	unsigned int reg = info->resets[id].resoff;
+	u32 mask = BIT(info->resets[id].resbit);
+	s8 monbit = info->resets[id].monbit;
+	u32 value = (mask << 16) | mask;
+
+	dev_dbg(rcdev->dev, "deassert id:%ld offset:0x%x\n", id, reg);
+
+	writel(value, priv->base + reg);
+
+	reg = info->resets[id].monoff;
+	mask = BIT(monbit);
+
+	return readl_poll_timeout_atomic(priv->base + reg, value,
+					 !(value & mask), 10, 200);
+}
+
+static int rzv2h_cpg_reset(struct reset_controller_dev *rcdev,
+			   unsigned long id)
+{
+	int ret;
+
+	ret = rzv2h_cpg_assert(rcdev, id);
+	if (ret)
+		return ret;
+
+	return rzv2h_cpg_deassert(rcdev, id);
+}
+
+static int rzv2h_cpg_status(struct reset_controller_dev *rcdev,
+			    unsigned long id)
+{
+	struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
+	const struct rzv2h_cpg_info *info = priv->info;
+	unsigned int reg = info->resets[id].monoff;
+	s8 monbit = info->resets[id].monbit;
+	u32 bitmask = BIT(monbit);
+
+	return !!(readl(priv->base + reg) & bitmask);
+}
+
+static const struct reset_control_ops rzv2h_cpg_reset_ops = {
+	.reset = rzv2h_cpg_reset,
+	.assert = rzv2h_cpg_assert,
+	.deassert = rzv2h_cpg_deassert,
+	.status = rzv2h_cpg_status,
+};
+
+static int rzv2h_cpg_reset_xlate(struct reset_controller_dev *rcdev,
+				 const struct of_phandle_args *reset_spec)
+{
+	struct rzv2h_cpg_priv *priv = rcdev_to_priv(rcdev);
+	const struct rzv2h_cpg_info *info = priv->info;
+	unsigned int id = reset_spec->args[0];
+
+	if (id >= rcdev->nr_resets || !info->resets[id].resoff) {
+		dev_err(rcdev->dev, "Invalid reset index %u\n", id);
+		return -EINVAL;
+	}
+
+	return id;
+}
+
+static int rzv2h_cpg_reset_controller_register(struct rzv2h_cpg_priv *priv)
+{
+	priv->rcdev.ops = &rzv2h_cpg_reset_ops;
+	priv->rcdev.of_node = priv->dev->of_node;
+	priv->rcdev.dev = priv->dev;
+	priv->rcdev.of_reset_n_cells = 1;
+	priv->rcdev.of_xlate = rzv2h_cpg_reset_xlate;
+	priv->rcdev.nr_resets = priv->num_resets;
+
+	return devm_reset_controller_register(priv->dev, &priv->rcdev);
+}
+
+/**
+ * struct rzv2h_cpg_pd - RZ/V2H power domain data structure
+ * @genpd: generic PM domain
+ * @priv: pointer to CPG private data structure
+ */
+struct rzv2h_cpg_pd {
+	struct generic_pm_domain genpd;
+	struct rzv2h_cpg_priv *priv;
+};
+
+static int rzv2h_cpg_attach_dev(struct generic_pm_domain *domain, struct device *dev)
+{
+	struct device_node *np = dev->of_node;
+	struct of_phandle_args clkspec;
+	bool once = true;
+	struct clk *clk;
+	int error;
+	int i = 0;
+
+	while (!of_parse_phandle_with_args(np, "clocks", "#clock-cells", i,
+					   &clkspec)) {
+		if (once) {
+			once = false;
+			error = pm_clk_create(dev);
+			if (error) {
+				of_node_put(clkspec.np);
+				goto err;
+			}
+		}
+		clk = of_clk_get_from_provider(&clkspec);
+		of_node_put(clkspec.np);
+		if (IS_ERR(clk)) {
+			error = PTR_ERR(clk);
+			goto fail_destroy;
+		}
+
+		error = pm_clk_add_clk(dev, clk);
+		if (error) {
+			dev_err(dev, "pm_clk_add_clk failed %d\n",
+				error);
+			goto fail_put;
+		}
+		i++;
+	}
+
+	return 0;
+
+fail_put:
+	clk_put(clk);
+
+fail_destroy:
+	pm_clk_destroy(dev);
+err:
+	return error;
+}
+
+static void rzv2h_cpg_detach_dev(struct generic_pm_domain *unused, struct device *dev)
+{
+	if (!pm_clk_no_clocks(dev))
+		pm_clk_destroy(dev);
+}
+
+static void rzv2h_cpg_genpd_remove_simple(void *data)
+{
+	pm_genpd_remove(data);
+}
+
+static int __init rzv2h_cpg_add_pm_domains(struct rzv2h_cpg_priv *priv)
+{
+	struct device *dev = priv->dev;
+	struct device_node *np = dev->of_node;
+	struct rzv2h_cpg_pd *pd;
+	int ret;
+
+	pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+	if (!pd)
+		return -ENOMEM;
+
+	pd->genpd.name = np->name;
+	pd->priv = priv;
+	pd->genpd.flags |= GENPD_FLAG_ALWAYS_ON | GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
+	pd->genpd.attach_dev = rzv2h_cpg_attach_dev;
+	pd->genpd.detach_dev = rzv2h_cpg_detach_dev;
+	ret = pm_genpd_init(&pd->genpd, &pm_domain_always_on_gov, false);
+	if (ret)
+		return ret;
+
+	ret = devm_add_action_or_reset(dev, rzv2h_cpg_genpd_remove_simple, &pd->genpd);
+	if (ret)
+		return ret;
+
+	return of_genpd_add_provider_simple(np, &pd->genpd);
+}
+
+static void rzv2h_cpg_del_clk_provider(void *data)
+{
+	of_clk_del_provider(data);
+}
+
+static int __init rzv2h_cpg_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
+	const struct rzv2h_cpg_info *info;
+	struct rzv2h_cpg_priv *priv;
+	unsigned int nclks, i;
+	struct clk **clks;
+	int error;
+
+	info = of_device_get_match_data(dev);
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+	priv->info = info;
+	spin_lock_init(&priv->rmw_lock);
+
+	priv->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(priv->base))
+		return PTR_ERR(priv->base);
+
+	nclks = info->num_total_core_clks + info->num_hw_mod_clks;
+	clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
+	if (!clks)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, priv);
+	priv->clks = clks;
+	priv->num_core_clks = info->num_total_core_clks;
+	priv->num_mod_clks = info->num_hw_mod_clks;
+	priv->num_resets = info->num_resets;
+
+	for (i = 0; i < nclks; i++)
+		clks[i] = ERR_PTR(-ENOENT);
+
+	for (i = 0; i < info->num_core_clks; i++)
+		rzv2h_cpg_register_core_clk(&info->core_clks[i], info, priv);
+
+	for (i = 0; i < info->num_mod_clks; i++)
+		rzv2h_cpg_register_mod_clk(&info->mod_clks[i], info, priv);
+
+	error = of_clk_add_provider(np, rzv2h_cpg_clk_src_twocell_get, priv);
+	if (error)
+		return error;
+
+	error = devm_add_action_or_reset(dev, rzv2h_cpg_del_clk_provider, np);
+	if (error)
+		return error;
+
+	error = rzv2h_cpg_add_pm_domains(priv);
+	if (error)
+		return error;
+
+	error = rzv2h_cpg_reset_controller_register(priv);
+	if (error)
+		return error;
+
+	return 0;
+}
+
+static const struct of_device_id rzv2h_cpg_match[] = {
+	{ /* sentinel */ }
+};
+
+static struct platform_driver rzv2h_cpg_driver = {
+	.driver		= {
+		.name	= "rzv2h-cpg",
+		.of_match_table = rzv2h_cpg_match,
+	},
+};
+
+static int __init rzv2h_cpg_init(void)
+{
+	return platform_driver_probe(&rzv2h_cpg_driver, rzv2h_cpg_probe);
+}
+
+subsys_initcall(rzv2h_cpg_init);
+
+MODULE_DESCRIPTION("Renesas RZ/V2H CPG Driver");
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
new file mode 100644
index 000000000000..689c123d01c5
--- /dev/null
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Renesas RZ/V2H(P) Clock Pulse Generator
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#ifndef __RENESAS_RZV2H_CPG_H__
+#define __RENESAS_RZV2H_CPG_H__
+
+/**
+ * Definitions of CPG Core Clocks
+ *
+ * These include:
+ *   - Clock outputs exported to DT
+ *   - External input clocks
+ *   - Internal CPG clocks
+ */
+struct cpg_core_clk {
+	const char *name;
+	unsigned int id;
+	unsigned int parent;
+	unsigned int div;
+	unsigned int mult;
+	unsigned int type;
+	unsigned int conf;
+};
+
+enum clk_types {
+	/* Generic */
+	CLK_TYPE_IN,		/* External Clock Input */
+	CLK_TYPE_FF,		/* Fixed Factor Clock */
+	CLK_TYPE_PLL,
+};
+
+#define DEF_TYPE(_name, _id, _type...) \
+	{ .name = _name, .id = _id, .type = _type }
+#define DEF_BASE(_name, _id, _type, _parent...) \
+	DEF_TYPE(_name, _id, _type, .parent = _parent)
+#define DEF_PLL(_name, _id, _parent, _conf) \
+	DEF_TYPE(_name, _id, CLK_TYPE_PLL, .parent = _parent, .conf = _conf)
+#define DEF_INPUT(_name, _id) \
+	DEF_TYPE(_name, _id, CLK_TYPE_IN)
+#define DEF_FIXED(_name, _id, _parent, _mult, _div) \
+	DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
+
+/**
+ * struct rzv2h_mod_clk - Module Clocks definitions
+ *
+ * @name: handle between common and hardware-specific interfaces
+ * @id: clock index in array containing all Core and Module Clocks
+ * @parent: id of parent clock
+ * @off: register offset
+ * @bit: ON/MON bit
+ * @monoff: monitor register offset
+ * @monbit: monitor bit
+ */
+struct rzv2h_mod_clk {
+	const char *name;
+	unsigned int id;
+	unsigned int parent;
+	u16 off;
+	u8 bit;
+	u16 monoff;
+	u8 monbit;
+};
+
+#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _monoff, _monbit)	\
+	{ \
+		.name = _name, \
+		.id = MOD_CLK_BASE + (_id), \
+		.parent = (_parent), \
+		.off = (_off), \
+		.bit = (_bit), \
+		.monoff = (_monoff), \
+		.monbit = (_monbit), \
+	}
+
+#define DEF_MOD(_name, _id, _parent, _off, _bit, _monoff, _monbit)	\
+	DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _monoff, _monbit)
+
+/**
+ * struct rzv2h_reset - Reset definitions
+ *
+ * @off: reset register offset
+ * @bit: reset bit
+ * @monoff: monitor register offset
+ * @monbit: monitor bit
+ */
+struct rzv2h_reset {
+	u16 resoff;
+	u8 resbit;
+	u16 monoff;
+	u8 monbit;
+};
+
+#define DEF_RST(_id, _resoff, _resbit, _monoff, _monbit)	\
+	[_id] = { \
+		.resoff = (_resoff), \
+		.resbit = (_resbit), \
+		.monoff = (_monoff), \
+		.monbit = (_monbit) \
+	}
+
+/**
+ * struct rzv2h_cpg_info - SoC-specific CPG Description
+ *
+ * @core_clks: Array of Core Clock definitions
+ * @num_core_clks: Number of entries in core_clks[]
+ * @num_total_core_clks: Total number of Core Clocks (exported + internal)
+ *
+ * @mod_clks: Array of Module Clock definitions
+ * @num_mod_clks: Number of entries in mod_clks[]
+ * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
+ *
+ * @resets: Array of Module Reset definitions
+ * @num_resets: Number of entries in resets[]
+ *
+ * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
+ *                 should not be disabled without a knowledgeable driver
+ * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
+ * @pll_get_clk1_offset: Function pointer to get PLL CLK1 offset
+ * @pll_get_clk2_offset: Function pointer to get PLL CLK2 offset
+ */
+struct rzv2h_cpg_info {
+	/* Core Clocks */
+	const struct cpg_core_clk *core_clks;
+	unsigned int num_core_clks;
+	unsigned int num_total_core_clks;
+
+	/* Module Clocks */
+	const struct rzv2h_mod_clk *mod_clks;
+	unsigned int num_mod_clks;
+	unsigned int num_hw_mod_clks;
+
+	/* Resets */
+	const struct rzv2h_reset *resets;
+	unsigned int num_resets;
+
+	/* Critical Module Clocks that should not be disabled */
+	const unsigned int *crit_mod_clks;
+	unsigned int num_crit_mod_clks;
+
+	/* function pointers for PLL information */
+	int (*pll_get_clk1_offset)(int clk);
+	int (*pll_get_clk2_offset)(int clk);
+};
+
+#endif	/* __RENESAS_RZV2H_CPG_H__ */
-- 
2.34.1

Re: [PATCH 3/4] clk: renesas: Add RZ/V2H CPG core wrapper driver

[Geert Uytterhoeven]

Hi Prabhakar,

Thanks for your patch!

On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add CPG core helper wrapper driver for RZ/V2H SoC.

What is a "core helper wrapper"? ;-)

Looking at the structure, this looks like a family-specific clock driver?
Will there be more RZ/V2H-alike SoCs?

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  drivers/clk/renesas/Kconfig     |   5 +
>  drivers/clk/renesas/Makefile    |   1 +
>  drivers/clk/renesas/rzv2h-cpg.c | 673 ++++++++++++++++++++++++++++++++
>  drivers/clk/renesas/rzv2h-cpg.h | 149 +++++++
>  4 files changed, 828 insertions(+)
>  create mode 100644 drivers/clk/renesas/rzv2h-cpg.c
>  create mode 100644 drivers/clk/renesas/rzv2h-cpg.h
>
> diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
> index d252150402e8..254203c2cb2e 100644
> --- a/drivers/clk/renesas/Kconfig
> +++ b/drivers/clk/renesas/Kconfig
> @@ -40,6 +40,7 @@ config CLK_RENESAS
>         select CLK_R9A07G054 if ARCH_R9A07G054
>         select CLK_R9A08G045 if ARCH_R9A08G045
>         select CLK_R9A09G011 if ARCH_R9A09G011
> +       select CLK_R9A09G057 if ARCH_R9A09G057
>         select CLK_SH73A0 if ARCH_SH73A0
>
>  if CLK_RENESAS
> @@ -193,6 +194,10 @@ config CLK_R9A09G011
>         bool "RZ/V2M clock support" if COMPILE_TEST
>         select CLK_RZG2L
>
> +config CLK_R9A09G057
> +       bool "Renesas RZ/V2H(P) clock support" if COMPILE_TEST

Please drop "Renesas "
(few other symbols have it, I'll fix the remaining).

> +       select RESET_CONTROLLER
> +
>  config CLK_SH73A0
>         bool "SH-Mobile AG5 clock support" if COMPILE_TEST
>         select CLK_RENESAS_CPG_MSTP
> diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
> index f7e18679c3b8..79cc7c4d77c6 100644
> --- a/drivers/clk/renesas/Makefile
> +++ b/drivers/clk/renesas/Makefile
> @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044)           += r9a07g044-cpg.o
>  obj-$(CONFIG_CLK_R9A07G054)            += r9a07g044-cpg.o
>  obj-$(CONFIG_CLK_R9A08G045)            += r9a08g045-cpg.o
>  obj-$(CONFIG_CLK_R9A09G011)            += r9a09g011-cpg.o
> +obj-$(CONFIG_CLK_R9A09G057)            += rzv2h-cpg.o

If this is a family-specific clock driver, please use a separate Kconfig
symbol, like other families do, and move it ...

>  obj-$(CONFIG_CLK_SH73A0)               += clk-sh73a0.o
>
>  # Family

... here.

> --- /dev/null
> +++ b/drivers/clk/renesas/rzv2h-cpg.c

> +/**
> + * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
> + *
> + * @rcdev: Reset controller entity
> + * @dev: CPG device
> + * @base: CPG register block base address
> + * @rmw_lock: protects register accesses
> + * @clks: Array containing all Core and Module Clocks
> + * @num_core_clks: Number of Core Clocks in clks[]
> + * @num_mod_clks: Number of Module Clocks in clks[]
> + * @num_resets: Number of Module Resets in info->resets[]
> + * @info: Pointer to platform data
> + */
> +struct rzv2h_cpg_priv {
> +       struct reset_controller_dev rcdev;
> +       struct device *dev;
> +       void __iomem *base;
> +       spinlock_t rmw_lock;

Unused

> +
> +       struct clk **clks;
> +       unsigned int num_core_clks;
> +       unsigned int num_mod_clks;
> +       unsigned int num_resets;
> +
> +       const struct rzv2h_cpg_info *info;
> +};

> +static struct clk
> +*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
> +                              void *data)
> +{
> +       unsigned int clkidx = clkspec->args[1];
> +       struct rzv2h_cpg_priv *priv = data;
> +       struct device *dev = priv->dev;
> +       const char *type;
> +       struct clk *clk;
> +
> +       switch (clkspec->args[0]) {
> +       case CPG_CORE:
> +               type = "core";
> +               clk = priv->clks[clkidx];

No range checking?

> +               break;
> +
> +       case CPG_MOD:
> +               type = "module";
> +               if (clkidx >= priv->num_mod_clks) {
> +                       dev_err(dev, "Invalid %s clock index %u\n", type,
> +                               clkidx);
> +                       return ERR_PTR(-EINVAL);
> +               }
> +               clk = priv->clks[priv->num_core_clks + clkidx];
> +               break;
> +
> +       default:
> +               dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
> +               return ERR_PTR(-EINVAL);
> +       }
> +
> +       if (IS_ERR(clk))
> +               dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
> +                       PTR_ERR(clk));
> +       else
> +               dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
> +                       clkspec->args[0], clkspec->args[1], clk,
> +                       clk_get_rate(clk));
> +       return clk;
> +}

> +static void __init
> +rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
> +                          const struct rzv2h_cpg_info *info,
> +                          struct rzv2h_cpg_priv *priv)
> +{
> +       struct mstp_clock *clock = NULL;
> +       struct device *dev = priv->dev;
> +       unsigned int id = mod->id;
> +       struct clk_init_data init;
> +       struct clk *parent, *clk;
> +       const char *parent_name;
> +       unsigned int i;
> +
> +       WARN_DEBUG(id < priv->num_core_clks);
> +       WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
> +       WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
> +       WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
> +
> +       if (!mod->name) {
> +               /* Skip NULLified clock */
> +               return;
> +       }

Do you have NULLified clocks?


> new file mode 100644
> index 000000000000..689c123d01c5
> --- /dev/null
> +++ b/drivers/clk/renesas/rzv2h-cpg.h

> +/**
> + * struct rzv2h_mod_clk - Module Clocks definitions
> + *
> + * @name: handle between common and hardware-specific interfaces
> + * @id: clock index in array containing all Core and Module Clocks
> + * @parent: id of parent clock
> + * @off: register offset

control register offset

> + * @bit: ON/MON bit

> + * @monoff: monitor register offset
> + * @monbit: monitor bit
> + */
> +struct rzv2h_mod_clk {
> +       const char *name;
> +       unsigned int id;
> +       unsigned int parent;
> +       u16 off;
> +       u8 bit;

Perhaps name them ctrl{off,bit}?

However, as all CPG_CLKONn registers are contiguous, storing
the register index (u8) might be better than the register offset (u16)?

> +       u16 monoff;
> +       u8 monbit;

Likewise for the CPG_CLKMONx registers...

> +};
> +
> +#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _monoff, _monbit)        \
> +       { \
> +               .name = _name, \
> +               .id = MOD_CLK_BASE + (_id), \
> +               .parent = (_parent), \
> +               .off = (_off), \
> +               .bit = (_bit), \
> +               .monoff = (_monoff), \
> +               .monbit = (_monbit), \
> +       }
> +
> +#define DEF_MOD(_name, _id, _parent, _off, _bit, _monoff, _monbit)     \
> +       DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _monoff, _monbit)
> +
> +/**
> + * struct rzv2h_reset - Reset definitions
> + *
> + * @off: reset register offset
> + * @bit: reset bit
> + * @monoff: monitor register offset
> + * @monbit: monitor bit
> + */
> +struct rzv2h_reset {
> +       u16 resoff;
> +       u8 resbit;
> +       u16 monoff;
> +       u8 monbit;

... and the CPG_RSTx and CPG_RSTMONx registers.


> +};
> +
> +#define DEF_RST(_id, _resoff, _resbit, _monoff, _monbit)       \
> +       [_id] = { \
> +               .resoff = (_resoff), \
> +               .resbit = (_resbit), \
> +               .monoff = (_monoff), \
> +               .monbit = (_monbit) \
> +       }
> +
> +/**
> + * struct rzv2h_cpg_info - SoC-specific CPG Description
> + *
> + * @core_clks: Array of Core Clock definitions
> + * @num_core_clks: Number of entries in core_clks[]
> + * @num_total_core_clks: Total number of Core Clocks (exported + internal)
> + *
> + * @mod_clks: Array of Module Clock definitions
> + * @num_mod_clks: Number of entries in mod_clks[]
> + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
> + *
> + * @resets: Array of Module Reset definitions
> + * @num_resets: Number of entries in resets[]
> + *
> + * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
> + *                 should not be disabled without a knowledgeable driver
> + * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
> + * @pll_get_clk1_offset: Function pointer to get PLL CLK1 offset
> + * @pll_get_clk2_offset: Function pointer to get PLL CLK2 offset
> + */
> +struct rzv2h_cpg_info {

> +       /* function pointers for PLL information */
> +       int (*pll_get_clk1_offset)(int clk);
> +       int (*pll_get_clk2_offset)(int clk);

Why are these function pointers?

> +};
> +
> +#endif /* __RENESAS_RZV2H_CPG_H__ */

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] clk: renesas: Add RZ/V2H CPG core wrapper driver

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Tue, Jun 4, 2024 at 5:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add CPG core helper wrapper driver for RZ/V2H SoC.
>
> What is a "core helper wrapper"? ;-)
>
As this file basically uses core API for clock and reset, I worded the
commit as such.

> Looking at the structure, this looks like a family-specific clock driver?
Yes, as the CPG on RZ/V2H varies quite a bit compared to RZ/G2L I have
introduced a family-specific clock driver

> Will there be more RZ/V2H-alike SoCs?
>
I'm not sure about it tbh!

> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  drivers/clk/renesas/Kconfig     |   5 +
> >  drivers/clk/renesas/Makefile    |   1 +
> >  drivers/clk/renesas/rzv2h-cpg.c | 673 ++++++++++++++++++++++++++++++++
> >  drivers/clk/renesas/rzv2h-cpg.h | 149 +++++++
> >  4 files changed, 828 insertions(+)
> >  create mode 100644 drivers/clk/renesas/rzv2h-cpg.c
> >  create mode 100644 drivers/clk/renesas/rzv2h-cpg.h
> >
> > diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
> > index d252150402e8..254203c2cb2e 100644
> > --- a/drivers/clk/renesas/Kconfig
> > +++ b/drivers/clk/renesas/Kconfig
> > @@ -40,6 +40,7 @@ config CLK_RENESAS
> >         select CLK_R9A07G054 if ARCH_R9A07G054
> >         select CLK_R9A08G045 if ARCH_R9A08G045
> >         select CLK_R9A09G011 if ARCH_R9A09G011
> > +       select CLK_R9A09G057 if ARCH_R9A09G057
> >         select CLK_SH73A0 if ARCH_SH73A0
> >
> >  if CLK_RENESAS
> > @@ -193,6 +194,10 @@ config CLK_R9A09G011
> >         bool "RZ/V2M clock support" if COMPILE_TEST
> >         select CLK_RZG2L
> >
> > +config CLK_R9A09G057
> > +       bool "Renesas RZ/V2H(P) clock support" if COMPILE_TEST
>
> Please drop "Renesas "
> (few other symbols have it, I'll fix the remaining).
>
OK.

> > +       select RESET_CONTROLLER
> > +
> >  config CLK_SH73A0
> >         bool "SH-Mobile AG5 clock support" if COMPILE_TEST
> >         select CLK_RENESAS_CPG_MSTP
> > diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
> > index f7e18679c3b8..79cc7c4d77c6 100644
> > --- a/drivers/clk/renesas/Makefile
> > +++ b/drivers/clk/renesas/Makefile
> > @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044)           += r9a07g044-cpg.o
> >  obj-$(CONFIG_CLK_R9A07G054)            += r9a07g044-cpg.o
> >  obj-$(CONFIG_CLK_R9A08G045)            += r9a08g045-cpg.o
> >  obj-$(CONFIG_CLK_R9A09G011)            += r9a09g011-cpg.o
> > +obj-$(CONFIG_CLK_R9A09G057)            += rzv2h-cpg.o
>
> If this is a family-specific clock driver, please use a separate Kconfig
> symbol, like other families do, and move it ...
>
> >  obj-$(CONFIG_CLK_SH73A0)               += clk-sh73a0.o
> >
> >  # Family
>
> ... here.
>
OK, I will move it to the family section.

> > --- /dev/null
> > +++ b/drivers/clk/renesas/rzv2h-cpg.c
>
> > +/**
> > + * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
> > + *
> > + * @rcdev: Reset controller entity
> > + * @dev: CPG device
> > + * @base: CPG register block base address
> > + * @rmw_lock: protects register accesses
> > + * @clks: Array containing all Core and Module Clocks
> > + * @num_core_clks: Number of Core Clocks in clks[]
> > + * @num_mod_clks: Number of Module Clocks in clks[]
> > + * @num_resets: Number of Module Resets in info->resets[]
> > + * @info: Pointer to platform data
> > + */
> > +struct rzv2h_cpg_priv {
> > +       struct reset_controller_dev rcdev;
> > +       struct device *dev;
> > +       void __iomem *base;
> > +       spinlock_t rmw_lock;
>
> Unused
>
I will drop it.

> > +
> > +       struct clk **clks;
> > +       unsigned int num_core_clks;
> > +       unsigned int num_mod_clks;
> > +       unsigned int num_resets;
> > +
> > +       const struct rzv2h_cpg_info *info;
> > +};
>
> > +static struct clk
> > +*rzv2h_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
> > +                              void *data)
> > +{
> > +       unsigned int clkidx = clkspec->args[1];
> > +       struct rzv2h_cpg_priv *priv = data;
> > +       struct device *dev = priv->dev;
> > +       const char *type;
> > +       struct clk *clk;
> > +
> > +       switch (clkspec->args[0]) {
> > +       case CPG_CORE:
> > +               type = "core";
> > +               clk = priv->clks[clkidx];
>
> No range checking?
>
I will add a check for it.

> > +               break;
> > +
> > +       case CPG_MOD:
> > +               type = "module";
> > +               if (clkidx >= priv->num_mod_clks) {
> > +                       dev_err(dev, "Invalid %s clock index %u\n", type,
> > +                               clkidx);
> > +                       return ERR_PTR(-EINVAL);
> > +               }
> > +               clk = priv->clks[priv->num_core_clks + clkidx];
> > +               break;
> > +
> > +       default:
> > +               dev_err(dev, "Invalid CPG clock type %u\n", clkspec->args[0]);
> > +               return ERR_PTR(-EINVAL);
> > +       }
> > +
> > +       if (IS_ERR(clk))
> > +               dev_err(dev, "Cannot get %s clock %u: %ld", type, clkidx,
> > +                       PTR_ERR(clk));
> > +       else
> > +               dev_dbg(dev, "clock (%u, %u) is %pC at %lu Hz\n",
> > +                       clkspec->args[0], clkspec->args[1], clk,
> > +                       clk_get_rate(clk));
> > +       return clk;
> > +}
>
> > +static void __init
> > +rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
> > +                          const struct rzv2h_cpg_info *info,
> > +                          struct rzv2h_cpg_priv *priv)
> > +{
> > +       struct mstp_clock *clock = NULL;
> > +       struct device *dev = priv->dev;
> > +       unsigned int id = mod->id;
> > +       struct clk_init_data init;
> > +       struct clk *parent, *clk;
> > +       const char *parent_name;
> > +       unsigned int i;
> > +
> > +       WARN_DEBUG(id < priv->num_core_clks);
> > +       WARN_DEBUG(id >= priv->num_core_clks + priv->num_mod_clks);
> > +       WARN_DEBUG(mod->parent >= priv->num_core_clks + priv->num_mod_clks);
> > +       WARN_DEBUG(PTR_ERR(priv->clks[id]) != -ENOENT);
> > +
> > +       if (!mod->name) {
> > +               /* Skip NULLified clock */
> > +               return;
> > +       }
>
> Do you have NULLified clocks?
>
Nope, I 'll drop this check.

>
> > new file mode 100644
> > index 000000000000..689c123d01c5
> > --- /dev/null
> > +++ b/drivers/clk/renesas/rzv2h-cpg.h
>
> > +/**
> > + * struct rzv2h_mod_clk - Module Clocks definitions
> > + *
> > + * @name: handle between common and hardware-specific interfaces
> > + * @id: clock index in array containing all Core and Module Clocks
> > + * @parent: id of parent clock
> > + * @off: register offset
>
> control register offset
>
> > + * @bit: ON/MON bit
>
> > + * @monoff: monitor register offset
> > + * @monbit: monitor bit
> > + */
> > +struct rzv2h_mod_clk {
> > +       const char *name;
> > +       unsigned int id;
> > +       unsigned int parent;
> > +       u16 off;
> > +       u8 bit;
>
> Perhaps name them ctrl{off,bit}?
>
> However, as all CPG_CLKONn registers are contiguous, storing
> the register index (u8) might be better than the register offset (u16)?
>
> > +       u16 monoff;
> > +       u8 monbit;
>
> Likewise for the CPG_CLKMONx registers...
>
> > +};
> > +
> > +#define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _monoff, _monbit)        \
> > +       { \
> > +               .name = _name, \
> > +               .id = MOD_CLK_BASE + (_id), \
> > +               .parent = (_parent), \
> > +               .off = (_off), \
> > +               .bit = (_bit), \
> > +               .monoff = (_monoff), \
> > +               .monbit = (_monbit), \
> > +       }
> > +
> > +#define DEF_MOD(_name, _id, _parent, _off, _bit, _monoff, _monbit)     \
> > +       DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _monoff, _monbit)
> > +
> > +/**
> > + * struct rzv2h_reset - Reset definitions
> > + *
> > + * @off: reset register offset
> > + * @bit: reset bit
> > + * @monoff: monitor register offset
> > + * @monbit: monitor bit
> > + */
> > +struct rzv2h_reset {
> > +       u16 resoff;
> > +       u8 resbit;
> > +       u16 monoff;
> > +       u8 monbit;
>
> ... and the CPG_RSTx and CPG_RSTMONx registers.
>
>
Ok, I will store the indexes for CLK/CLKMON/RST/RSTMON regs.

> > +};
> > +
> > +#define DEF_RST(_id, _resoff, _resbit, _monoff, _monbit)       \
> > +       [_id] = { \
> > +               .resoff = (_resoff), \
> > +               .resbit = (_resbit), \
> > +               .monoff = (_monoff), \
> > +               .monbit = (_monbit) \
> > +       }
> > +
> > +/**
> > + * struct rzv2h_cpg_info - SoC-specific CPG Description
> > + *
> > + * @core_clks: Array of Core Clock definitions
> > + * @num_core_clks: Number of entries in core_clks[]
> > + * @num_total_core_clks: Total number of Core Clocks (exported + internal)
> > + *
> > + * @mod_clks: Array of Module Clock definitions
> > + * @num_mod_clks: Number of entries in mod_clks[]
> > + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
> > + *
> > + * @resets: Array of Module Reset definitions
> > + * @num_resets: Number of entries in resets[]
> > + *
> > + * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
> > + *                 should not be disabled without a knowledgeable driver
> > + * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
> > + * @pll_get_clk1_offset: Function pointer to get PLL CLK1 offset
> > + * @pll_get_clk2_offset: Function pointer to get PLL CLK2 offset
> > + */
> > +struct rzv2h_cpg_info {
>
> > +       /* function pointers for PLL information */
> > +       int (*pll_get_clk1_offset)(int clk);
> > +       int (*pll_get_clk2_offset)(int clk);
>
> Why are these function pointers?
>
To get the offsets for PLL CLK1/2. But I plan to drop these and get
the offset from conf instead.

Cheers,
Prabhakar

Re: [PATCH 3/4] clk: renesas: Add RZ/V2H CPG core wrapper driver

[Geert Uytterhoeven]

Hi Prabhakar,

On Tue, Jun 11, 2024 at 12:03 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Tue, Jun 4, 2024 at 5:01 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add CPG core helper wrapper driver for RZ/V2H SoC.
> >
> > What is a "core helper wrapper"? ;-)
> >
> As this file basically uses core API for clock and reset, I worded the
> commit as such.
>
> > Looking at the structure, this looks like a family-specific clock driver?
> Yes, as the CPG on RZ/V2H varies quite a bit compared to RZ/G2L I have
> introduced a family-specific clock driver
>
> > Will there be more RZ/V2H-alike SoCs?
> >
> I'm not sure about it tbh!

OK, I see we did the same when introducing RZ/G2L support.

> > > --- /dev/null
> > > +++ b/drivers/clk/renesas/rzv2h-cpg.h

> > > +/**
> > > + * struct rzv2h_cpg_info - SoC-specific CPG Description
> > > + *
> > > + * @core_clks: Array of Core Clock definitions
> > > + * @num_core_clks: Number of entries in core_clks[]
> > > + * @num_total_core_clks: Total number of Core Clocks (exported + internal)
> > > + *
> > > + * @mod_clks: Array of Module Clock definitions
> > > + * @num_mod_clks: Number of entries in mod_clks[]
> > > + * @num_hw_mod_clks: Number of Module Clocks supported by the hardware
> > > + *
> > > + * @resets: Array of Module Reset definitions
> > > + * @num_resets: Number of entries in resets[]
> > > + *
> > > + * @crit_mod_clks: Array with Module Clock IDs of critical clocks that
> > > + *                 should not be disabled without a knowledgeable driver
> > > + * @num_crit_mod_clks: Number of entries in crit_mod_clks[]
> > > + * @pll_get_clk1_offset: Function pointer to get PLL CLK1 offset
> > > + * @pll_get_clk2_offset: Function pointer to get PLL CLK2 offset
> > > + */
> > > +struct rzv2h_cpg_info {
> >
> > > +       /* function pointers for PLL information */
> > > +       int (*pll_get_clk1_offset)(int clk);
> > > +       int (*pll_get_clk2_offset)(int clk);
> >
> > Why are these function pointers?

I meant "... and not pointer/len pairs?".

> To get the offsets for PLL CLK1/2. But I plan to drop these and get
> the offset from conf instead.

OK

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 4/4] clk: renesas: Add RZ/V2H(P) CPG helper driver

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add RZ/V2H(P) CPG helper driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/clk/renesas/Makefile        |   2 +-
 drivers/clk/renesas/r9a09g057-cpg.c | 112 ++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.c     |   4 +
 drivers/clk/renesas/rzv2h-cpg.h     |   2 +
 4 files changed, 119 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/renesas/r9a09g057-cpg.c

diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index 79cc7c4d77c6..df0ba8bb5e6f 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -37,7 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044)		+= r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A07G054)		+= r9a07g044-cpg.o
 obj-$(CONFIG_CLK_R9A08G045)		+= r9a08g045-cpg.o
 obj-$(CONFIG_CLK_R9A09G011)		+= r9a09g011-cpg.o
-obj-$(CONFIG_CLK_R9A09G057)		+= rzv2h-cpg.o
+obj-$(CONFIG_CLK_R9A09G057)		+= rzv2h-cpg.o r9a09g057-cpg.o
 obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o
 
 # Family
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
new file mode 100644
index 000000000000..21f8be90107c
--- /dev/null
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/V2H(P) CPG driver
+ *
+ * Copyright (C) 2024 Renesas Electronics Corp.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/clock/r9a09g057-cpg.h>
+
+#include "rzv2h-cpg.h"
+
+enum pll_clk {
+	PLLCM33,
+	PLLCLN,
+	PLLDTY,
+	PLLCA55,
+	PLLVDO,
+	PLLETH,
+	PLLDSI,
+	PLLDDR0,
+	PLLDDR1,
+	PLLGPU,
+	PLLDRP,
+};
+
+static int pll_clk1_offset[] = { -EINVAL, -EINVAL, -EINVAL, 0x64, -EINVAL,
+			       -EINVAL, 0xC4, -EINVAL, -EINVAL, 0x124, 0x144 };
+static int pll_clk2_offset[] = { -EINVAL, -EINVAL, -EINVAL, 0x68, -EINVAL,
+			       -EINVAL, 0xC8, -EINVAL, -EINVAL, 0x128, 0x148 };
+
+enum clk_ids {
+	/* External Input Clocks */
+	CLK_EXTAL,
+	CLK_XINMAINCLK,
+	/* Internal Core Clocks */
+	CLK_PLLCM33,
+	CLK_PLLCM33_DIV16,
+
+	CLK_PLLCA55,
+	/* Module Clocks */
+	MOD_CLK_BASE,
+};
+
+static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = {
+	/* External Clock Inputs */
+	DEF_INPUT("extal", CLK_EXTAL),
+
+	/* Internal Core Clocks */
+	DEF_FIXED(".main", CLK_XINMAINCLK, CLK_EXTAL, 1, 1),
+	DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_EXTAL, 200, 3),
+	DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
+
+	DEF_PLL(".pllca55", CLK_PLLCA55, CLK_EXTAL, PLLCA55),
+};
+
+static int rzv2h_pll_get_clk1_offset(int clk)
+{
+	if (clk < 0 || clk >= ARRAY_SIZE(pll_clk1_offset))
+		return -EINVAL;
+
+	return pll_clk1_offset[clk];
+}
+
+static int rzv2h_pll_get_clk2_offset(int clk)
+{
+	if (clk < 0 || clk >= ARRAY_SIZE(pll_clk2_offset))
+		return -EINVAL;
+
+	return pll_clk2_offset[clk];
+}
+
+static struct rzv2h_mod_clk r9a09g057_mod_clks[] = {
+	DEF_MOD("scif_0_clk_pck",		R9A09G057_SCIF_0_CLK_PCK, CLK_PLLCM33_DIV16,
+						0x620, 15, 0x810, 15),
+};
+
+static struct rzv2h_reset r9a09g057_resets[] = {
+	DEF_RST(R9A09G057_SCIF_0_RST_SYSTEM_N,		0x924,	5, 0xA10, 6),
+};
+
+static const unsigned int r9a09g057_crit_mod_clks[] __initconst = {
+	MOD_CLK_BASE + R9A09G057_ICU_0_PCLK_I,
+	MOD_CLK_BASE + R9A09G057_GIC_0_GICCLK,
+};
+
+const struct rzv2h_cpg_info r9a09g057_cpg_info = {
+	/* Core Clocks */
+	.core_clks = r9a09g057_core_clks,
+	.num_core_clks = ARRAY_SIZE(r9a09g057_core_clks),
+	.num_total_core_clks = MOD_CLK_BASE,
+
+	/* Critical Module Clocks */
+	.crit_mod_clks = r9a09g057_crit_mod_clks,
+	.num_crit_mod_clks = ARRAY_SIZE(r9a09g057_crit_mod_clks),
+
+	/* Module Clocks */
+	.mod_clks = r9a09g057_mod_clks,
+	.num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks),
+	.num_hw_mod_clks = R9A09G057_TZCDDR_1_CLK400DG_ACP_ACLK4 + 1,
+
+	/* Resets */
+	.resets = r9a09g057_resets,
+	.num_resets = R9A09G057_DRPAI_0_ARESETN + 1, /* Last reset ID + 1 */
+
+	.pll_get_clk1_offset = &rzv2h_pll_get_clk1_offset,
+	.pll_get_clk2_offset = &rzv2h_pll_get_clk2_offset,
+};
diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c
index eb6b7ab86675..93866833ff21 100644
--- a/drivers/clk/renesas/rzv2h-cpg.c
+++ b/drivers/clk/renesas/rzv2h-cpg.c
@@ -653,6 +653,10 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id rzv2h_cpg_match[] = {
+	{
+		.compatible = "renesas,r9a09g057-cpg",
+		.data = &r9a09g057_cpg_info,
+	},
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
index 689c123d01c5..b764079d448d 100644
--- a/drivers/clk/renesas/rzv2h-cpg.h
+++ b/drivers/clk/renesas/rzv2h-cpg.h
@@ -146,4 +146,6 @@ struct rzv2h_cpg_info {
 	int (*pll_get_clk2_offset)(int clk);
 };
 
+extern const struct rzv2h_cpg_info r9a09g057_cpg_info;
+
 #endif	/* __RENESAS_RZV2H_CPG_H__ */
-- 
2.34.1

Re: [PATCH 4/4] clk: renesas: Add RZ/V2H(P) CPG helper driver

[Geert Uytterhoeven]

Hii Prabhakar,

Thanks for your patch!

On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add RZ/V2H(P) CPG helper driver.

Drop "helper"?

> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

> --- /dev/null
> +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> @@ -0,0 +1,112 @@

> +static int pll_clk1_offset[] = { -EINVAL, -EINVAL, -EINVAL, 0x64, -EINVAL,
> +                              -EINVAL, 0xC4, -EINVAL, -EINVAL, 0x124, 0x144 };
> +static int pll_clk2_offset[] = { -EINVAL, -EINVAL, -EINVAL, 0x68, -EINVAL,
> +                              -EINVAL, 0xC8, -EINVAL, -EINVAL, 0x128, 0x148 };

const (both)

Both arrays are very similar: all valid values differ by an offset of 4.
If that is universal, perhaps the second one can be dropped, and
the offset can be handled by the user?

> +static struct rzv2h_mod_clk r9a09g057_mod_clks[] = {

const

> +       DEF_MOD("scif_0_clk_pck",               R9A09G057_SCIF_0_CLK_PCK, CLK_PLLCM33_DIV16,
> +                                               0x620, 15, 0x810, 15),
> +};
> +
> +static struct rzv2h_reset r9a09g057_resets[] = {

const

> +       DEF_RST(R9A09G057_SCIF_0_RST_SYSTEM_N,          0x924,  5, 0xA10, 6),
> +};


Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 4/4] clk: renesas: Add RZ/V2H(P) CPG helper driver

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Wed, Jun 5, 2024 at 8:06 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hii Prabhakar,
>
> Thanks for your patch!
>
> On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add RZ/V2H(P) CPG helper driver.
>
> Drop "helper"?
>
OK.

> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> > --- /dev/null
> > +++ b/drivers/clk/renesas/r9a09g057-cpg.c
> > @@ -0,0 +1,112 @@
>
> > +static int pll_clk1_offset[] = { -EINVAL, -EINVAL, -EINVAL, 0x64, -EINVAL,
> > +                              -EINVAL, 0xC4, -EINVAL, -EINVAL, 0x124, 0x144 };
> > +static int pll_clk2_offset[] = { -EINVAL, -EINVAL, -EINVAL, 0x68, -EINVAL,
> > +                              -EINVAL, 0xC8, -EINVAL, -EINVAL, 0x128, 0x148 };
>
> const (both)
>
> Both arrays are very similar: all valid values differ by an offset of 4.
> If that is universal, perhaps the second one can be dropped, and
> the offset can be handled by the user?
>
Agreed.

> > +static struct rzv2h_mod_clk r9a09g057_mod_clks[] = {
>
> const
>
Ok (and below)

> > +       DEF_MOD("scif_0_clk_pck",               R9A09G057_SCIF_0_CLK_PCK, CLK_PLLCM33_DIV16,
> > +                                               0x620, 15, 0x810, 15),
> > +};
> > +
> > +static struct rzv2h_reset r9a09g057_resets[] = {
>
> const
>
> > +       DEF_RST(R9A09G057_SCIF_0_RST_SYSTEM_N,          0x924,  5, 0xA10, 6),
> > +};
>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds