From: Conor Dooley <conor.dooley@microchip.com>
To: <linux-riscv@lists.infradead.org>
Cc: <conor@kernel.org>, <conor.dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Daire McNamara" <daire.mcnamara@microchip.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>,
<devicetree@vger.kernel.org>
Subject: [PATCH v1 5/5] riscv: dts: microchip: update pcie reg properties
Date: Mon, 10 Jun 2024 12:09:17 +0100 [thread overview]
Message-ID: <20240610-panda-revenue-7248a5403dfc@wendy> (raw)
In-Reply-To: <20240610-vertical-frugally-a92a55427dd9@wendy>
Split the "apb" regions of memory on PolarFire SoC devicetrees PCIe
nodes into two regions, so that it will be possible to distinguish
between which root port instance is in use. Currently the "apb" region
points to the base of the root port region and the Linux driver uses
hard-coded offsets to find the "control" and "bridge" regions. The new
method for describing these regions explicitly passes the base address
for the two regions of interest.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 6 ++++--
arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi | 6 ++++--
arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi | 6 ++++--
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index 33e76db965bbc..f151aa2606d7b 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -45,8 +45,10 @@ pcie: pcie@3000000000 {
#size-cells = <0x2>;
device_type = "pci";
dma-noncoherent;
- reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
- reg-names = "cfg", "apb";
+ reg = <0x30 0x0 0x0 0x8000000>,
+ <0x0 0x43008000 0x0 0x00002000>,
+ <0x0 0x4300a000 0x0 0x00002000>;
+ reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
index 8230f06ddf48a..f5036126f2654 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi
@@ -20,8 +20,10 @@ pcie: pcie@2000000000 {
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
- reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
- reg-names = "cfg", "apb";
+ reg = <0x30 0x0 0x0 0x8000000>,
+ <0x0 0x43008000 0x0 0x00002000>,
+ <0x0 0x4300a000 0x0 0x00002000>;
+ reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
index 9a56de7b91d64..121b13f9c8bf4 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi
@@ -20,8 +20,10 @@ pcie: pcie@2000000000 {
#interrupt-cells = <0x1>;
#size-cells = <0x2>;
device_type = "pci";
- reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
- reg-names = "cfg", "apb";
+ reg = <0x30 0x0 0x0 0x8000000>,
+ <0x0 0x43008000 0x0 0x00002000>,
+ <0x0 0x4300a000 0x0 0x00002000>;
+ reg-names = "cfg", "bridge", "ctrl";
bus-range = <0x0 0x7f>;
interrupt-parent = <&plic>;
interrupts = <119>;
--
2.43.2
next prev parent reply other threads:[~2024-06-10 11:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-10 11:09 [PATCH v1 0/5] PolarFire SoC Icicle Reference Design PCIe ?support?/fixes Conor Dooley
2024-06-10 11:09 ` [PATCH v1 1/5] cache: ccache: allow building for PolarFire Conor Dooley
2024-06-12 9:23 ` Emil Renner Berthing
2024-06-10 11:09 ` [PATCH v1 2/5] cache: ccache: add mpfs to nonstandard cache ops list Conor Dooley
2024-06-12 9:23 ` Emil Renner Berthing
2024-06-10 11:09 ` [PATCH v1 3/5] RISC-V: Add an MPFS erratum for PCIe Conor Dooley
2024-06-12 9:29 ` Emil Renner Berthing
2024-06-10 11:09 ` [PATCH v1 4/5] riscv: dts: microchip: modify memory map & add dma-ranges for pcie on icicle Conor Dooley
2024-06-10 11:09 ` Conor Dooley [this message]
2024-06-10 11:16 ` [PATCH v1 0/5] PolarFire SoC Icicle Reference Design PCIe ?support?/fixes Conor Dooley
2024-06-10 19:55 ` Rob Herring (Arm)
2024-06-10 21:28 ` Conor Dooley
2024-07-03 20:09 ` Palmer Dabbelt
2024-07-03 20:15 ` Conor Dooley
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