From: Conor Dooley <conor.dooley@microchip.com>
To: <linux-riscv@lists.infradead.org>
Cc: <conor@kernel.org>, <conor.dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
"Daire McNamara" <daire.mcnamara@microchip.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Samuel Holland <samuel.holland@sifive.com>,
<devicetree@vger.kernel.org>
Subject: [PATCH v1 2/5] cache: ccache: add mpfs to nonstandard cache ops list
Date: Mon, 10 Jun 2024 12:09:14 +0100 [thread overview]
Message-ID: <20240610-reenact-amicably-bd088724b3cb@wendy> (raw)
In-Reply-To: <20240610-vertical-frugally-a92a55427dd9@wendy>
On PolarFire SoC, for performance reasons, we want to use non-coherent
DMA. Add it to the match table with the non-standard non-coherent
cache ops requirement.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/cache/sifive_ccache.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c
index 6874b72ec59d8..277e66a61efdc 100644
--- a/drivers/cache/sifive_ccache.c
+++ b/drivers/cache/sifive_ccache.c
@@ -122,6 +122,8 @@ static const struct of_device_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu740-c000-ccache" },
{ .compatible = "starfive,jh7100-ccache",
.data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS | QUIRK_BROKEN_DATA_UNCORR) },
+ { .compatible = "microchip,mpfs-ccache",
+ .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) },
{ .compatible = "sifive,ccache0" },
{ /* end of table */ }
};
--
2.43.2
next prev parent reply other threads:[~2024-06-10 11:10 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-10 11:09 [PATCH v1 0/5] PolarFire SoC Icicle Reference Design PCIe ?support?/fixes Conor Dooley
2024-06-10 11:09 ` [PATCH v1 1/5] cache: ccache: allow building for PolarFire Conor Dooley
2024-06-12 9:23 ` Emil Renner Berthing
2024-06-10 11:09 ` Conor Dooley [this message]
2024-06-12 9:23 ` [PATCH v1 2/5] cache: ccache: add mpfs to nonstandard cache ops list Emil Renner Berthing
2024-06-10 11:09 ` [PATCH v1 3/5] RISC-V: Add an MPFS erratum for PCIe Conor Dooley
2024-06-12 9:29 ` Emil Renner Berthing
2024-06-10 11:09 ` [PATCH v1 4/5] riscv: dts: microchip: modify memory map & add dma-ranges for pcie on icicle Conor Dooley
2024-06-10 11:09 ` [PATCH v1 5/5] riscv: dts: microchip: update pcie reg properties Conor Dooley
2024-06-10 11:16 ` [PATCH v1 0/5] PolarFire SoC Icicle Reference Design PCIe ?support?/fixes Conor Dooley
2024-06-10 19:55 ` Rob Herring (Arm)
2024-06-10 21:28 ` Conor Dooley
2024-07-03 20:09 ` Palmer Dabbelt
2024-07-03 20:15 ` Conor Dooley
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