* [PATCH v1 0/2] Support for Melfas lmfbx101117480 MIPI-DSI panel
@ 2024-07-02 13:01 Cong Yang
2024-07-02 13:01 ` [PATCH v1 1/2] dt-bindings: display: panel: Add compatible for melfas lmfbx101117480 Cong Yang
2024-07-02 13:01 ` [PATCH v1 2/2] drm/panel: jd9365da: Support for Melfas lmfbx101117480 MIPI-DSI panel Cong Yang
0 siblings, 2 replies; 6+ messages in thread
From: Cong Yang @ 2024-07-02 13:01 UTC (permalink / raw)
To: sam, neil.armstrong, daniel, dianders, linus.walleij, swboyd,
airlied, dmitry.baryshkov, krzysztof.kozlowski+dt, robh+dt,
conor+dt
Cc: lvzhaoxiong, dri-devel, devicetree, linux-kernel, Cong Yang
Melfas lmfbx101117480 is a 10.1" WXGA TFT LCD panel with jadard-jd9365da
controller, which fits in nicely with the existing panel-jadard-jd9365da-h3
driver. Add compatible for melfas lmfbx101117480 in dt-bindings.
Cong Yang (2):
dt-bindings: display: panel: Add compatible for melfas lmfbx101117480
drm/panel: jd9365da: Support for Melfas lmfbx101117480 MIPI-DSI panel
.../display/panel/jadard,jd9365da-h3.yaml | 1 +
.../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 246 ++++++++++++++++++
2 files changed, 247 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v1 1/2] dt-bindings: display: panel: Add compatible for melfas lmfbx101117480
2024-07-02 13:01 [PATCH v1 0/2] Support for Melfas lmfbx101117480 MIPI-DSI panel Cong Yang
@ 2024-07-02 13:01 ` Cong Yang
2024-07-02 14:42 ` Conor Dooley
2024-07-02 13:01 ` [PATCH v1 2/2] drm/panel: jd9365da: Support for Melfas lmfbx101117480 MIPI-DSI panel Cong Yang
1 sibling, 1 reply; 6+ messages in thread
From: Cong Yang @ 2024-07-02 13:01 UTC (permalink / raw)
To: sam, neil.armstrong, daniel, dianders, linus.walleij, swboyd,
airlied, dmitry.baryshkov, krzysztof.kozlowski+dt, robh+dt,
conor+dt
Cc: lvzhaoxiong, dri-devel, devicetree, linux-kernel, Cong Yang
The Melfas lmfbx101117480 is a 10.1" WXGA TFT LCD panel with jadard-jd9365da
controller. Hence, we add a new compatible with panel specific config.
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
---
.../devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
index 3d5bede98cf1..b8783eba3ddc 100644
--- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
+++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml
@@ -18,6 +18,7 @@ properties:
- enum:
- chongzhou,cz101b4001
- kingdisplay,kd101ne3-40ti
+ - melfas,lmfbx101117480
- radxa,display-10hd-ad001
- radxa,display-8hd-ad002
- const: jadard,jd9365da-h3
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v1 2/2] drm/panel: jd9365da: Support for Melfas lmfbx101117480 MIPI-DSI panel
2024-07-02 13:01 [PATCH v1 0/2] Support for Melfas lmfbx101117480 MIPI-DSI panel Cong Yang
2024-07-02 13:01 ` [PATCH v1 1/2] dt-bindings: display: panel: Add compatible for melfas lmfbx101117480 Cong Yang
@ 2024-07-02 13:01 ` Cong Yang
2024-07-03 13:10 ` Linus Walleij
1 sibling, 1 reply; 6+ messages in thread
From: Cong Yang @ 2024-07-02 13:01 UTC (permalink / raw)
To: sam, neil.armstrong, daniel, dianders, linus.walleij, swboyd,
airlied, dmitry.baryshkov, krzysztof.kozlowski+dt, robh+dt,
conor+dt
Cc: lvzhaoxiong, dri-devel, devicetree, linux-kernel, Cong Yang
The Melfas lmfbx101117480 is a 10.1" WXGA TFT-LCD panel, use jd9365da
controller, which fits in nicely with the existing panel-jadard-jd9365da-h3
driver. Hence, we add a new compatible with panel specific config.
Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
---
.../gpu/drm/panel/panel-jadard-jd9365da-h3.c | 246 ++++++++++++++++++
1 file changed, 246 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
index c6b669866fed..5b525a111b90 100644
--- a/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
+++ b/drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
@@ -850,6 +850,248 @@ static const struct jadard_panel_desc kingdisplay_kd101ne3_40ti_desc = {
.enter_sleep_to_reset_down_delay_ms = 100,
};
+static int melfas_lmfbx101117480_init_cmds(struct jadard *jadard)
+{
+ struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
+
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xbf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0xbf);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x70);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x2d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x7e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xfe);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x28);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x12);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x78);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0xff);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xa0);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x74);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x8e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5a, 0x2e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x1a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x69);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x59);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x68);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x5b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6c, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x24);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x12);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x7f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x69);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x59);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x30);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7a, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7b, 0x68);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7c, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7d, 0x5b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7e, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7f, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x24);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x12);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x52);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x50);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x4e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x4c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0a, 0x4a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0b, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0c, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0d, 0x46);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x44);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0f, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x53);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x51);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1a, 0x77);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1b, 0x57);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1c, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1d, 0x4f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1e, 0x4d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1f, 0x5f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x4b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x47);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x45);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x41);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2a, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x55);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2c, 0x13);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2d, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2f, 0x01);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x30, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x31, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x32, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x33, 0x0d);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x34, 0x0f);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x35, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x07);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x09);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3a, 0x0b);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3b, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3c, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3d, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3e, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3f, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x42, 0x12);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x46, 0x37);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x47, 0x17);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x48, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x49, 0x0c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4a, 0x0e);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4b, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4c, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4d, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4e, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4f, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x50, 0x0a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x51, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x52, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x53, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x54, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0x15);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5b, 0x10);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5c, 0x06);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5d, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5e, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5f, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x40);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x6c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x75);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0xb4);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x6c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6a, 0x6c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6b, 0x0c);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6d, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6e, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6f, 0x88);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xbb);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x05);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2a);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x04);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x23);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x11);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0e, 0x48);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x49);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2b, 0x08);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2e, 0x03);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe6, 0x02);
+ mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe7, 0x06);
+
+ return dsi_ctx.accum_err;
+};
+
+static const struct jadard_panel_desc melfas_lmfbx101117480_desc = {
+ .mode = {
+ .clock = (800 + 24 + 24 + 24) * (1280 + 30 + 4 + 8) * 60 / 1000,
+
+ .hdisplay = 800,
+ .hsync_start = 800 + 24,
+ .hsync_end = 800 + 24 + 24,
+ .htotal = 800 + 24 + 24 + 24,
+
+ .vdisplay = 1280,
+ .vsync_start = 1280 + 30,
+ .vsync_end = 1280 + 30 + 4,
+ .vtotal = 1280 + 30 + 4 + 8,
+
+ .width_mm = 135,
+ .height_mm = 216,
+ .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
+ },
+ .lanes = 4,
+ .format = MIPI_DSI_FMT_RGB888,
+ .init = melfas_lmfbx101117480_init_cmds,
+ .lp11_before_reset = true,
+ .reset_before_power_off_vcioo = true,
+ .vcioo_to_lp11_delay_ms = 5,
+ .lp11_to_reset_delay_ms = 10,
+ .exit_sleep_to_display_on_delay_ms = 120,
+ .display_on_delay_ms = 20,
+ .backlight_off_to_display_off_delay_ms = 100,
+ .display_off_to_enter_sleep_delay_ms = 50,
+ .enter_sleep_to_reset_down_delay_ms = 100,
+};
+
static int jadard_dsi_probe(struct mipi_dsi_device *dsi)
{
struct device *dev = &dsi->dev;
@@ -926,6 +1168,10 @@ static const struct of_device_id jadard_of_match[] = {
.compatible = "kingdisplay,kd101ne3-40ti",
.data = &kingdisplay_kd101ne3_40ti_desc
},
+ {
+ .compatible = "melfas,lmfbx101117480",
+ .data = &melfas_lmfbx101117480_desc
+ },
{
.compatible = "radxa,display-10hd-ad001",
.data = &cz101b4001_desc
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v1 1/2] dt-bindings: display: panel: Add compatible for melfas lmfbx101117480
2024-07-02 13:01 ` [PATCH v1 1/2] dt-bindings: display: panel: Add compatible for melfas lmfbx101117480 Cong Yang
@ 2024-07-02 14:42 ` Conor Dooley
0 siblings, 0 replies; 6+ messages in thread
From: Conor Dooley @ 2024-07-02 14:42 UTC (permalink / raw)
To: Cong Yang
Cc: sam, neil.armstrong, daniel, dianders, linus.walleij, swboyd,
airlied, dmitry.baryshkov, krzysztof.kozlowski+dt, robh+dt,
conor+dt, lvzhaoxiong, dri-devel, devicetree, linux-kernel
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On Tue, Jul 02, 2024 at 09:01:37PM +0800, Cong Yang wrote:
> The Melfas lmfbx101117480 is a 10.1" WXGA TFT LCD panel with jadard-jd9365da
> controller. Hence, we add a new compatible with panel specific config.
>
> Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 2/2] drm/panel: jd9365da: Support for Melfas lmfbx101117480 MIPI-DSI panel
2024-07-02 13:01 ` [PATCH v1 2/2] drm/panel: jd9365da: Support for Melfas lmfbx101117480 MIPI-DSI panel Cong Yang
@ 2024-07-03 13:10 ` Linus Walleij
2024-07-04 4:36 ` cong yang
0 siblings, 1 reply; 6+ messages in thread
From: Linus Walleij @ 2024-07-03 13:10 UTC (permalink / raw)
To: Cong Yang
Cc: sam, neil.armstrong, daniel, dianders, swboyd, airlied,
dmitry.baryshkov, krzysztof.kozlowski+dt, robh+dt, conor+dt,
lvzhaoxiong, dri-devel, devicetree, linux-kernel
On Tue, Jul 2, 2024 at 3:02 PM Cong Yang
<yangcong5@huaqin.corp-partner.google.com> wrote:
> The Melfas lmfbx101117480 is a 10.1" WXGA TFT-LCD panel, use jd9365da
> controller, which fits in nicely with the existing panel-jadard-jd9365da-h3
> driver. Hence, we add a new compatible with panel specific config.
>
> Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
This is certainly OK
Acked-by: Linus Walleij <linus.walleij@linaro.org>
> +static int melfas_lmfbx101117480_init_cmds(struct jadard *jadard)
> +{
> + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
> +
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03);
> + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01);
Until this point *all* displays have the same init sequence, what about
a follow-up patch that start to break things that are always the
same into helper functions?
These sequences all have a lot of the same magic bytes, so if
you guys have a datasheet for this display controller then start
adding gradually some #defines for the e0, e1, e2 etc commands
please.
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v1 2/2] drm/panel: jd9365da: Support for Melfas lmfbx101117480 MIPI-DSI panel
2024-07-03 13:10 ` Linus Walleij
@ 2024-07-04 4:36 ` cong yang
0 siblings, 0 replies; 6+ messages in thread
From: cong yang @ 2024-07-04 4:36 UTC (permalink / raw)
To: Linus Walleij
Cc: sam, neil.armstrong, daniel, dianders, swboyd, airlied,
dmitry.baryshkov, krzysztof.kozlowski+dt, robh+dt, conor+dt,
lvzhaoxiong, dri-devel, devicetree, linux-kernel
Hi,
Linus Walleij <linus.walleij@linaro.org> 于2024年7月3日周三 21:10写道：
>
> On Tue, Jul 2, 2024 at 3:02 PM Cong Yang
> <yangcong5@huaqin.corp-partner.google.com> wrote:
>
> > The Melfas lmfbx101117480 is a 10.1" WXGA TFT-LCD panel, use jd9365da
> > controller, which fits in nicely with the existing panel-jadard-jd9365da-h3
> > driver. Hence, we add a new compatible with panel specific config.
> >
> > Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com>
>
> This is certainly OK
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> > +static int melfas_lmfbx101117480_init_cmds(struct jadard *jadard)
> > +{
> > + struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };
> > +
> > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x00);
> > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe1, 0x93);
> > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe2, 0x65);
> > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe3, 0xf8);
> > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x03);
> > + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0xe0, 0x01);
>
> Until this point *all* displays have the same init sequence, what about
> a follow-up patch that start to break things that are always the
> same into helper functions?
>
> These sequences all have a lot of the same magic bytes, so if
> you guys have a datasheet for this display controller then start
> adding gradually some #defines for the e0, e1, e2 etc commands
> please.
Okay, will add a patch in V2 series to fix it. Thanks.
>
> Yours,
> Linus Walleij
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2024-07-04 4:36 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-07-02 13:01 [PATCH v1 0/2] Support for Melfas lmfbx101117480 MIPI-DSI panel Cong Yang
2024-07-02 13:01 ` [PATCH v1 1/2] dt-bindings: display: panel: Add compatible for melfas lmfbx101117480 Cong Yang
2024-07-02 14:42 ` Conor Dooley
2024-07-02 13:01 ` [PATCH v1 2/2] drm/panel: jd9365da: Support for Melfas lmfbx101117480 MIPI-DSI panel Cong Yang
2024-07-03 13:10 ` Linus Walleij
2024-07-04 4:36 ` cong yang
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