* Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
2024-07-12 8:38 ` [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Yong-Xuan Wang
@ 2024-07-15 16:21 ` Conor Dooley
2024-07-18 16:45 ` Alexandre Ghiti
2024-07-18 23:38 ` Samuel Holland
2 siblings, 0 replies; 8+ messages in thread
From: Conor Dooley @ 2024-07-15 16:21 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: linux-kernel, linux-riscv, kvm-riscv, kvm, greentime.hu,
vincent.chen, Rob Herring, Krzysztof Kozlowski, Paul Walmsley,
Palmer Dabbelt, Albert Ou, devicetree
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On Fri, Jul 12, 2024 at 04:38:46PM +0800, Yong-Xuan Wang wrote:
> Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
> property.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
2024-07-12 8:38 ` [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Yong-Xuan Wang
2024-07-15 16:21 ` Conor Dooley
@ 2024-07-18 16:45 ` Alexandre Ghiti
2024-07-18 23:38 ` Samuel Holland
2 siblings, 0 replies; 8+ messages in thread
From: Alexandre Ghiti @ 2024-07-18 16:45 UTC (permalink / raw)
To: Yong-Xuan Wang, linux-kernel, linux-riscv, kvm-riscv, kvm
Cc: greentime.hu, vincent.chen, Conor Dooley, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
devicetree
On 12/07/2024 10:38, Yong-Xuan Wang wrote:
> Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
> property.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 468c646247aa..e91a6f4ede38 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -153,6 +153,34 @@ properties:
> ratified at commit 3f9ed34 ("Add ability to manually trigger
> workflow. (#2)") of riscv-time-compare.
>
> + - const: svade
> + description: |
> + The standard Svade supervisor-level extension for SW-managed PTE A/D
> + bit updates as ratified in the 20240213 version of the privileged
> + ISA specification.
> +
> + Both Svade and Svadu extensions control the hardware behavior when
> + the PTE A/D bits need to be set. The default behavior for the four
> + possible combinations of these extensions in the device tree are:
> + 1) Neither Svade nor Svadu present in DT => It is technically
> + unknown whether the platform uses Svade or Svadu. Supervisor
> + software should be prepared to handle either hardware updating
> + of the PTE A/D bits or page faults when they need updated.
> + 2) Only Svade present in DT => Supervisor must assume Svade to be
> + always enabled.
> + 3) Only Svadu present in DT => Supervisor must assume Svadu to be
> + always enabled.
> + 4) Both Svade and Svadu present in DT => Supervisor must assume
> + Svadu turned-off at boot time. To use Svadu, supervisor must
> + explicitly enable it using the SBI FWFT extension.
> +
> + - const: svadu
> + description: |
> + The standard Svadu supervisor-level extension for hardware updating
> + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request
> + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade
> + dt-binding description for more details.
> +
> - const: svinval
> description:
> The standard Svinval supervisor-level extension for fine-grained
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Thanks,
Alex
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
2024-07-12 8:38 ` [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries Yong-Xuan Wang
2024-07-15 16:21 ` Conor Dooley
2024-07-18 16:45 ` Alexandre Ghiti
@ 2024-07-18 23:38 ` Samuel Holland
2024-07-19 6:58 ` Yong-Xuan Wang
2 siblings, 1 reply; 8+ messages in thread
From: Samuel Holland @ 2024-07-18 23:38 UTC (permalink / raw)
To: Yong-Xuan Wang, Conor Dooley
Cc: greentime.hu, vincent.chen, Rob Herring, Krzysztof Kozlowski,
Paul Walmsley, Palmer Dabbelt, Albert Ou, devicetree,
linux-kernel, linux-riscv, kvm-riscv, kvm
On 2024-07-12 3:38 AM, Yong-Xuan Wang wrote:
> Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
> property.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> ---
> .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index 468c646247aa..e91a6f4ede38 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -153,6 +153,34 @@ properties:
> ratified at commit 3f9ed34 ("Add ability to manually trigger
> workflow. (#2)") of riscv-time-compare.
>
> + - const: svade
> + description: |
> + The standard Svade supervisor-level extension for SW-managed PTE A/D
> + bit updates as ratified in the 20240213 version of the privileged
> + ISA specification.
> +
> + Both Svade and Svadu extensions control the hardware behavior when
> + the PTE A/D bits need to be set. The default behavior for the four
> + possible combinations of these extensions in the device tree are:
> + 1) Neither Svade nor Svadu present in DT => It is technically
> + unknown whether the platform uses Svade or Svadu. Supervisor
> + software should be prepared to handle either hardware updating
> + of the PTE A/D bits or page faults when they need updated.
> + 2) Only Svade present in DT => Supervisor must assume Svade to be
> + always enabled.
> + 3) Only Svadu present in DT => Supervisor must assume Svadu to be
> + always enabled.
> + 4) Both Svade and Svadu present in DT => Supervisor must assume
> + Svadu turned-off at boot time. To use Svadu, supervisor must
> + explicitly enable it using the SBI FWFT extension.
> +
> + - const: svadu
> + description: |
> + The standard Svadu supervisor-level extension for hardware updating
> + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request
> + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade
Should we be referencing the archived riscv-svadu repository now that Svadu has
been merged to the main privileged ISA manual? Either way:
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> + dt-binding description for more details.
> +
> - const: svinval
> description:
> The standard Svinval supervisor-level extension for fine-grained
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
2024-07-18 23:38 ` Samuel Holland
@ 2024-07-19 6:58 ` Yong-Xuan Wang
2024-07-19 13:17 ` Conor Dooley
0 siblings, 1 reply; 8+ messages in thread
From: Yong-Xuan Wang @ 2024-07-19 6:58 UTC (permalink / raw)
To: Samuel Holland
Cc: Conor Dooley, greentime.hu, vincent.chen, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
devicetree, linux-kernel, linux-riscv, kvm-riscv, kvm
Hi Samuel,
On Fri, Jul 19, 2024 at 7:38 AM Samuel Holland
<samuel.holland@sifive.com> wrote:
>
> On 2024-07-12 3:38 AM, Yong-Xuan Wang wrote:
> > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
> > property.
> >
> > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> > ---
> > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
> > 1 file changed, 28 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index 468c646247aa..e91a6f4ede38 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -153,6 +153,34 @@ properties:
> > ratified at commit 3f9ed34 ("Add ability to manually trigger
> > workflow. (#2)") of riscv-time-compare.
> >
> > + - const: svade
> > + description: |
> > + The standard Svade supervisor-level extension for SW-managed PTE A/D
> > + bit updates as ratified in the 20240213 version of the privileged
> > + ISA specification.
> > +
> > + Both Svade and Svadu extensions control the hardware behavior when
> > + the PTE A/D bits need to be set. The default behavior for the four
> > + possible combinations of these extensions in the device tree are:
> > + 1) Neither Svade nor Svadu present in DT => It is technically
> > + unknown whether the platform uses Svade or Svadu. Supervisor
> > + software should be prepared to handle either hardware updating
> > + of the PTE A/D bits or page faults when they need updated.
> > + 2) Only Svade present in DT => Supervisor must assume Svade to be
> > + always enabled.
> > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be
> > + always enabled.
> > + 4) Both Svade and Svadu present in DT => Supervisor must assume
> > + Svadu turned-off at boot time. To use Svadu, supervisor must
> > + explicitly enable it using the SBI FWFT extension.
> > +
> > + - const: svadu
> > + description: |
> > + The standard Svadu supervisor-level extension for hardware updating
> > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request
> > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade
>
> Should we be referencing the archived riscv-svadu repository now that Svadu has
> been merged to the main privileged ISA manual? Either way:
>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
>
Yes, this commit is from the archived riscv-svadu repo. Or should I update it to
"commit c1abccf ("Merge pull request #25 from ved-rivos/ratified") of
riscvarchive/riscv-svadu."?
Regards,
Yong-Xuan
> > + dt-binding description for more details.
> > +
> > - const: svinval
> > description:
> > The standard Svinval supervisor-level extension for fine-grained
>
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
2024-07-19 6:58 ` Yong-Xuan Wang
@ 2024-07-19 13:17 ` Conor Dooley
2024-07-22 2:14 ` Yong-Xuan Wang
0 siblings, 1 reply; 8+ messages in thread
From: Conor Dooley @ 2024-07-19 13:17 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: Samuel Holland, greentime.hu, vincent.chen, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
devicetree, linux-kernel, linux-riscv, kvm-riscv, kvm
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On Fri, Jul 19, 2024 at 02:58:59PM +0800, Yong-Xuan Wang wrote:
> Hi Samuel,
>
> On Fri, Jul 19, 2024 at 7:38 AM Samuel Holland
> <samuel.holland@sifive.com> wrote:
> >
> > On 2024-07-12 3:38 AM, Yong-Xuan Wang wrote:
> > > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
> > > property.
> > >
> > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> > > ---
> > > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
> > > 1 file changed, 28 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > index 468c646247aa..e91a6f4ede38 100644
> > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > @@ -153,6 +153,34 @@ properties:
> > > ratified at commit 3f9ed34 ("Add ability to manually trigger
> > > workflow. (#2)") of riscv-time-compare.
> > >
> > > + - const: svade
> > > + description: |
> > > + The standard Svade supervisor-level extension for SW-managed PTE A/D
> > > + bit updates as ratified in the 20240213 version of the privileged
> > > + ISA specification.
> > > +
> > > + Both Svade and Svadu extensions control the hardware behavior when
> > > + the PTE A/D bits need to be set. The default behavior for the four
> > > + possible combinations of these extensions in the device tree are:
> > > + 1) Neither Svade nor Svadu present in DT => It is technically
> > > + unknown whether the platform uses Svade or Svadu. Supervisor
> > > + software should be prepared to handle either hardware updating
> > > + of the PTE A/D bits or page faults when they need updated.
> > > + 2) Only Svade present in DT => Supervisor must assume Svade to be
> > > + always enabled.
> > > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be
> > > + always enabled.
> > > + 4) Both Svade and Svadu present in DT => Supervisor must assume
> > > + Svadu turned-off at boot time. To use Svadu, supervisor must
> > > + explicitly enable it using the SBI FWFT extension.
> > > +
> > > + - const: svadu
> > > + description: |
> > > + The standard Svadu supervisor-level extension for hardware updating
> > > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request
> > > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade
> >
> > Should we be referencing the archived riscv-svadu repository now that Svadu has
> > been merged to the main privileged ISA manual? Either way:
> >
> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> >
>
> Yes, this commit is from the archived riscv-svadu repo. Or should I update it to
> "commit c1abccf ("Merge pull request #25 from ved-rivos/ratified") of
> riscvarchive/riscv-svadu."?
I think Samuel was saying that we should use the commit where it was
merged into riscv-isa-manual instead.
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^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
2024-07-19 13:17 ` Conor Dooley
@ 2024-07-22 2:14 ` Yong-Xuan Wang
2024-07-22 16:51 ` Conor Dooley
0 siblings, 1 reply; 8+ messages in thread
From: Yong-Xuan Wang @ 2024-07-22 2:14 UTC (permalink / raw)
To: Conor Dooley
Cc: Samuel Holland, greentime.hu, vincent.chen, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
devicetree, linux-kernel, linux-riscv, kvm-riscv, kvm
Hi Conor,
On Fri, Jul 19, 2024 at 9:17 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Jul 19, 2024 at 02:58:59PM +0800, Yong-Xuan Wang wrote:
> > Hi Samuel,
> >
> > On Fri, Jul 19, 2024 at 7:38 AM Samuel Holland
> > <samuel.holland@sifive.com> wrote:
> > >
> > > On 2024-07-12 3:38 AM, Yong-Xuan Wang wrote:
> > > > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions
> > > > property.
> > > >
> > > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> > > > ---
> > > > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++
> > > > 1 file changed, 28 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > index 468c646247aa..e91a6f4ede38 100644
> > > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > > > @@ -153,6 +153,34 @@ properties:
> > > > ratified at commit 3f9ed34 ("Add ability to manually trigger
> > > > workflow. (#2)") of riscv-time-compare.
> > > >
> > > > + - const: svade
> > > > + description: |
> > > > + The standard Svade supervisor-level extension for SW-managed PTE A/D
> > > > + bit updates as ratified in the 20240213 version of the privileged
> > > > + ISA specification.
> > > > +
> > > > + Both Svade and Svadu extensions control the hardware behavior when
> > > > + the PTE A/D bits need to be set. The default behavior for the four
> > > > + possible combinations of these extensions in the device tree are:
> > > > + 1) Neither Svade nor Svadu present in DT => It is technically
> > > > + unknown whether the platform uses Svade or Svadu. Supervisor
> > > > + software should be prepared to handle either hardware updating
> > > > + of the PTE A/D bits or page faults when they need updated.
> > > > + 2) Only Svade present in DT => Supervisor must assume Svade to be
> > > > + always enabled.
> > > > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be
> > > > + always enabled.
> > > > + 4) Both Svade and Svadu present in DT => Supervisor must assume
> > > > + Svadu turned-off at boot time. To use Svadu, supervisor must
> > > > + explicitly enable it using the SBI FWFT extension.
> > > > +
> > > > + - const: svadu
> > > > + description: |
> > > > + The standard Svadu supervisor-level extension for hardware updating
> > > > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request
> > > > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade
> > >
> > > Should we be referencing the archived riscv-svadu repository now that Svadu has
> > > been merged to the main privileged ISA manual? Either way:
> > >
> > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> > >
> >
> > Yes, this commit is from the archived riscv-svadu repo. Or should I update it to
> > "commit c1abccf ("Merge pull request #25 from ved-rivos/ratified") of
> > riscvarchive/riscv-svadu."?
>
> I think Samuel was saying that we should use the commit where it was
> merged into riscv-isa-manual instead.
Got it. I will update the description in the next version. Thank you!
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH v7 2/4] dt-bindings: riscv: Add Svade and Svadu Entries
2024-07-22 2:14 ` Yong-Xuan Wang
@ 2024-07-22 16:51 ` Conor Dooley
0 siblings, 0 replies; 8+ messages in thread
From: Conor Dooley @ 2024-07-22 16:51 UTC (permalink / raw)
To: Yong-Xuan Wang
Cc: Samuel Holland, greentime.hu, vincent.chen, Rob Herring,
Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou,
devicetree, linux-kernel, linux-riscv, kvm-riscv, kvm
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On Mon, Jul 22, 2024 at 10:14:11AM +0800, Yong-Xuan Wang wrote:
> > > > > + - const: svadu
> > > > > + description: |
> > > > > + The standard Svadu supervisor-level extension for hardware updating
> > > > > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request
> > > > > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade
> > > >
> > > > Should we be referencing the archived riscv-svadu repository now that Svadu has
> > > > been merged to the main privileged ISA manual? Either way:
> > > >
> > > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> > > >
> > >
> > > Yes, this commit is from the archived riscv-svadu repo. Or should I update it to
> > > "commit c1abccf ("Merge pull request #25 from ved-rivos/ratified") of
> > > riscvarchive/riscv-svadu."?
> >
> > I think Samuel was saying that we should use the commit where it was
> > merged into riscv-isa-manual instead.
>
> Got it. I will update the description in the next version. Thank you!
There's no need (IMO) to send a new version for this alone - but if you
have to send another version for some other reason then do it.
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 8+ messages in thread