* [PATCH v2 0/2] Make i.MX9 OCOTP work as accessing controller
@ 2024-12-17 8:43 Peng Fan (OSS)
2024-12-17 8:43 ` [PATCH v2 1/2] dt-bindings: nvmem: imx-ocotp: Introduce #access-controller-cells Peng Fan (OSS)
2024-12-17 8:43 ` [PATCH v2 2/2] nvmem: imx-ocotp-ele: Support accessing controller for i.MX9 Peng Fan (OSS)
0 siblings, 2 replies; 5+ messages in thread
From: Peng Fan (OSS) @ 2024-12-17 8:43 UTC (permalink / raw)
To: Srinivas Kandagatla, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan,
Frank Li
Previously there was discussion on using "feature-controller" or
adding a specific node to group the fuse information for U-Boot to
parse and update node. But rejected by DT maintainer(Rob).
Since the STM32 engineers added access controller concept and landed
the support in Linux Kernel, reuse the concept for i.MX.
i.MX OCOTP eFuse has some bits to indicate a specific periphral or
function is avaiable for current chip, for example i.MX93 has variants
that not have NPU. So introduce '#access-controller-cells' for OCOTP,
and add "#access-controllers = <&ocotp [gate_index]>" for periphrals
that needs accessing control checking.
In OCOTP driver, the nodes under "/" will be iterated, and checked
if property "#access-controllers" exsits. If not allow access, detach
the node.
In the end, cpu nodes should still be handled by bootloader.
And I may also update i.MX8M to use same method to support variants
if this patchset is good.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Changes in v2:
- Add R-b for patch 1
- Use '/' root node instead of '/soc' or '/soc@0' for patch 2
- Link to v1: https://lore.kernel.org/r/20241212-imx-ocotp-v1-0-198bb0af86a0@nxp.com
---
Peng Fan (2):
dt-bindings: nvmem: imx-ocotp: Introduce #access-controller-cells
nvmem: imx-ocotp-ele: Support accessing controller for i.MX9
.../devicetree/bindings/nvmem/imx-ocotp.yaml | 5 +
drivers/nvmem/imx-ocotp-ele.c | 184 ++++++++++++++++++++-
include/dt-bindings/nvmem/fsl,imx93-ocotp.h | 24 +++
include/dt-bindings/nvmem/fsl,imx95-ocotp.h | 43 +++++
4 files changed, 255 insertions(+), 1 deletion(-)
---
base-commit: d49bc7ced87506bedbcce1ca7782ff942b309f2d
change-id: 20241212-imx-ocotp-cbef304140f5
Best regards,
--
Peng Fan <peng.fan@nxp.com>
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v2 1/2] dt-bindings: nvmem: imx-ocotp: Introduce #access-controller-cells 2024-12-17 8:43 [PATCH v2 0/2] Make i.MX9 OCOTP work as accessing controller Peng Fan (OSS) @ 2024-12-17 8:43 ` Peng Fan (OSS) 2024-12-17 18:20 ` Conor Dooley 2024-12-17 8:43 ` [PATCH v2 2/2] nvmem: imx-ocotp-ele: Support accessing controller for i.MX9 Peng Fan (OSS) 1 sibling, 1 reply; 5+ messages in thread From: Peng Fan (OSS) @ 2024-12-17 8:43 UTC (permalink / raw) To: Srinivas Kandagatla, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan, Frank Li From: Peng Fan <peng.fan@nxp.com> Introduce "#access-controller-cells" to make OCOTP be an accessing controller, because i.MX Family OCOTP supports a specific peripheral or function being fused which means being disabled. Add the i.MX[95,93] OCOTP gate index. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> --- .../devicetree/bindings/nvmem/imx-ocotp.yaml | 5 +++ include/dt-bindings/nvmem/fsl,imx93-ocotp.h | 24 ++++++++++++ include/dt-bindings/nvmem/fsl,imx95-ocotp.h | 43 ++++++++++++++++++++++ 3 files changed, 72 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml index b2cb76cf9053a883a158acaf5eaa108895818afc..c78e202ced22f1c278f7be827b71ba434832d2a7 100644 --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.yaml @@ -54,6 +54,11 @@ properties: clocks: maxItems: 1 + "#access-controller-cells": + const: 1 + description: + Contains the gate ID associated to the peripheral. + required: - "#address-cells" - "#size-cells" diff --git a/include/dt-bindings/nvmem/fsl,imx93-ocotp.h b/include/dt-bindings/nvmem/fsl,imx93-ocotp.h new file mode 100644 index 0000000000000000000000000000000000000000..6ef525173845fd4ee0e847cf5a17e53a14f71362 --- /dev/null +++ b/include/dt-bindings/nvmem/fsl,imx93-ocotp.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef _DT_BINDINGS_NVMEM_IMX93_OTPC_H +#define _DT_BINDINGS_NVMEM_IMX93_OTPC_H + +#define IMX93_OCOTP_NPU_GATE 0 +#define IMX93_OCOTP_A550_GATE 1 +#define IMX93_OCOTP_A551_GATE 2 +#define IMX93_OCOTP_M33_GATE 3 +#define IMX93_OCOTP_CAN1_FD_GATE 4 +#define IMX93_OCOTP_CAN2_FD_GATE 5 +#define IMX93_OCOTP_CAN1_GATE 6 +#define IMX93_OCOTP_CAN2_GATE 7 +#define IMX93_OCOTP_USB1_GATE 8 +#define IMX93_OCOTP_USB2_GATE 9 +#define IMX93_OCOTP_ENET1_GATE 10 +#define IMX93_OCOTP_ENET2_GATE 11 +#define IMX93_OCOTP_PXP_GATE 12 +#define IMX93_OCOTP_MIPI_CSI1_GATE 13 +#define IMX93_OCOTP_MIPI_DSI1_GATE 14 +#define IMX93_OCOTP_LVDS1_GATE 15 +#define IMX93_OCOTP_ADC1_GATE 16 + +#endif diff --git a/include/dt-bindings/nvmem/fsl,imx95-ocotp.h b/include/dt-bindings/nvmem/fsl,imx95-ocotp.h new file mode 100644 index 0000000000000000000000000000000000000000..2d21d1f690974d0215c71352168378a150f489af --- /dev/null +++ b/include/dt-bindings/nvmem/fsl,imx95-ocotp.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef _DT_BINDINGS_NVMEM_IMX95_OTPC_H +#define _DT_BINDINGS_NVMEM_IMX95_OTPC_H + +#define IMX95_OCOTP_CANFD1_GATE 0 +#define IMX95_OCOTP_CANFD2_GATE 1 +#define IMX95_OCOTP_CANFD3_GATE 2 +#define IMX95_OCOTP_CANFD4_GATE 3 +#define IMX95_OCOTP_CANFD5_GATE 4 +#define IMX95_OCOTP_CAN1_GATE 5 +#define IMX95_OCOTP_CAN2_GATE 6 +#define IMX95_OCOTP_CAN3_GATE 7 +#define IMX95_OCOTP_CAN4_GATE 8 +#define IMX95_OCOTP_CAN5_GATE 9 +#define IMX95_OCOTP_NPU_GATE 10 +#define IMX95_OCOTP_A550_GATE 11 +#define IMX95_OCOTP_A551_GATE 12 +#define IMX95_OCOTP_A552_GATE 13 +#define IMX95_OCOTP_A553_GATE 14 +#define IMX95_OCOTP_A554_GATE 15 +#define IMX95_OCOTP_A555_GATE 16 +#define IMX95_OCOTP_M7_GATE 17 +#define IMX95_OCOTP_DCSS_GATE 18 +#define IMX95_OCOTP_LVDS1_GATE 19 +#define IMX95_OCOTP_ISP_GATE 20 +#define IMX95_OCOTP_USB1_GATE 21 +#define IMX95_OCOTP_USB2_GATE 22 +#define IMX95_OCOTP_NETC_GATE 23 +#define IMX95_OCOTP_PCIE1_GATE 24 +#define IMX95_OCOTP_PCIE2_GATE 25 +#define IMX95_OCOTP_ADC1_GATE 26 +#define IMX95_OCOTP_EARC_RX_GATE 27 +#define IMX95_OCOTP_GPU3D_GATE 28 +#define IMX95_OCOTP_VPU_GATE 29 +#define IMX95_OCOTP_JPEG_ENC_GATE 30 +#define IMX95_OCOTP_JPEG_DEC_GATE 31 +#define IMX95_OCOTP_MIPI_CSI1_GATE 32 +#define IMX95_OCOTP_MIPI_CSI2_GATE 33 +#define IMX95_OCOTP_MIPI_DSI1_GATE 34 +#define IMX95_OCOTP_V2X_GATE 35 + +#endif -- 2.37.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: nvmem: imx-ocotp: Introduce #access-controller-cells 2024-12-17 8:43 ` [PATCH v2 1/2] dt-bindings: nvmem: imx-ocotp: Introduce #access-controller-cells Peng Fan (OSS) @ 2024-12-17 18:20 ` Conor Dooley 0 siblings, 0 replies; 5+ messages in thread From: Conor Dooley @ 2024-12-17 18:20 UTC (permalink / raw) To: Peng Fan (OSS) Cc: Srinivas Kandagatla, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan, Frank Li [-- Attachment #1: Type: text/plain, Size: 497 bytes --] On Tue, Dec 17, 2024 at 04:43:36PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > Introduce "#access-controller-cells" to make OCOTP be an accessing > controller, because i.MX Family OCOTP supports a specific peripheral > or function being fused which means being disabled. > > Add the i.MX[95,93] OCOTP gate index. > > Reviewed-by: Frank Li <Frank.Li@nxp.com> > Signed-off-by: Peng Fan <peng.fan@nxp.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] nvmem: imx-ocotp-ele: Support accessing controller for i.MX9 2024-12-17 8:43 [PATCH v2 0/2] Make i.MX9 OCOTP work as accessing controller Peng Fan (OSS) 2024-12-17 8:43 ` [PATCH v2 1/2] dt-bindings: nvmem: imx-ocotp: Introduce #access-controller-cells Peng Fan (OSS) @ 2024-12-17 8:43 ` Peng Fan (OSS) 2024-12-17 16:02 ` Frank Li 1 sibling, 1 reply; 5+ messages in thread From: Peng Fan (OSS) @ 2024-12-17 8:43 UTC (permalink / raw) To: Srinivas Kandagatla, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam Cc: devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan From: Peng Fan <peng.fan@nxp.com> i.MX9 OCOTP supports a specific peripheral or function being fused which means disabled, so - Introduce ocotp_access_gates to be container of efuse gate info - Iterate each node under '/soc' to check accessing permission. If not allowed to be accessed, detach the node Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/nvmem/imx-ocotp-ele.c | 184 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 183 insertions(+), 1 deletion(-) diff --git a/drivers/nvmem/imx-ocotp-ele.c b/drivers/nvmem/imx-ocotp-ele.c index ca6dd71d8a2e29888c6e556aaea116c1a967cb5f..2c7b698ae4da0ec22eeeabf4ed35d1b703771f6c 100644 --- a/drivers/nvmem/imx-ocotp-ele.c +++ b/drivers/nvmem/imx-ocotp-ele.c @@ -5,6 +5,8 @@ * Copyright 2023 NXP */ +#include <dt-bindings/nvmem/fsl,imx93-ocotp.h> +#include <dt-bindings/nvmem/fsl,imx95-ocotp.h> #include <linux/device.h> #include <linux/io.h> #include <linux/module.h> @@ -27,6 +29,7 @@ struct ocotp_map_entry { }; struct ocotp_devtype_data { + const struct ocotp_access_gates *access_gates; u32 reg_off; char *name; u32 size; @@ -36,11 +39,26 @@ struct ocotp_devtype_data { struct ocotp_map_entry entry[]; }; +#define OCOTP_MAX_NUM_GATE_WORDS 4 +#define IMX93_OCOTP_NUM_GATES 17 +#define IMX95_OCOTP_NUM_GATES 36 + +struct ocotp_access_gates { + u32 num_words; + u32 words[OCOTP_MAX_NUM_GATE_WORDS]; + u32 num_gates; + struct access_gate { + u32 word; + u32 mask; + } gates[]; +}; + struct imx_ocotp_priv { struct device *dev; void __iomem *base; struct nvmem_config config; struct mutex lock; + u32 value[OCOTP_MAX_NUM_GATE_WORDS]; const struct ocotp_devtype_data *data; }; @@ -131,6 +149,97 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem, cell->read_post_process = imx_ocotp_cell_pp; } +static int imx_ele_ocotp_check_access(struct platform_device *pdev, u32 id) +{ + struct imx_ocotp_priv *priv = platform_get_drvdata(pdev); + const struct ocotp_access_gates *access_gates = priv->data->access_gates; + u32 word, mask; + + if (id >= access_gates->num_gates) { + dev_err(&pdev->dev, "Index %d too large\n", id); + return -EACCES; + } + + word = access_gates->gates[id].word; + mask = access_gates->gates[id].mask; + + dev_dbg(&pdev->dev, "id:%d word:%d mask:0x%08x\n", id, word, mask); + /* true means not allow access */ + if (priv->value[word] & mask) + return -EACCES; + + return 0; +} + +static int imx_ele_ocotp_grant_access(struct platform_device *pdev, struct device_node *parent) +{ + struct device_node *child; + struct device *dev = &pdev->dev; + + for_each_available_child_of_node(parent, child) { + struct of_phandle_iterator it; + int err; + u32 id; + + of_for_each_phandle(&it, err, child, "access-controllers", + "#access-controller-cells", 0) { + struct of_phandle_args provider_args; + struct device_node *provider = it.node; + + if (err) { + dev_err(dev, "Unable to get access-controllers property for node %s\n, err: %d", + child->full_name, err); + of_node_put(provider); + return err; + } + + /* Only support one cell */ + if (of_phandle_iterator_args(&it, provider_args.args, 1) != 1) { + dev_err(dev, "wrong args count\n"); + return -EINVAL; + } + + id = provider_args.args[0]; + + dev_dbg(dev, "Checking node: %s gate: %d\n", child->full_name, id); + + if (imx_ele_ocotp_check_access(pdev, id)) { + of_detach_node(child); + dev_err(dev, "%s: Not granted, device driver will not be probed\n", + child->full_name); + } + } + + imx_ele_ocotp_grant_access(pdev, child); + } + + return 0; +} + +static int imx_ele_ocotp_access_control(struct platform_device *pdev) +{ + struct imx_ocotp_priv *priv = platform_get_drvdata(pdev); + struct device_node *root __free(device_node) = of_find_node_by_path("/"); + const struct ocotp_access_gates *access_gates = priv->data->access_gates; + void __iomem *reg = priv->base + priv->data->reg_off; + u32 off; + int i; + + if (!priv->data->access_gates) + return 0; + + /* This should never happen */ + WARN_ON(!root); + + for (i = 0; i < access_gates->num_words; i++) { + off = access_gates->words[i] << 2; + priv->value[i] = readl(reg + off); + dev_dbg(&pdev->dev, "word:%d 0x%08x\n", access_gates->words[i], priv->value[i]); + } + + return imx_ele_ocotp_grant_access(pdev, root); +} + static int imx_ele_ocotp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -161,14 +270,43 @@ static int imx_ele_ocotp_probe(struct platform_device *pdev) priv->config.fixup_dt_cell_info = imx_ocotp_fixup_dt_cell_info; mutex_init(&priv->lock); + platform_set_drvdata(pdev, priv); + nvmem = devm_nvmem_register(dev, &priv->config); if (IS_ERR(nvmem)) return PTR_ERR(nvmem); - return 0; + + return imx_ele_ocotp_access_control(pdev); } +static const struct ocotp_access_gates imx93_access_gates = { + .num_words = 3, + .words = {19, 20, 21}, + .num_gates = IMX93_OCOTP_NUM_GATES, + .gates = { + [IMX93_OCOTP_NPU_GATE] = { .word = 19, .mask = BIT(13) }, + [IMX93_OCOTP_A550_GATE] = { .word = 19, .mask = BIT(14) }, + [IMX93_OCOTP_A551_GATE] = { .word = 19, .mask = BIT(15) }, + [IMX93_OCOTP_M33_GATE] = { .word = 19, .mask = BIT(24) }, + [IMX93_OCOTP_CAN1_FD_GATE] = { .word = 19, .mask = BIT(28) }, + [IMX93_OCOTP_CAN2_FD_GATE] = { .word = 19, .mask = BIT(29) }, + [IMX93_OCOTP_CAN1_GATE] = { .word = 19, .mask = BIT(30) }, + [IMX93_OCOTP_CAN2_GATE] = { .word = 19, .mask = BIT(31) }, + [IMX93_OCOTP_USB1_GATE] = { .word = 20, .mask = BIT(3) }, + [IMX93_OCOTP_USB2_GATE] = { .word = 20, .mask = BIT(4) }, + [IMX93_OCOTP_ENET1_GATE] = { .word = 20, .mask = BIT(5) }, + [IMX93_OCOTP_ENET2_GATE] = { .word = 20, .mask = BIT(6) }, + [IMX93_OCOTP_PXP_GATE] = { .word = 20, .mask = BIT(10) }, + [IMX93_OCOTP_MIPI_CSI1_GATE] = { .word = 20, .mask = BIT(17) }, + [IMX93_OCOTP_MIPI_DSI1_GATE] = { .word = 20, .mask = BIT(19) }, + [IMX93_OCOTP_LVDS1_GATE] = { .word = 20, .mask = BIT(24) }, + [IMX93_OCOTP_ADC1_GATE] = { .word = 21, .mask = BIT(7) }, + }, +}; + static const struct ocotp_devtype_data imx93_ocotp_data = { + .access_gates = &imx93_access_gates, .reg_off = 0x8000, .reg_read = imx_ocotp_reg_read, .size = 2048, @@ -183,7 +321,51 @@ static const struct ocotp_devtype_data imx93_ocotp_data = { }, }; +static const struct ocotp_access_gates imx95_access_gates = { + .num_words = 3, + .words = {17, 18, 19}, + .num_gates = IMX95_OCOTP_NUM_GATES, + .gates = { + [IMX95_OCOTP_CANFD1_GATE] = { .word = 17, .mask = BIT(20) }, + [IMX95_OCOTP_CANFD2_GATE] = { .word = 17, .mask = BIT(21) }, + [IMX95_OCOTP_CANFD3_GATE] = { .word = 17, .mask = BIT(22) }, + [IMX95_OCOTP_CANFD4_GATE] = { .word = 17, .mask = BIT(23) }, + [IMX95_OCOTP_CANFD5_GATE] = { .word = 17, .mask = BIT(24) }, + [IMX95_OCOTP_CAN1_GATE] = { .word = 17, .mask = BIT(25) }, + [IMX95_OCOTP_CAN2_GATE] = { .word = 17, .mask = BIT(26) }, + [IMX95_OCOTP_CAN3_GATE] = { .word = 17, .mask = BIT(27) }, + [IMX95_OCOTP_CAN4_GATE] = { .word = 17, .mask = BIT(28) }, + [IMX95_OCOTP_CAN5_GATE] = { .word = 17, .mask = BIT(29) }, + [IMX95_OCOTP_NPU_GATE] = { .word = 18, .mask = BIT(0) }, + [IMX95_OCOTP_A550_GATE] = { .word = 18, .mask = BIT(1) }, + [IMX95_OCOTP_A551_GATE] = { .word = 18, .mask = BIT(2) }, + [IMX95_OCOTP_A552_GATE] = { .word = 18, .mask = BIT(3) }, + [IMX95_OCOTP_A553_GATE] = { .word = 18, .mask = BIT(4) }, + [IMX95_OCOTP_A554_GATE] = { .word = 18, .mask = BIT(5) }, + [IMX95_OCOTP_A555_GATE] = { .word = 18, .mask = BIT(6) }, + [IMX95_OCOTP_M7_GATE] = { .word = 18, .mask = BIT(9) }, + [IMX95_OCOTP_DCSS_GATE] = { .word = 18, .mask = BIT(22) }, + [IMX95_OCOTP_LVDS1_GATE] = { .word = 18, .mask = BIT(27) }, + [IMX95_OCOTP_ISP_GATE] = { .word = 18, .mask = BIT(29) }, + [IMX95_OCOTP_USB1_GATE] = { .word = 19, .mask = BIT(2) }, + [IMX95_OCOTP_USB2_GATE] = { .word = 19, .mask = BIT(3) }, + [IMX95_OCOTP_NETC_GATE] = { .word = 19, .mask = BIT(4) }, + [IMX95_OCOTP_PCIE1_GATE] = { .word = 19, .mask = BIT(6) }, + [IMX95_OCOTP_PCIE2_GATE] = { .word = 19, .mask = BIT(7) }, + [IMX95_OCOTP_ADC1_GATE] = { .word = 19, .mask = BIT(8) }, + [IMX95_OCOTP_EARC_RX_GATE] = { .word = 19, .mask = BIT(11) }, + [IMX95_OCOTP_GPU3D_GATE] = { .word = 19, .mask = BIT(16) }, + [IMX95_OCOTP_VPU_GATE] = { .word = 19, .mask = BIT(17) }, + [IMX95_OCOTP_JPEG_ENC_GATE] = { .word = 19, .mask = BIT(18) }, + [IMX95_OCOTP_JPEG_DEC_GATE] = { .word = 19, .mask = BIT(19) }, + [IMX95_OCOTP_MIPI_CSI1_GATE] = { .word = 19, .mask = BIT(21) }, + [IMX95_OCOTP_MIPI_CSI2_GATE] = { .word = 19, .mask = BIT(22) }, + [IMX95_OCOTP_MIPI_DSI1_GATE] = { .word = 19, .mask = BIT(23) }, + } +}; + static const struct ocotp_devtype_data imx95_ocotp_data = { + .access_gates = &imx95_access_gates, .reg_off = 0x8000, .reg_read = imx_ocotp_reg_read, .size = 2048, -- 2.37.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 2/2] nvmem: imx-ocotp-ele: Support accessing controller for i.MX9 2024-12-17 8:43 ` [PATCH v2 2/2] nvmem: imx-ocotp-ele: Support accessing controller for i.MX9 Peng Fan (OSS) @ 2024-12-17 16:02 ` Frank Li 0 siblings, 0 replies; 5+ messages in thread From: Frank Li @ 2024-12-17 16:02 UTC (permalink / raw) To: Peng Fan (OSS) Cc: Srinivas Kandagatla, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, devicetree, imx, linux-arm-kernel, linux-kernel, Peng Fan On Tue, Dec 17, 2024 at 04:43:37PM +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > i.MX9 OCOTP supports a specific peripheral or function being fused > which means disabled, so > - Introduce ocotp_access_gates to be container of efuse gate info > - Iterate each node under '/soc' to check accessing permission. If not > allowed to be accessed, detach the node > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/nvmem/imx-ocotp-ele.c | 184 +++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 183 insertions(+), 1 deletion(-) > > diff --git a/drivers/nvmem/imx-ocotp-ele.c b/drivers/nvmem/imx-ocotp-ele.c > index ca6dd71d8a2e29888c6e556aaea116c1a967cb5f..2c7b698ae4da0ec22eeeabf4ed35d1b703771f6c 100644 > --- a/drivers/nvmem/imx-ocotp-ele.c > +++ b/drivers/nvmem/imx-ocotp-ele.c > @@ -5,6 +5,8 @@ > * Copyright 2023 NXP > */ > > +#include <dt-bindings/nvmem/fsl,imx93-ocotp.h> > +#include <dt-bindings/nvmem/fsl,imx95-ocotp.h> > #include <linux/device.h> > #include <linux/io.h> > #include <linux/module.h> > @@ -27,6 +29,7 @@ struct ocotp_map_entry { > }; > > struct ocotp_devtype_data { > + const struct ocotp_access_gates *access_gates; > u32 reg_off; > char *name; > u32 size; > @@ -36,11 +39,26 @@ struct ocotp_devtype_data { > struct ocotp_map_entry entry[]; > }; > > +#define OCOTP_MAX_NUM_GATE_WORDS 4 > +#define IMX93_OCOTP_NUM_GATES 17 > +#define IMX95_OCOTP_NUM_GATES 36 > + > +struct ocotp_access_gates { > + u32 num_words; > + u32 words[OCOTP_MAX_NUM_GATE_WORDS]; > + u32 num_gates; > + struct access_gate { > + u32 word; > + u32 mask; > + } gates[]; > +}; > + > struct imx_ocotp_priv { > struct device *dev; > void __iomem *base; > struct nvmem_config config; > struct mutex lock; > + u32 value[OCOTP_MAX_NUM_GATE_WORDS]; > const struct ocotp_devtype_data *data; > }; > > @@ -131,6 +149,97 @@ static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem, > cell->read_post_process = imx_ocotp_cell_pp; > } > > +static int imx_ele_ocotp_check_access(struct platform_device *pdev, u32 id) > +{ > + struct imx_ocotp_priv *priv = platform_get_drvdata(pdev); > + const struct ocotp_access_gates *access_gates = priv->data->access_gates; > + u32 word, mask; > + > + if (id >= access_gates->num_gates) { > + dev_err(&pdev->dev, "Index %d too large\n", id); > + return -EACCES; > + } > + > + word = access_gates->gates[id].word; > + mask = access_gates->gates[id].mask; > + > + dev_dbg(&pdev->dev, "id:%d word:%d mask:0x%08x\n", id, word, mask); > + /* true means not allow access */ > + if (priv->value[word] & mask) > + return -EACCES; > + > + return 0; > +} > + > +static int imx_ele_ocotp_grant_access(struct platform_device *pdev, struct device_node *parent) > +{ > + struct device_node *child; > + struct device *dev = &pdev->dev; move 'dev' before child. > + > + for_each_available_child_of_node(parent, child) { for_each_child_of_node_scoped() ? I am not sure if you need of_node_put for child node. Frank > + struct of_phandle_iterator it; > + int err; > + u32 id; > + > + of_for_each_phandle(&it, err, child, "access-controllers", > + "#access-controller-cells", 0) { > + struct of_phandle_args provider_args; > + struct device_node *provider = it.node; > + > + if (err) { > + dev_err(dev, "Unable to get access-controllers property for node %s\n, err: %d", > + child->full_name, err); > + of_node_put(provider); > + return err; > + } > + > + /* Only support one cell */ > + if (of_phandle_iterator_args(&it, provider_args.args, 1) != 1) { > + dev_err(dev, "wrong args count\n"); > + return -EINVAL; > + } > + > + id = provider_args.args[0]; > + > + dev_dbg(dev, "Checking node: %s gate: %d\n", child->full_name, id); > + > + if (imx_ele_ocotp_check_access(pdev, id)) { > + of_detach_node(child); > + dev_err(dev, "%s: Not granted, device driver will not be probed\n", > + child->full_name); > + } > + } > + > + imx_ele_ocotp_grant_access(pdev, child); > + } > + > + return 0; > +} > + > +static int imx_ele_ocotp_access_control(struct platform_device *pdev) > +{ > + struct imx_ocotp_priv *priv = platform_get_drvdata(pdev); > + struct device_node *root __free(device_node) = of_find_node_by_path("/"); > + const struct ocotp_access_gates *access_gates = priv->data->access_gates; > + void __iomem *reg = priv->base + priv->data->reg_off; > + u32 off; > + int i; > + > + if (!priv->data->access_gates) > + return 0; > + > + /* This should never happen */ > + WARN_ON(!root); > + > + for (i = 0; i < access_gates->num_words; i++) { > + off = access_gates->words[i] << 2; > + priv->value[i] = readl(reg + off); > + dev_dbg(&pdev->dev, "word:%d 0x%08x\n", access_gates->words[i], priv->value[i]); > + } > + > + return imx_ele_ocotp_grant_access(pdev, root); > +} > + > static int imx_ele_ocotp_probe(struct platform_device *pdev) > { > struct device *dev = &pdev->dev; > @@ -161,14 +270,43 @@ static int imx_ele_ocotp_probe(struct platform_device *pdev) > priv->config.fixup_dt_cell_info = imx_ocotp_fixup_dt_cell_info; > mutex_init(&priv->lock); > > + platform_set_drvdata(pdev, priv); > + > nvmem = devm_nvmem_register(dev, &priv->config); > if (IS_ERR(nvmem)) > return PTR_ERR(nvmem); > > - return 0; > + > + return imx_ele_ocotp_access_control(pdev); > } > > +static const struct ocotp_access_gates imx93_access_gates = { > + .num_words = 3, > + .words = {19, 20, 21}, > + .num_gates = IMX93_OCOTP_NUM_GATES, > + .gates = { > + [IMX93_OCOTP_NPU_GATE] = { .word = 19, .mask = BIT(13) }, > + [IMX93_OCOTP_A550_GATE] = { .word = 19, .mask = BIT(14) }, > + [IMX93_OCOTP_A551_GATE] = { .word = 19, .mask = BIT(15) }, > + [IMX93_OCOTP_M33_GATE] = { .word = 19, .mask = BIT(24) }, > + [IMX93_OCOTP_CAN1_FD_GATE] = { .word = 19, .mask = BIT(28) }, > + [IMX93_OCOTP_CAN2_FD_GATE] = { .word = 19, .mask = BIT(29) }, > + [IMX93_OCOTP_CAN1_GATE] = { .word = 19, .mask = BIT(30) }, > + [IMX93_OCOTP_CAN2_GATE] = { .word = 19, .mask = BIT(31) }, > + [IMX93_OCOTP_USB1_GATE] = { .word = 20, .mask = BIT(3) }, > + [IMX93_OCOTP_USB2_GATE] = { .word = 20, .mask = BIT(4) }, > + [IMX93_OCOTP_ENET1_GATE] = { .word = 20, .mask = BIT(5) }, > + [IMX93_OCOTP_ENET2_GATE] = { .word = 20, .mask = BIT(6) }, > + [IMX93_OCOTP_PXP_GATE] = { .word = 20, .mask = BIT(10) }, > + [IMX93_OCOTP_MIPI_CSI1_GATE] = { .word = 20, .mask = BIT(17) }, > + [IMX93_OCOTP_MIPI_DSI1_GATE] = { .word = 20, .mask = BIT(19) }, > + [IMX93_OCOTP_LVDS1_GATE] = { .word = 20, .mask = BIT(24) }, > + [IMX93_OCOTP_ADC1_GATE] = { .word = 21, .mask = BIT(7) }, > + }, > +}; > + > static const struct ocotp_devtype_data imx93_ocotp_data = { > + .access_gates = &imx93_access_gates, > .reg_off = 0x8000, > .reg_read = imx_ocotp_reg_read, > .size = 2048, > @@ -183,7 +321,51 @@ static const struct ocotp_devtype_data imx93_ocotp_data = { > }, > }; > > +static const struct ocotp_access_gates imx95_access_gates = { > + .num_words = 3, > + .words = {17, 18, 19}, > + .num_gates = IMX95_OCOTP_NUM_GATES, > + .gates = { > + [IMX95_OCOTP_CANFD1_GATE] = { .word = 17, .mask = BIT(20) }, > + [IMX95_OCOTP_CANFD2_GATE] = { .word = 17, .mask = BIT(21) }, > + [IMX95_OCOTP_CANFD3_GATE] = { .word = 17, .mask = BIT(22) }, > + [IMX95_OCOTP_CANFD4_GATE] = { .word = 17, .mask = BIT(23) }, > + [IMX95_OCOTP_CANFD5_GATE] = { .word = 17, .mask = BIT(24) }, > + [IMX95_OCOTP_CAN1_GATE] = { .word = 17, .mask = BIT(25) }, > + [IMX95_OCOTP_CAN2_GATE] = { .word = 17, .mask = BIT(26) }, > + [IMX95_OCOTP_CAN3_GATE] = { .word = 17, .mask = BIT(27) }, > + [IMX95_OCOTP_CAN4_GATE] = { .word = 17, .mask = BIT(28) }, > + [IMX95_OCOTP_CAN5_GATE] = { .word = 17, .mask = BIT(29) }, > + [IMX95_OCOTP_NPU_GATE] = { .word = 18, .mask = BIT(0) }, > + [IMX95_OCOTP_A550_GATE] = { .word = 18, .mask = BIT(1) }, > + [IMX95_OCOTP_A551_GATE] = { .word = 18, .mask = BIT(2) }, > + [IMX95_OCOTP_A552_GATE] = { .word = 18, .mask = BIT(3) }, > + [IMX95_OCOTP_A553_GATE] = { .word = 18, .mask = BIT(4) }, > + [IMX95_OCOTP_A554_GATE] = { .word = 18, .mask = BIT(5) }, > + [IMX95_OCOTP_A555_GATE] = { .word = 18, .mask = BIT(6) }, > + [IMX95_OCOTP_M7_GATE] = { .word = 18, .mask = BIT(9) }, > + [IMX95_OCOTP_DCSS_GATE] = { .word = 18, .mask = BIT(22) }, > + [IMX95_OCOTP_LVDS1_GATE] = { .word = 18, .mask = BIT(27) }, > + [IMX95_OCOTP_ISP_GATE] = { .word = 18, .mask = BIT(29) }, > + [IMX95_OCOTP_USB1_GATE] = { .word = 19, .mask = BIT(2) }, > + [IMX95_OCOTP_USB2_GATE] = { .word = 19, .mask = BIT(3) }, > + [IMX95_OCOTP_NETC_GATE] = { .word = 19, .mask = BIT(4) }, > + [IMX95_OCOTP_PCIE1_GATE] = { .word = 19, .mask = BIT(6) }, > + [IMX95_OCOTP_PCIE2_GATE] = { .word = 19, .mask = BIT(7) }, > + [IMX95_OCOTP_ADC1_GATE] = { .word = 19, .mask = BIT(8) }, > + [IMX95_OCOTP_EARC_RX_GATE] = { .word = 19, .mask = BIT(11) }, > + [IMX95_OCOTP_GPU3D_GATE] = { .word = 19, .mask = BIT(16) }, > + [IMX95_OCOTP_VPU_GATE] = { .word = 19, .mask = BIT(17) }, > + [IMX95_OCOTP_JPEG_ENC_GATE] = { .word = 19, .mask = BIT(18) }, > + [IMX95_OCOTP_JPEG_DEC_GATE] = { .word = 19, .mask = BIT(19) }, > + [IMX95_OCOTP_MIPI_CSI1_GATE] = { .word = 19, .mask = BIT(21) }, > + [IMX95_OCOTP_MIPI_CSI2_GATE] = { .word = 19, .mask = BIT(22) }, > + [IMX95_OCOTP_MIPI_DSI1_GATE] = { .word = 19, .mask = BIT(23) }, > + } > +}; > + > static const struct ocotp_devtype_data imx95_ocotp_data = { > + .access_gates = &imx95_access_gates, > .reg_off = 0x8000, > .reg_read = imx_ocotp_reg_read, > .size = 2048, > > -- > 2.37.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-12-17 18:20 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-12-17 8:43 [PATCH v2 0/2] Make i.MX9 OCOTP work as accessing controller Peng Fan (OSS) 2024-12-17 8:43 ` [PATCH v2 1/2] dt-bindings: nvmem: imx-ocotp: Introduce #access-controller-cells Peng Fan (OSS) 2024-12-17 18:20 ` Conor Dooley 2024-12-17 8:43 ` [PATCH v2 2/2] nvmem: imx-ocotp-ele: Support accessing controller for i.MX9 Peng Fan (OSS) 2024-12-17 16:02 ` Frank Li
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