From: niravkumar.l.rabara@intel.com
To: Dinh Nguyen <dinguyen@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
niravkumar.l.rabara@intel.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH] arm64: dts: socfpga: agilex5: add clock-names property to nand node
Date: Tue, 7 Jan 2025 16:49:55 +0800 [thread overview]
Message-ID: <20250107084955.2750154-1-niravkumar.l.rabara@intel.com> (raw)
From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Cadence nand controller driver requires clock-names = "nf_clk" property.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 51c6e19e40b8..4357572e96e3 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -272,6 +272,7 @@ nand: nand-controller@10b80000 {
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clkmgr AGILEX5_NAND_NF_CLK>;
cdns,board-delay-ps = <4830>;
+ clock-names = "nf_clk";
status = "disabled";
};
--
2.25.1
next reply other threads:[~2025-01-07 8:53 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-07 8:49 niravkumar.l.rabara [this message]
2025-01-07 9:21 ` [PATCH] arm64: dts: socfpga: agilex5: add clock-names property to nand node Krzysztof Kozlowski
2025-01-07 10:21 ` Rabara, Niravkumar L
2025-01-08 7:14 ` Krzysztof Kozlowski
2025-01-08 10:00 ` Rabara, Niravkumar L
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