From: Conor Dooley <conor@kernel.org>
To: "Clément Léger" <cleger@rivosinc.com>
Cc: linux-riscv@lists.infradead.org,
Conor Dooley <conor.dooley@microchip.com>,
Eric Biggers <ebiggers@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andy Chiu <andybnac@gmail.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/6] RISC-V: add f & d extension validation checks
Date: Tue, 11 Feb 2025 12:06:44 +0000 [thread overview]
Message-ID: <20250211-phobia-spiritism-3c0ffba5315d@spud> (raw)
In-Reply-To: <cfd0a7d1-464f-468d-9302-46d6b28efe5f@rivosinc.com>
[-- Attachment #1: Type: text/plain, Size: 2602 bytes --]
On Tue, Feb 11, 2025 at 11:22:13AM +0100, Clément Léger wrote:
>
>
> On 05/02/2025 17:05, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > Using Clement's new validation callbacks, support checking that
> > dependencies have been satisfied for the floating point extensions.
> >
> > The check for "d" might be slightly confusingly shorter than that of "f",
> > despite "d" depending on "f". This is because the requirement that a
> > hart supporting double precision must also support single precision,
> > should be validated by dt-bindings etc, not the kernel but lack of
> > support for single precision only is a limitation of the kernel.
> >
> > Since vector will now be disabled proactively, there's no need to clear
> > the bit in elf_hwcap in riscv_fill_hwcap() any longer.
> >
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > arch/riscv/kernel/cpufeature.c | 27 +++++++++++++++++++++++++--
> > 1 file changed, 25 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 1c148ecea612..ad4fbaa4ff0d 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -109,6 +109,29 @@ static int riscv_ext_zicboz_validate(const struct riscv_isa_ext_data *data,
> > return 0;
> > }
> >
> > +static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data,
> > + const unsigned long *isa_bitmap)
> > +{
> > + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) {
> > + pr_warn_once("This kernel does not support systems with F but not D\n");
> > + return -EINVAL;
> > + }
>
> While I tested to remove the RISCV_ISA_EXT_d from the input isa bitmap
> and it worked, I didn't realized that it was due to the probe order of
> single letter extensions. D is probed before F so that works as
> expected. But returning -EPROBEDEFER would not allow to display the
> warn_once or wrongly display it if D was not yet probed. So I'm inclined
> to keep it as is and rely on probe order (a bit fragile but for single
> letter extensions, that seems acceptable).
I guess it's worth adding a comment to that effect.
> > +
> > + if (!IS_ENABLED(CONFIG_FPU))
> > + return -EINVAL;
>
> I would have actually move that chunk before the
> __riscv_isa_extension_available() check so that the whole function body
> is elided if FPU is disabled.
I think you're right, but for another reason too - warning when someone
has turned off CONIFG_FPU doesn't make sense.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2025-02-11 12:06 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-05 16:05 [PATCH v3 0/6] Add some validation for vector, vector crypto and fp stuff Conor Dooley
2025-02-05 16:05 ` [PATCH v3 1/6] RISC-V: add vector extension validation checks Conor Dooley
2025-02-06 10:08 ` Clément Léger
2025-02-06 11:19 ` Conor Dooley
2025-02-11 10:16 ` Clément Léger
2025-02-11 14:43 ` Conor Dooley
2025-02-05 16:05 ` [PATCH v3 2/6] RISC-V: add vector crypto " Conor Dooley
2025-02-06 10:20 ` Clément Léger
2025-02-06 11:24 ` Conor Dooley
2025-02-06 12:56 ` Clément Léger
2025-02-06 20:32 ` Eric Biggers
2025-02-07 0:02 ` Conor Dooley
2025-02-11 8:45 ` Clément Léger
2025-02-11 12:34 ` Conor Dooley
2025-02-11 13:33 ` Clément Léger
2025-02-05 16:05 ` [PATCH v3 3/6] RISC-V: add f & d " Conor Dooley
2025-02-06 10:08 ` Clément Léger
2025-02-11 10:22 ` Clément Léger
2025-02-11 12:06 ` Conor Dooley [this message]
2025-02-05 16:05 ` [PATCH v3 4/6] dt-bindings: riscv: d requires f Conor Dooley
2025-02-05 16:05 ` [PATCH v3 5/6] dt-bindings: riscv: add vector sub-extension dependencies Conor Dooley
2025-02-05 16:05 ` [PATCH v3 6/6] dt-bindings: riscv: document vector crypto requirements Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250211-phobia-spiritism-3c0ffba5315d@spud \
--to=conor@kernel.org \
--cc=andybnac@gmail.com \
--cc=cleger@rivosinc.com \
--cc=conor.dooley@microchip.com \
--cc=devicetree@vger.kernel.org \
--cc=ebiggers@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox