[PATCH 0/2] PCI: qcom-ep: BAR fixes

[PATCH 0/2] PCI: qcom-ep: BAR fixes

[Manivannan Sadhasivam]

Hi,

This series has a couple of fixes for Qcom PCIe endpoint controller. The dts
patch fixes the size of the 'addr_space' regions that allows the endpoint
drivers to request and map BARs of size >= 1MB. The driver patch marks BAR0/BAR2
as 64bit BARs.

Previously, this series was part of the Kselftest series [1]. But submitting
separately as these are independent fixes anyway.

- Mani

[1] https://lore.kernel.org/linux-pci/20241211080105.11104-1-manivannan.sadhasivam@linaro.org/

Manivannan Sadhasivam (2):
  arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regions
  PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED

 arch/arm64/boot/dts/qcom/sa8775p.dtsi     | 4 ++--
 drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++++
 2 files changed, 6 insertions(+), 2 deletions(-)

-- 
2.25.1

[PATCH 1/2] arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regions

[Manivannan Sadhasivam]

For both the controller instances, size of the 'addr_space' region should
be 0x1fe00000 as per the hardware memory layout.

Otherwise, endpoint drivers cannot request even reasonable BAR size of 1MB.

Cc: stable@vger.kernel.org # 6.11
Fixes: c5f5de8434ec ("arm64: dts: qcom: sa8775p: Add ep pcie1 controller node")
Fixes: 1924f5518224 ("arm64: dts: qcom: sa8775p: Add ep pcie0 controller node")
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 arch/arm64/boot/dts/qcom/sa8775p.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 9f315a51a7c1..368bcf7c9802 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -6092,7 +6092,7 @@ pcie0_ep: pcie-ep@1c00000 {
 		      <0x0 0x40000000 0x0 0xf20>,
 		      <0x0 0x40000f20 0x0 0xa8>,
 		      <0x0 0x40001000 0x0 0x4000>,
-		      <0x0 0x40200000 0x0 0x100000>,
+		      <0x0 0x40200000 0x0 0x1fe00000>,
 		      <0x0 0x01c03000 0x0 0x1000>,
 		      <0x0 0x40005000 0x0 0x2000>;
 		reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
@@ -6250,7 +6250,7 @@ pcie1_ep: pcie-ep@1c10000 {
 		      <0x0 0x60000000 0x0 0xf20>,
 		      <0x0 0x60000f20 0x0 0xa8>,
 		      <0x0 0x60001000 0x0 0x4000>,
-		      <0x0 0x60200000 0x0 0x100000>,
+		      <0x0 0x60200000 0x0 0x1fe00000>,
 		      <0x0 0x01c13000 0x0 0x1000>,
 		      <0x0 0x60005000 0x0 0x2000>;
 		reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
-- 
2.25.1

[PATCH 2/2] PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED

[Manivannan Sadhasivam]

On all Qcom endpoint SoCs, BAR0/BAR2 are 64bit BARs by default and software
cannot change the type. So mark the those BARs as 64bit BARs and also mark
the successive BAR1/BAR3 as RESERVED BARs so that the EPF drivers cannot
use them.

Cc: stable+noautosel@kernel.org # depends on patch introducing only_64bit flag
Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index c08f64d7a825..01d3862d7003 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -825,6 +825,10 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
 	.msi_capable = true,
 	.msix_capable = false,
 	.align = SZ_4K,
+	.bar[BAR_0] = { .only_64bit = true, },
+	.bar[BAR_1] = { .type = BAR_RESERVED, },
+	.bar[BAR_2] = { .only_64bit = true, },
+	.bar[BAR_3] = { .type = BAR_RESERVED, },
 };
 
 static const struct pci_epc_features *
-- 
2.25.1

Re: [PATCH 2/2] PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED

[Krzysztof Wilczyński]

Hello,

> On all Qcom endpoint SoCs, BAR0/BAR2 are 64bit BARs by default and software
> cannot change the type. So mark the those BARs as 64bit BARs and also mark
> the successive BAR1/BAR3 as RESERVED BARs so that the EPF drivers cannot
> use them.

Applied to controller/qcom, thank you!

	Krzysztof

Re: (subset) [PATCH 0/2] PCI: qcom-ep: BAR fixes

[Bjorn Andersson]

On Tue, 31 Dec 2024 18:32:22 +0530, Manivannan Sadhasivam wrote:
> This series has a couple of fixes for Qcom PCIe endpoint controller. The dts
> patch fixes the size of the 'addr_space' regions that allows the endpoint
> drivers to request and map BARs of size >= 1MB. The driver patch marks BAR0/BAR2
> as 64bit BARs.
> 
> Previously, this series was part of the Kselftest series [1]. But submitting
> separately as these are independent fixes anyway.
> 
> [...]

Applied, thanks!

[1/2] arm64: dts: qcom: sa8775p: Fix the size of 'addr_space' regions
      commit: ec2f548e1a92f49f765e2bce14ceed34698514fc

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>