[PATCH v3 0/2] Add support for Versal Net CPM5N Root Port controller

[PATCH v3 0/2] Add support for Versal Net CPM5N Root Port controller

[Thippeswamy Havalige]

Add support for Versal Net CPM5NC Root Port controller 0.

The Versal-Net ACAP devices include CCIX-PCIe Module (CPM). The integrated
block for CPM5NC along with the integrated bridge can function as PCIe Root
Port.

Bridge error in Versal-Net CPM5NC are handled using Versal-Net CPM5N
specific interrupt line & there is no support for legacy interrupts.

Thippeswamy Havalige (2):
  dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5NC Versal
    Net host
  PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port
    controller

 .../bindings/pci/xilinx-versal-cpm.yaml       |  1 +
 drivers/pci/controller/pcie-xilinx-cpm.c      | 48 ++++++++++++-------
 2 files changed, 33 insertions(+), 16 deletions(-)

-- 
2.43.0

[PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5NC Versal Net host

[Thippeswamy Havalige]

The Xilinx Versal Net series has Coherency and PCIe Gen5 Module
Next-Generation compact (CPM5NC) block which supports Root Port
controller functionality at Gen5 speed.

Error interrupts are handled CPM5NC specific interrupt line and
INTx interrupt is not support.

Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v2:
- Update commit message to INTx
Changes in v3:
- None
---
 Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
index b63a759ec2d7..d674a24c8ccc 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
+++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
@@ -18,6 +18,7 @@ properties:
       - xlnx,versal-cpm-host-1.00
       - xlnx,versal-cpm5-host
       - xlnx,versal-cpm5-host1
+      - xlnx,versal-cpm5nc-host
 
   reg:
     items:
-- 
2.43.0

[PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller

[Thippeswamy Havalige]

The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
incorporate the Coherency and PCIe Gen5 Module, specifically the
Next-Generation Compact Module (CPM5NC).

The integrated CPM5NC block, along with the built-in bridge, can function
as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
configuration.

Bridge errors are managed using a specific interrupt line designed for
CPM5N. Intx interrupt support is not available.

Currently in this commit platform specific Bridge errors support is not
added.

Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
---
Changes in v2:
- Update commit message.
---
 drivers/pci/controller/pcie-xilinx-cpm.c | 48 ++++++++++++++++--------
 1 file changed, 32 insertions(+), 16 deletions(-)

diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index 81e8bfae53d0..9b241c665f0a 100644
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -84,6 +84,7 @@ enum xilinx_cpm_version {
 	CPM,
 	CPM5,
 	CPM5_HOST1,
+	CPM5NC_HOST,
 };
 
 /**
@@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
 {
 	const struct xilinx_cpm_variant *variant = port->variant;
 
+	if (variant->version != CPM5NC_HOST)
+		return;
+
 	if (cpm_pcie_link_up(port))
 		dev_info(port->dev, "PCIe Link is UP\n");
 	else
@@ -493,18 +497,16 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
 		   XILINX_CPM_PCIE_REG_IDR);
 
 	/*
-	 * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
-	 * CPM SLCR block.
+	 * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to CPM SLCR block.
 	 */
 	writel(variant->ir_misc_value,
 	       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
 
-	if (variant->ir_enable) {
+	if (variant->ir_enable)
 		writel(XILINX_CPM_PCIE_IR_LOCAL,
 		       port->cpm_base + variant->ir_enable);
-	}
 
-	/* Set Bridge enable bit */
+		/* Set Bridge enable bit */
 	pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
 		   XILINX_CPM_PCIE_REG_RPSC_BEN,
 		   XILINX_CPM_PCIE_REG_RPSC);
@@ -578,16 +580,18 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 
 	port->dev = dev;
 
-	err = xilinx_cpm_pcie_init_irq_domain(port);
-	if (err)
-		return err;
+	port->variant = of_device_get_match_data(dev);
+
+	if (port->variant->version != CPM5NC_HOST) {
+		err = xilinx_cpm_pcie_init_irq_domain(port);
+		if (err)
+			return err;
+	}
 
 	bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
 	if (!bus)
 		return -ENODEV;
 
-	port->variant = of_device_get_match_data(dev);
-
 	err = xilinx_cpm_pcie_parse_dt(port, bus->res);
 	if (err) {
 		dev_err(dev, "Parsing DT failed\n");
@@ -596,10 +600,12 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 
 	xilinx_cpm_pcie_init_port(port);
 
-	err = xilinx_cpm_setup_irq(port);
-	if (err) {
-		dev_err(dev, "Failed to set up interrupts\n");
-		goto err_setup_irq;
+	if (port->variant->version != CPM5NC_HOST) {
+		err = xilinx_cpm_setup_irq(port);
+		if (err) {
+			dev_err(dev, "Failed to set up interrupts\n");
+			goto err_setup_irq;
+		}
 	}
 
 	bridge->sysdata = port->cfg;
@@ -612,11 +618,13 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 	return 0;
 
 err_host_bridge:
-	xilinx_cpm_free_interrupts(port);
+	if (port->variant->version != CPM5NC_HOST)
+		xilinx_cpm_free_interrupts(port);
 err_setup_irq:
 	pci_ecam_free(port->cfg);
 err_parse_dt:
-	xilinx_cpm_free_irq_domains(port);
+	if (port->variant->version != CPM5NC_HOST)
+		xilinx_cpm_free_irq_domains(port);
 	return err;
 }
 
@@ -639,6 +647,10 @@ static const struct xilinx_cpm_variant cpm5_host1 = {
 	.ir_enable = XILINX_CPM_PCIE1_IR_ENABLE,
 };
 
+static const struct xilinx_cpm_variant cpm5n_host = {
+	.version = CPM5NC_HOST,
+};
+
 static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
 	{
 		.compatible = "xlnx,versal-cpm-host-1.00",
@@ -652,6 +664,10 @@ static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
 		.compatible = "xlnx,versal-cpm5-host1",
 		.data = &cpm5_host1,
 	},
+	{
+		.compatible = "xlnx,versal-cpm5nc-host",
+		.data = &cpm5n_host,
+	},
 	{}
 };
 
-- 
2.43.0

RE: [PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller

[Havalige, Thippeswamy]

[AMD Official Use Only - AMD Internal Distribution Only]

Hi Manivannan Sadhasivam,

Could you please provide an update on this patch.

Regards,
Thippeswamy H

> -----Original Message-----
> From: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> Sent: Monday, February 17, 2025 12:57 PM
> To: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com;
> manivannan.sadhasivam@linaro.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org
> Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Simek, Michal <michal.simek@amd.com>; Gogada,
> Bharat Kumar <bharat.kumar.gogada@amd.com>; Havalige, Thippeswamy
> <thippeswamy.havalige@amd.com>
> Subject: [PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC
> Root Port controller
>
> The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> incorporate the Coherency and PCIe Gen5 Module, specifically the
> Next-Generation Compact Module (CPM5NC).
>
> The integrated CPM5NC block, along with the built-in bridge, can function
> as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
> rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
> configuration.
>
> Bridge errors are managed using a specific interrupt line designed for
> CPM5N. Intx interrupt support is not available.
>
> Currently in this commit platform specific Bridge errors support is not
> added.
>
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> ---
> Changes in v2:
> - Update commit message.
> ---
>  drivers/pci/controller/pcie-xilinx-cpm.c | 48 ++++++++++++++++--------
>  1 file changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c
> b/drivers/pci/controller/pcie-xilinx-cpm.c
> index 81e8bfae53d0..9b241c665f0a 100644
> --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> @@ -84,6 +84,7 @@ enum xilinx_cpm_version {
>       CPM,
>       CPM5,
>       CPM5_HOST1,
> +     CPM5NC_HOST,
>  };
>
>  /**
> @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct
> xilinx_cpm_pcie *port)
>  {
>       const struct xilinx_cpm_variant *variant = port->variant;
>
> +     if (variant->version != CPM5NC_HOST)
> +             return;
> +
>       if (cpm_pcie_link_up(port))
>               dev_info(port->dev, "PCIe Link is UP\n");
>       else
> @@ -493,18 +497,16 @@ static void xilinx_cpm_pcie_init_port(struct
> xilinx_cpm_pcie *port)
>                  XILINX_CPM_PCIE_REG_IDR);
>
>       /*
> -      * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
> -      * CPM SLCR block.
> +      * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to CPM
> SLCR block.
>        */
>       writel(variant->ir_misc_value,
>              port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
>
> -     if (variant->ir_enable) {
> +     if (variant->ir_enable)
>               writel(XILINX_CPM_PCIE_IR_LOCAL,
>                      port->cpm_base + variant->ir_enable);
> -     }
>
> -     /* Set Bridge enable bit */
> +             /* Set Bridge enable bit */
>       pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
>                  XILINX_CPM_PCIE_REG_RPSC_BEN,
>                  XILINX_CPM_PCIE_REG_RPSC);
> @@ -578,16 +580,18 @@ static int xilinx_cpm_pcie_probe(struct
> platform_device *pdev)
>
>       port->dev = dev;
>
> -     err = xilinx_cpm_pcie_init_irq_domain(port);
> -     if (err)
> -             return err;
> +     port->variant = of_device_get_match_data(dev);
> +
> +     if (port->variant->version != CPM5NC_HOST) {
> +             err = xilinx_cpm_pcie_init_irq_domain(port);
> +             if (err)
> +                     return err;
> +     }
>
>       bus = resource_list_first_type(&bridge->windows,
> IORESOURCE_BUS);
>       if (!bus)
>               return -ENODEV;
>
> -     port->variant = of_device_get_match_data(dev);
> -
>       err = xilinx_cpm_pcie_parse_dt(port, bus->res);
>       if (err) {
>               dev_err(dev, "Parsing DT failed\n");
> @@ -596,10 +600,12 @@ static int xilinx_cpm_pcie_probe(struct
> platform_device *pdev)
>
>       xilinx_cpm_pcie_init_port(port);
>
> -     err = xilinx_cpm_setup_irq(port);
> -     if (err) {
> -             dev_err(dev, "Failed to set up interrupts\n");
> -             goto err_setup_irq;
> +     if (port->variant->version != CPM5NC_HOST) {
> +             err = xilinx_cpm_setup_irq(port);
> +             if (err) {
> +                     dev_err(dev, "Failed to set up interrupts\n");
> +                     goto err_setup_irq;
> +             }
>       }
>
>       bridge->sysdata = port->cfg;
> @@ -612,11 +618,13 @@ static int xilinx_cpm_pcie_probe(struct
> platform_device *pdev)
>       return 0;
>
>  err_host_bridge:
> -     xilinx_cpm_free_interrupts(port);
> +     if (port->variant->version != CPM5NC_HOST)
> +             xilinx_cpm_free_interrupts(port);
>  err_setup_irq:
>       pci_ecam_free(port->cfg);
>  err_parse_dt:
> -     xilinx_cpm_free_irq_domains(port);
> +     if (port->variant->version != CPM5NC_HOST)
> +             xilinx_cpm_free_irq_domains(port);
>       return err;
>  }
>
> @@ -639,6 +647,10 @@ static const struct xilinx_cpm_variant cpm5_host1 =
> {
>       .ir_enable = XILINX_CPM_PCIE1_IR_ENABLE,
>  };
>
> +static const struct xilinx_cpm_variant cpm5n_host = {
> +     .version = CPM5NC_HOST,
> +};
> +
>  static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
>       {
>               .compatible = "xlnx,versal-cpm-host-1.00",
> @@ -652,6 +664,10 @@ static const struct of_device_id
> xilinx_cpm_pcie_of_match[] = {
>               .compatible = "xlnx,versal-cpm5-host1",
>               .data = &cpm5_host1,
>       },
> +     {
> +             .compatible = "xlnx,versal-cpm5nc-host",
> +             .data = &cpm5n_host,
> +     },
>       {}
>  };
>
> --
> 2.43.0

Re: [PATCH v3 1/2] dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5NC Versal Net host

[Manivannan Sadhasivam]

On Mon, Feb 17, 2025 at 12:57:12PM +0530, Thippeswamy Havalige wrote:
> The Xilinx Versal Net series has Coherency and PCIe Gen5 Module
> Next-Generation compact (CPM5NC) block which supports Root Port
> controller functionality at Gen5 speed.
> 
> Error interrupts are handled CPM5NC specific interrupt line and
> INTx interrupt is not support.
> 
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

- Mani

> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Changes in v2:
> - Update commit message to INTx
> Changes in v3:
> - None
> ---
>  Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> index b63a759ec2d7..d674a24c8ccc 100644
> --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
> @@ -18,6 +18,7 @@ properties:
>        - xlnx,versal-cpm-host-1.00
>        - xlnx,versal-cpm5-host
>        - xlnx,versal-cpm5-host1
> +      - xlnx,versal-cpm5nc-host
>  
>    reg:
>      items:
> -- 
> 2.43.0
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller

[Manivannan Sadhasivam]

On Mon, Feb 17, 2025 at 12:57:13PM +0530, Thippeswamy Havalige wrote:
> The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> incorporate the Coherency and PCIe Gen5 Module, specifically the

What do you mean by 'Coherency' here? Cache coherency?

> Next-Generation Compact Module (CPM5NC).
> 
> The integrated CPM5NC block, along with the built-in bridge, can function
> as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
> rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
> configuration.
> 
> Bridge errors are managed using a specific interrupt line designed for
> CPM5N. Intx interrupt support is not available.

INTx

> 
> Currently in this commit platform specific Bridge errors support is not
> added.
> 
> Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> ---
> Changes in v2:
> - Update commit message.
> ---
>  drivers/pci/controller/pcie-xilinx-cpm.c | 48 ++++++++++++++++--------
>  1 file changed, 32 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
> index 81e8bfae53d0..9b241c665f0a 100644
> --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> @@ -84,6 +84,7 @@ enum xilinx_cpm_version {
>  	CPM,
>  	CPM5,
>  	CPM5_HOST1,
> +	CPM5NC_HOST,
>  };
>  
>  /**
> @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
>  {
>  	const struct xilinx_cpm_variant *variant = port->variant;
>  
> +	if (variant->version != CPM5NC_HOST)
> +		return;
> +
>  	if (cpm_pcie_link_up(port))
>  		dev_info(port->dev, "PCIe Link is UP\n");
>  	else
> @@ -493,18 +497,16 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
>  		   XILINX_CPM_PCIE_REG_IDR);
>  
>  	/*
> -	 * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
> -	 * CPM SLCR block.
> +	 * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to CPM SLCR block.

Spurious change.

>  	 */
>  	writel(variant->ir_misc_value,
>  	       port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
>  
> -	if (variant->ir_enable) {
> +	if (variant->ir_enable)
>  		writel(XILINX_CPM_PCIE_IR_LOCAL,
>  		       port->cpm_base + variant->ir_enable);
> -	}

Same here. You should not do these kind of the cleanups in this patch as this
patch is supposed to add only CPM5NC support.

>  
> -	/* Set Bridge enable bit */
> +		/* Set Bridge enable bit */

Same here.

Rest LGTM!

- Mani

-- 
மணிவண்ணன் சதாசிவம்

RE: [PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller

[Havalige, Thippeswamy]

[AMD Official Use Only - AMD Internal Distribution Only]

Hi Mani,

> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Sent: Monday, February 24, 2025 12:39 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>
> Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com;
> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; linux-
> pci@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Simek, Michal <michal.simek@amd.com>; Gogada,
> Bharat Kumar <bharat.kumar.gogada@amd.com>
> Subject: Re: [PATCH v3 2/2] PCI: xilinx-cpm: Add support for Versal Net
> CPM5NC Root Port controller
>
> On Mon, Feb 17, 2025 at 12:57:13PM +0530, Thippeswamy Havalige wrote:
> > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> > incorporate the Coherency and PCIe Gen5 Module, specifically the
>
> What do you mean by 'Coherency' here? Cache coherency?
- Thank you for reviewing, Here Coherency is about CCIX/CXL but I don't
Think this should be mentioned here.
>
> > Next-Generation Compact Module (CPM5NC).
> >
> > The integrated CPM5NC block, along with the built-in bridge, can
> > function as a PCIe Root Port & supports the PCIe Gen5 protocol with
> > data transfer rates of up to 32 GT/s, capable of supporting up to a
> > x16 lane-width configuration.
> >
> > Bridge errors are managed using a specific interrupt line designed for
> > CPM5N. Intx interrupt support is not available.
>
> INTx
- Thanks for reviewing, I ll update this in next patch.
>
> >
> > Currently in this commit platform specific Bridge errors support is
> > not added.
> >
> > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> > ---
> > Changes in v2:
> > - Update commit message.
> > ---
> >  drivers/pci/controller/pcie-xilinx-cpm.c | 48
> > ++++++++++++++++--------
> >  1 file changed, 32 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c
> > b/drivers/pci/controller/pcie-xilinx-cpm.c
> > index 81e8bfae53d0..9b241c665f0a 100644
> > --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> > @@ -84,6 +84,7 @@ enum xilinx_cpm_version {
> >     CPM,
> >     CPM5,
> >     CPM5_HOST1,
> > +   CPM5NC_HOST,
> >  };
> >
> >  /**
> > @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct
> > xilinx_cpm_pcie *port)  {
> >     const struct xilinx_cpm_variant *variant = port->variant;
> >
> > +   if (variant->version != CPM5NC_HOST)
> > +           return;
> > +
> >     if (cpm_pcie_link_up(port))
> >             dev_info(port->dev, "PCIe Link is UP\n");
> >     else
> > @@ -493,18 +497,16 @@ static void xilinx_cpm_pcie_init_port(struct
> xilinx_cpm_pcie *port)
> >                XILINX_CPM_PCIE_REG_IDR);
> >
> >     /*
> > -    * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to
> > -    * CPM SLCR block.
> > +    * XILINX_CPM_PCIE_MISC_IR_ENABLE register is mapped to CPM
> SLCR block.
>
> Spurious change.
- Thank you for reviewing. These comments were made in the v2 patch, and I have addressed them in this version.
Ll remove this changes in next patch.
>
> >      */
> >     writel(variant->ir_misc_value,
> >            port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
> >
> > -   if (variant->ir_enable) {
> > +   if (variant->ir_enable)
> >             writel(XILINX_CPM_PCIE_IR_LOCAL,
> >                    port->cpm_base + variant->ir_enable);
> > -   }
>
> Same here. You should not do these kind of the cleanups in this patch as this
> patch is supposed to add only CPM5NC support.
- Thank you for reviewing. These comments were made in the v2 patch, and I have addressed them in this version.
Ll remove this changes in next patch.
> >
> > -   /* Set Bridge enable bit */
> > +           /* Set Bridge enable bit */
Thank you for reviewing. Ll update this in next patch.
>
> Same here.
>
> Rest LGTM!
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்