From: Conor Dooley <conor@kernel.org>
To: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Paul Walmsley <paul.walmsley@sifive.com>,
Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Min Lin <linmin@eswincomputing.com>,
Pritesh Patel <pritesh.patel@einfochips.com>,
Yangyu Chen <cyy@cyyself.name>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Yu Chien Peter Lin <peterlin@andestech.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Kanak Shilledar <kanakshilledar@gmail.com>,
Darshan Prajapati <darshan.prajapati@einfochips.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Heiko Stuebner <heiko@sntech.de>,
Aradhya Bhatia <a-bhatia1@ti.com>,
"rafal@milecki.pl" <rafal@milecki.pl>,
Anup Patel <anup@brainfault.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC
Date: Fri, 21 Mar 2025 13:41:36 +0000 [thread overview]
Message-ID: <20250321-pacifier-varied-bbb1cae00182@spud> (raw)
In-Reply-To: <SA3PR04MB893147FE3E09B43DA41A7DF283DB2@SA3PR04MB8931.namprd04.prod.outlook.com>
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On Fri, Mar 21, 2025 at 11:29:27AM +0000, Pinkesh Vaghela wrote:
> On Fri, Mar 21, 2025 at 3:07 PM, Krzysztof Kozlowski wrote:
> > > On Thu, Mar 20, 2025 at 10:39:52AM +0000, Pinkesh Vaghela wrote:
> > >> On Tue, Mar 11, 2025 at 11:38 PM, Conor Dooley wrote:
> > >>> On Tue, Mar 11, 2025 at 01:04:22PM +0530, Pinkesh Vaghela wrote:
> > >>>> Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
> > >>>> P550 CPU cluster and the first development board that uses it, the
> > >>>> SiFive HiFive Premier P550.
> > >>>>
> > >>>> This patch series adds initial device tree and also adds ESWIN
> > >>>> architecture support.
> > >>>>
> > >>>> Boot-tested using intiramfs with Linux 6.14.0-rc2 on HiFive Premier
> > >>>> P550 board using U-Boot 2024.01 and OpenSBI 1.4.
> > >>>
> > >>> There's no git tree in your MAINTAINERS entry, nor mention here of
> > >>> what the story is going to be in terms of sending patches to Arnd.
> > >>> Who is going to be doing that?
> > >>
> > >> We are not currently set up for sending signed pull requests, so for
> > >> now we plan to send changes to Arnd as separate patches.
> > >
> > > Undesirable, but sure. You didn't answer the first part of my question
> >
> > Just to clarify - separate patches as separate postings to soc@ after the review
> > was done on the lists and then you applied them to the tree Conor asked
> > below, right?
>
> Correct. Once the patches are reviewed, will send separate patches to @soc
> and then apply to the git tree.
No, that's the wrong order. You apply reviewed patches to the git tree,
they then appear in linux-next, after some time soaking there, you send
a PR (or in your case patches) to soc@kernel.org, usually around rc6 or
rc7. Fixes get applied to a different branch and can be sent at any
time. I expect both branches to appear in linux-next.
Bear in mind that patches for this SoC might be sent by other people,
for example me if I find some issues, and you'll need to forward those
on to soc@kernel.org on top of whatever work you're doing to bring up
the SoC.
> > > though, and there's no git tree listed in your v2 series. That part is
> > > not negotiable, you have to have one and get it included in linux-next.
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next prev parent reply other threads:[~2025-03-21 13:41 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-11 7:34 [PATCH 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Pinkesh Vaghela
2025-03-11 7:34 ` [PATCH 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible Pinkesh Vaghela
2025-03-11 18:14 ` Conor Dooley
2025-03-11 7:34 ` [PATCH 02/10] riscv: Add Kconfig option for ESWIN platforms Pinkesh Vaghela
2025-03-11 18:14 ` Conor Dooley
2025-03-11 7:34 ` [PATCH 03/10] dt-bindings: vendor-prefixes: add eswin Pinkesh Vaghela
2025-03-11 18:15 ` Conor Dooley
2025-03-11 7:34 ` [PATCH 04/10] dt-bindings: riscv: Add SiFive HiFive Premier P550 board Pinkesh Vaghela
2025-03-12 12:03 ` Matthias Brugger
2025-03-12 12:50 ` Conor Dooley
2025-03-12 12:52 ` Matthias Brugger
2025-03-12 12:55 ` Krzysztof Kozlowski
2025-03-12 14:25 ` [External] " Pinkesh Vaghela
2025-03-13 8:15 ` Samuel Holland
2025-03-13 8:39 ` Krzysztof Kozlowski
2025-03-11 7:34 ` [PATCH 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Pinkesh Vaghela
2025-03-11 18:11 ` Conor Dooley
2025-03-12 13:51 ` [External] " Pinkesh Vaghela
2025-03-11 7:34 ` [PATCH 06/10] cache: sifive_ccache: Add ESWIN EIC7700 support Pinkesh Vaghela
2025-03-11 7:34 ` [PATCH 07/10] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC Pinkesh Vaghela
2025-03-11 18:12 ` Conor Dooley
2025-03-11 7:34 ` [PATCH 08/10] dt-bindings: timer: Add ESWIN EIC7700 CLINT Pinkesh Vaghela
2025-03-11 18:12 ` Conor Dooley
2025-03-11 7:34 ` [PATCH 09/10] riscv: dts: add initial support for EIC7700 SoC Pinkesh Vaghela
2025-03-11 7:34 ` [PATCH 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree Pinkesh Vaghela
2025-03-11 18:07 ` [PATCH 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Conor Dooley
2025-03-20 10:39 ` Pinkesh Vaghela
2025-03-20 12:00 ` Conor Dooley
2025-03-21 9:37 ` Krzysztof Kozlowski
2025-03-21 11:29 ` Pinkesh Vaghela
2025-03-21 13:41 ` Conor Dooley [this message]
2025-03-21 11:25 ` Pinkesh Vaghela
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