From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Tingwei Zhang <quic_tingweiz@quicinc.com>,
Jinlong Mao <quic_jinlmao@quicinc.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com
Subject: [PATCH v2 5/5] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device
Date: Thu, 10 Apr 2025 09:33:30 +0800 [thread overview]
Message-ID: <20250410013330.3609482-6-jie.gan@oss.qualcomm.com> (raw)
In-Reply-To: <20250410013330.3609482-1-jie.gan@oss.qualcomm.com>
Add interrupts to enable byte-cntr function for TMC ETR devices.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index a904960359d7..b091e941aa21 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -2427,6 +2427,11 @@ ctcu@4001000 {
clocks = <&aoss_qmp>;
clock-names = "apb";
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "etr0",
+ "etr1";
+
in-ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.34.1
next prev parent reply other threads:[~2025-04-10 1:34 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-10 1:33 [PATCH v2 0/5] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-04-10 1:33 ` [PATCH v2 1/5] coresight: tmc: Introduce new APIs to get the RWP offset of ETR buffer Jie Gan
2025-04-10 1:33 ` [PATCH v2 2/5] dt-bindings: arm: Add an interrupt property for Coresight CTCU Jie Gan
2025-04-10 6:47 ` Krzysztof Kozlowski
2025-04-10 6:56 ` Jie Gan
2025-04-10 1:33 ` [PATCH v2 3/5] coresight: ctcu: Enable byte-cntr for TMC ETR devices Jie Gan
2025-04-10 1:33 ` [PATCH v2 4/5] coresight: tmc: add functions for byte-cntr operation Jie Gan
2025-04-10 1:33 ` Jie Gan [this message]
2025-04-10 16:28 ` [PATCH v2 5/5] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Konrad Dybcio
2025-04-11 10:16 ` [PATCH v2 0/5] coresight: ctcu: Enable byte-cntr function for TMC ETR Mike Leach
2025-06-03 1:44 ` Jie Gan
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