From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Jie Gan <jie.gan@oss.qualcomm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Tingwei Zhang <quic_tingweiz@quicinc.com>,
Jinlong Mao <quic_jinlmao@quicinc.com>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-msm@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH v2 5/5] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device
Date: Thu, 10 Apr 2025 18:28:51 +0200 [thread overview]
Message-ID: <5cf9c47f-089a-4748-b4b5-21637fb7368c@oss.qualcomm.com> (raw)
In-Reply-To: <20250410013330.3609482-6-jie.gan@oss.qualcomm.com>
On 4/10/25 3:33 AM, Jie Gan wrote:
> Add interrupts to enable byte-cntr function for TMC ETR devices.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
next prev parent reply other threads:[~2025-04-10 16:28 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-10 1:33 [PATCH v2 0/5] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-04-10 1:33 ` [PATCH v2 1/5] coresight: tmc: Introduce new APIs to get the RWP offset of ETR buffer Jie Gan
2025-04-10 1:33 ` [PATCH v2 2/5] dt-bindings: arm: Add an interrupt property for Coresight CTCU Jie Gan
2025-04-10 6:47 ` Krzysztof Kozlowski
2025-04-10 6:56 ` Jie Gan
2025-04-10 1:33 ` [PATCH v2 3/5] coresight: ctcu: Enable byte-cntr for TMC ETR devices Jie Gan
2025-04-10 1:33 ` [PATCH v2 4/5] coresight: tmc: add functions for byte-cntr operation Jie Gan
2025-04-10 1:33 ` [PATCH v2 5/5] arm64: dts: qcom: sa8775p: Add interrupts to CTCU device Jie Gan
2025-04-10 16:28 ` Konrad Dybcio [this message]
2025-04-11 10:16 ` [PATCH v2 0/5] coresight: ctcu: Enable byte-cntr function for TMC ETR Mike Leach
2025-06-03 1:44 ` Jie Gan
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