* [PATCH v8 1/5] dt-bindings: gpio: spacemit: add support for K1 SoC
2025-04-11 23:31 [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
@ 2025-04-11 23:31 ` Yixun Lan
2025-04-11 23:31 ` [PATCH v8 2/5] " Yixun Lan
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2025-04-11 23:31 UTC (permalink / raw)
To: Bartosz Golaszewski, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Conor Dooley, Paul Walmsley,
Palmer Dabbelt
Cc: Alex Elder, Yangyu Chen, Jisheng Zhang, Jesse Taube,
Inochi Amaoto, Icenowy Zheng, Meng Zhang, linux-gpio, devicetree,
linux-kernel, linux-riscv, spacemit, Yixun Lan
The GPIO controller of K1 support basic functions as input/output,
all pins can be used as interrupt which route to one IRQ line,
trigger type can be select between rising edge, falling edge, or both.
There are four GPIO banks, each consisting of 32 pins.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
hi Rob, I've kept your Review tag in this version, but want to
mention some changes here:
- new clock property is added
- add reset preperty, but make it optional
---
.../devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 96 ++++++++++++++++++++++
1 file changed, 96 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..ec0232e72c71221444972f0d3e0f391be05e4ef6
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/spacemit,k1-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 GPIO controller
+
+maintainers:
+ - Yixun Lan <dlan@gentoo.org>
+
+description:
+ The controller's registers are organized as sets of eight 32-bit
+ registers with each set of port controlling 32 pins. A single
+ interrupt line is shared for all of the pins by the controller.
+
+properties:
+ $nodename:
+ pattern: "^gpio@[0-9a-f]+$"
+
+ compatible:
+ const: spacemit,k1-gpio
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: GPIO Core Clock
+ - description: GPIO Bus Clock
+
+ clock-names:
+ items:
+ - const: core
+ - const: bus
+
+ resets:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 3
+ description:
+ The first two cells are the GPIO bank index and offset inside the bank,
+ the third cell should specify GPIO flag.
+
+ gpio-ranges: true
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 3
+ description:
+ The first two cells are the GPIO bank index and offset inside the bank,
+ the third cell should specify interrupt flag. The controller does not
+ support level interrupts, so flags of IRQ_TYPE_LEVEL_HIGH,
+ IRQ_TYPE_LEVEL_LOW should not be used.
+ Refer <dt-bindings/interrupt-controller/irq.h> for valid flags.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+ - gpio-ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio@d4019000 {
+ compatible = "spacemit,k1-gpio";
+ reg = <0xd4019000 0x800>;
+ clocks =<&ccu 9>, <&ccu 61>;
+ clock-names = "core", "bus";
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupts = <58>;
+ interrupt-controller;
+ interrupt-parent = <&plic>;
+ #interrupt-cells = <3>;
+ gpio-ranges = <&pinctrl 0 0 0 32>,
+ <&pinctrl 1 0 32 32>,
+ <&pinctrl 2 0 64 32>,
+ <&pinctrl 3 0 96 32>;
+ };
+...
--
2.49.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v8 2/5] gpio: spacemit: add support for K1 SoC
2025-04-11 23:31 [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
2025-04-11 23:31 ` [PATCH v8 1/5] dt-bindings: gpio: spacemit: add " Yixun Lan
@ 2025-04-11 23:31 ` Yixun Lan
2025-04-11 23:31 ` [PATCH v8 3/5] riscv: defconfig: spacemit: enable gpio " Yixun Lan
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2025-04-11 23:31 UTC (permalink / raw)
To: Bartosz Golaszewski, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Conor Dooley, Paul Walmsley,
Palmer Dabbelt
Cc: Alex Elder, Yangyu Chen, Jisheng Zhang, Jesse Taube,
Inochi Amaoto, Icenowy Zheng, Meng Zhang, linux-gpio, devicetree,
linux-kernel, linux-riscv, spacemit, Yixun Lan
Implement GPIO functionality which capable of setting pin as
input, output. Also, each pin can be used as interrupt which
support rising, falling, or both edge type trigger.
Reviewed-by: Alex Elder <elder@riscstar.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
drivers/gpio/Kconfig | 9 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-spacemit-k1.c | 293 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 303 insertions(+)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index f2c39bbff83a33dcb12b2d32aa3ebc358a0dd949..b12de1612d5c07866b7709e8a79a798b09fb55b9 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -656,6 +656,15 @@ config GPIO_SNPS_CREG
where only several fields in register belong to GPIO lines and
each GPIO line owns a field with different length and on/off value.
+config GPIO_SPACEMIT_K1
+ tristate "SPACEMIT K1 GPIO support"
+ depends on ARCH_SPACEMIT || COMPILE_TEST
+ depends on OF_GPIO
+ select GPIO_GENERIC
+ select GPIOLIB_IRQCHIP
+ help
+ Say yes here to support the SpacemiT's K1 GPIO device.
+
config GPIO_SPEAR_SPICS
bool "ST SPEAr13xx SPI Chip Select as GPIO support"
depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index af130882ffeeef8b1d518867bfe1493ec4f21b5f..d7bee8fe3778e9e196ba5ce2fde7bc5315daf933 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -159,6 +159,7 @@ obj-$(CONFIG_GPIO_SIOX) += gpio-siox.o
obj-$(CONFIG_GPIO_SL28CPLD) += gpio-sl28cpld.o
obj-$(CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER) += gpio-sloppy-logic-analyzer.o
obj-$(CONFIG_GPIO_SODAVILLE) += gpio-sodaville.o
+obj-$(CONFIG_GPIO_SPACEMIT_K1) += gpio-spacemit-k1.o
obj-$(CONFIG_GPIO_SPEAR_SPICS) += gpio-spear-spics.o
obj-$(CONFIG_GPIO_SPRD) += gpio-sprd.o
obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
diff --git a/drivers/gpio/gpio-spacemit-k1.c b/drivers/gpio/gpio-spacemit-k1.c
new file mode 100644
index 0000000000000000000000000000000000000000..f027066365ff8741f99da076d1e7b6339a6c1a22
--- /dev/null
+++ b/drivers/gpio/gpio-spacemit-k1.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023-2025 SpacemiT (Hangzhou) Technology Co. Ltd
+ * Copyright (C) 2025 Yixun Lan <dlan@gentoo.org>
+ */
+
+#include <linux/clk.h>
+#include <linux/gpio/driver.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+
+/* register offset */
+#define SPACEMIT_GPLR 0x00 /* port level - R */
+#define SPACEMIT_GPDR 0x0c /* port direction - R/W */
+#define SPACEMIT_GPSR 0x18 /* port set - W */
+#define SPACEMIT_GPCR 0x24 /* port clear - W */
+#define SPACEMIT_GRER 0x30 /* port rising edge R/W */
+#define SPACEMIT_GFER 0x3c /* port falling edge R/W */
+#define SPACEMIT_GEDR 0x48 /* edge detect status - R/W1C */
+#define SPACEMIT_GSDR 0x54 /* (set) direction - W */
+#define SPACEMIT_GCDR 0x60 /* (clear) direction - W */
+#define SPACEMIT_GSRER 0x6c /* (set) rising edge detect enable - W */
+#define SPACEMIT_GCRER 0x78 /* (clear) rising edge detect enable - W */
+#define SPACEMIT_GSFER 0x84 /* (set) falling edge detect enable - W */
+#define SPACEMIT_GCFER 0x90 /* (clear) falling edge detect enable - W */
+#define SPACEMIT_GAPMASK 0x9c /* interrupt mask , 0 disable, 1 enable - R/W */
+
+#define SPACEMIT_NR_BANKS 4
+#define SPACEMIT_NR_GPIOS_PER_BANK 32
+
+#define to_spacemit_gpio_bank(x) container_of((x), struct spacemit_gpio_bank, gc)
+
+struct spacemit_gpio;
+
+struct spacemit_gpio_bank {
+ struct gpio_chip gc;
+ struct spacemit_gpio *sg;
+ void __iomem *base;
+ u32 irq_mask;
+ u32 irq_rising_edge;
+ u32 irq_falling_edge;
+};
+
+struct spacemit_gpio {
+ struct device *dev;
+ struct spacemit_gpio_bank sgb[SPACEMIT_NR_BANKS];
+};
+
+static u32 spacemit_gpio_bank_index(struct spacemit_gpio_bank *gb)
+{
+ return (u32)(gb - gb->sg->sgb);
+}
+
+static irqreturn_t spacemit_gpio_irq_handler(int irq, void *dev_id)
+{
+ struct spacemit_gpio_bank *gb = dev_id;
+ unsigned long pending;
+ u32 n, gedr;
+
+ gedr = readl(gb->base + SPACEMIT_GEDR);
+ if (!gedr)
+ return IRQ_NONE;
+ writel(gedr, gb->base + SPACEMIT_GEDR);
+
+ pending = gedr & gb->irq_mask;
+ if (!pending)
+ return IRQ_NONE;
+
+ for_each_set_bit(n, &pending, BITS_PER_LONG)
+ handle_nested_irq(irq_find_mapping(gb->gc.irq.domain, n));
+
+ return IRQ_HANDLED;
+}
+
+static void spacemit_gpio_irq_ack(struct irq_data *d)
+{
+ struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d);
+
+ writel(BIT(irqd_to_hwirq(d)), gb->base + SPACEMIT_GEDR);
+}
+
+static void spacemit_gpio_irq_mask(struct irq_data *d)
+{
+ struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d);
+ u32 bit = BIT(irqd_to_hwirq(d));
+
+ gb->irq_mask &= ~bit;
+ writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK);
+
+ if (bit & gb->irq_rising_edge)
+ writel(bit, gb->base + SPACEMIT_GCRER);
+
+ if (bit & gb->irq_falling_edge)
+ writel(bit, gb->base + SPACEMIT_GCFER);
+}
+
+static void spacemit_gpio_irq_unmask(struct irq_data *d)
+{
+ struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d);
+ u32 bit = BIT(irqd_to_hwirq(d));
+
+ gb->irq_mask |= bit;
+
+ if (bit & gb->irq_rising_edge)
+ writel(bit, gb->base + SPACEMIT_GSRER);
+
+ if (bit & gb->irq_falling_edge)
+ writel(bit, gb->base + SPACEMIT_GSFER);
+
+ writel(gb->irq_mask, gb->base + SPACEMIT_GAPMASK);
+}
+
+static int spacemit_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(d);
+ u32 bit = BIT(irqd_to_hwirq(d));
+
+ if (type & IRQ_TYPE_EDGE_RISING) {
+ gb->irq_rising_edge |= bit;
+ writel(bit, gb->base + SPACEMIT_GSRER);
+ } else {
+ gb->irq_rising_edge &= ~bit;
+ writel(bit, gb->base + SPACEMIT_GCRER);
+ }
+
+ if (type & IRQ_TYPE_EDGE_FALLING) {
+ gb->irq_falling_edge |= bit;
+ writel(bit, gb->base + SPACEMIT_GSFER);
+ } else {
+ gb->irq_falling_edge &= ~bit;
+ writel(bit, gb->base + SPACEMIT_GCFER);
+ }
+
+ return 0;
+}
+
+static void spacemit_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p)
+{
+ struct spacemit_gpio_bank *gb = irq_data_get_irq_chip_data(data);
+
+ seq_printf(p, "%s-%d", dev_name(gb->gc.parent), spacemit_gpio_bank_index(gb));
+}
+
+static struct irq_chip spacemit_gpio_chip = {
+ .name = "k1-gpio-irqchip",
+ .irq_ack = spacemit_gpio_irq_ack,
+ .irq_mask = spacemit_gpio_irq_mask,
+ .irq_unmask = spacemit_gpio_irq_unmask,
+ .irq_set_type = spacemit_gpio_irq_set_type,
+ .irq_print_chip = spacemit_gpio_irq_print_chip,
+ .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE,
+ GPIOCHIP_IRQ_RESOURCE_HELPERS,
+};
+
+static bool spacemit_of_node_instance_match(struct gpio_chip *gc, unsigned int i)
+{
+ struct spacemit_gpio_bank *gb = gpiochip_get_data(gc);
+ struct spacemit_gpio *sg = gb->sg;
+
+ if (i >= SPACEMIT_NR_BANKS)
+ return false;
+
+ return (gc == &sg->sgb[i].gc);
+}
+
+static int spacemit_gpio_add_bank(struct spacemit_gpio *sg,
+ void __iomem *regs,
+ int index, int irq)
+{
+ struct spacemit_gpio_bank *gb = &sg->sgb[index];
+ struct gpio_chip *gc = &gb->gc;
+ struct device *dev = sg->dev;
+ struct gpio_irq_chip *girq;
+ void __iomem *dat, *set, *clr, *dirin, *dirout;
+ int ret, bank_base[] = { 0x0, 0x4, 0x8, 0x100 };
+
+ gb->base = regs + bank_base[index];
+
+ dat = gb->base + SPACEMIT_GPLR;
+ set = gb->base + SPACEMIT_GPSR;
+ clr = gb->base + SPACEMIT_GPCR;
+ dirin = gb->base + SPACEMIT_GCDR;
+ dirout = gb->base + SPACEMIT_GSDR;
+
+ /* This registers 32 GPIO lines per bank */
+ ret = bgpio_init(gc, dev, 4, dat, set, clr, dirout, dirin,
+ BGPIOF_UNREADABLE_REG_SET | BGPIOF_UNREADABLE_REG_DIR);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to init gpio chip\n");
+
+ gb->sg = sg;
+
+ gc->label = dev_name(dev);
+ gc->request = gpiochip_generic_request;
+ gc->free = gpiochip_generic_free;
+ gc->ngpio = SPACEMIT_NR_GPIOS_PER_BANK;
+ gc->base = -1;
+ gc->of_gpio_n_cells = 3;
+ gc->of_node_instance_match = spacemit_of_node_instance_match;
+
+ girq = &gc->irq;
+ girq->threaded = true;
+ girq->handler = handle_simple_irq;
+
+ gpio_irq_chip_set_chip(girq, &spacemit_gpio_chip);
+
+ /* Disable Interrupt */
+ writel(0, gb->base + SPACEMIT_GAPMASK);
+ /* Disable Edge Detection Settings */
+ writel(0x0, gb->base + SPACEMIT_GRER);
+ writel(0x0, gb->base + SPACEMIT_GFER);
+ /* Clear Interrupt */
+ writel(0xffffffff, gb->base + SPACEMIT_GCRER);
+ writel(0xffffffff, gb->base + SPACEMIT_GCFER);
+
+ ret = devm_request_threaded_irq(dev, irq, NULL,
+ spacemit_gpio_irq_handler,
+ IRQF_ONESHOT | IRQF_SHARED,
+ gb->gc.label, gb);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to register IRQ\n");
+
+ ret = devm_gpiochip_add_data(dev, gc, gb);
+ if (ret)
+ return ret;
+
+ /* Distuingish IRQ domain, for selecting threecells mode */
+ irq_domain_update_bus_token(girq->domain, DOMAIN_BUS_WIRED);
+
+ return 0;
+}
+
+static int spacemit_gpio_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct spacemit_gpio *sg;
+ struct clk *core_clk, *bus_clk;
+ void __iomem *regs;
+ int i, irq, ret;
+
+ sg = devm_kzalloc(dev, sizeof(*sg), GFP_KERNEL);
+ if (!sg)
+ return -ENOMEM;
+
+ regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ sg->dev = dev;
+
+ core_clk = devm_clk_get_enabled(dev, "core");
+ if (IS_ERR(core_clk))
+ return dev_err_probe(dev, PTR_ERR(core_clk), "failed to get clock\n");
+
+ bus_clk = devm_clk_get_enabled(dev, "bus");
+ if (IS_ERR(bus_clk))
+ return dev_err_probe(dev, PTR_ERR(bus_clk), "failed to get bus clock\n");
+
+ for (i = 0; i < SPACEMIT_NR_BANKS; i++) {
+ ret = spacemit_gpio_add_bank(sg, regs, i, irq);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id spacemit_gpio_dt_ids[] = {
+ { .compatible = "spacemit,k1-gpio" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver spacemit_gpio_driver = {
+ .probe = spacemit_gpio_probe,
+ .driver = {
+ .name = "k1-gpio",
+ .of_match_table = spacemit_gpio_dt_ids,
+ },
+};
+module_platform_driver(spacemit_gpio_driver);
+
+MODULE_AUTHOR("Yixun Lan <dlan@gentoo.org>");
+MODULE_DESCRIPTION("GPIO driver for SpacemiT K1 SoC");
+MODULE_LICENSE("GPL");
--
2.49.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v8 3/5] riscv: defconfig: spacemit: enable gpio support for K1 SoC
2025-04-11 23:31 [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
2025-04-11 23:31 ` [PATCH v8 1/5] dt-bindings: gpio: spacemit: add " Yixun Lan
2025-04-11 23:31 ` [PATCH v8 2/5] " Yixun Lan
@ 2025-04-11 23:31 ` Yixun Lan
2025-04-11 23:31 ` [PATCH v8 4/5] riscv: dts: spacemit: add " Yixun Lan
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2025-04-11 23:31 UTC (permalink / raw)
To: Bartosz Golaszewski, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Conor Dooley, Paul Walmsley,
Palmer Dabbelt
Cc: Alex Elder, Yangyu Chen, Jisheng Zhang, Jesse Taube,
Inochi Amaoto, Icenowy Zheng, Meng Zhang, linux-gpio, devicetree,
linux-kernel, linux-riscv, spacemit, Yixun Lan
Enable GPIO support, in order to activate follow-up GPIO LED,
and ethernet reset pin.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 3c8e16d71e175e0e4c27136c31761127ce6e1602..b8899d59dd345c50d877829c05d0330f2986895c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -169,6 +169,7 @@ CONFIG_PINCTRL_SOPHGO_SG2002=y
CONFIG_PINCTRL_TH1520=y
CONFIG_GPIO_DWAPB=y
CONFIG_GPIO_SIFIVE=y
+CONFIG_GPIO_SPACEMIT_K1=y
CONFIG_POWER_RESET_GPIO_RESTART=y
CONFIG_SENSORS_SFCTEMP=m
CONFIG_CPU_THERMAL=y
--
2.49.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v8 4/5] riscv: dts: spacemit: add gpio support for K1 SoC
2025-04-11 23:31 [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
` (2 preceding siblings ...)
2025-04-11 23:31 ` [PATCH v8 3/5] riscv: defconfig: spacemit: enable gpio " Yixun Lan
@ 2025-04-11 23:31 ` Yixun Lan
2025-04-11 23:31 ` [PATCH v8 5/5] riscv: dts: spacemit: add gpio LED for system heartbeat Yixun Lan
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2025-04-11 23:31 UTC (permalink / raw)
To: Bartosz Golaszewski, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Conor Dooley, Paul Walmsley,
Palmer Dabbelt
Cc: Alex Elder, Yangyu Chen, Jisheng Zhang, Jesse Taube,
Inochi Amaoto, Icenowy Zheng, Meng Zhang, linux-gpio, devicetree,
linux-kernel, linux-riscv, spacemit, Yixun Lan
Populate the GPIO node in the device tree for SpacemiT K1 SoC.
Each of 32 pins will act as one bank and map pins to pinctrl controller.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 3 +++
arch/riscv/boot/dts/spacemit/k1.dtsi | 15 +++++++++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index a8eac5517f8578d60cb45214589ccb45ac376b9a..283663647a86ff137917ced8bfe79a129c86342a 100644
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -7,6 +7,9 @@
#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
+/* Map GPIO pin to each bank's <index, offset> */
+#define K1_GPIO(x) (x / 32) (x % 32)
+
&pinctrl {
uart0_2_cfg: uart0-2-cfg {
uart0-2-pins {
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index c670ebf8fa12917aa6493fcd89fdd1409529538b..ff86a02c25f2e0818a48ed56c75e911d8612f6d1 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -404,6 +404,21 @@ uart9: serial@d4017800 {
status = "disabled";
};
+ gpio: gpio@d4019000 {
+ compatible = "spacemit,k1-gpio";
+ reg = <0x0 0xd4019000 0x0 0x100>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ interrupts = <58>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ gpio-ranges = <&pinctrl 0 0 0 32>,
+ <&pinctrl 1 0 32 32>,
+ <&pinctrl 2 0 64 32>,
+ <&pinctrl 3 0 96 32>;
+ };
+
pinctrl: pinctrl@d401e000 {
compatible = "spacemit,k1-pinctrl";
reg = <0x0 0xd401e000 0x0 0x400>;
--
2.49.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v8 5/5] riscv: dts: spacemit: add gpio LED for system heartbeat
2025-04-11 23:31 [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
` (3 preceding siblings ...)
2025-04-11 23:31 ` [PATCH v8 4/5] riscv: dts: spacemit: add " Yixun Lan
@ 2025-04-11 23:31 ` Yixun Lan
2025-04-15 2:32 ` [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
2025-04-17 12:35 ` (subset) " Bartosz Golaszewski
6 siblings, 0 replies; 9+ messages in thread
From: Yixun Lan @ 2025-04-11 23:31 UTC (permalink / raw)
To: Bartosz Golaszewski, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Conor Dooley, Paul Walmsley,
Palmer Dabbelt
Cc: Alex Elder, Yangyu Chen, Jisheng Zhang, Jesse Taube,
Inochi Amaoto, Icenowy Zheng, Meng Zhang, linux-gpio, devicetree,
linux-kernel, linux-riscv, spacemit, Yixun Lan
Leverage GPIO to support system LED to indicate activity of CPUs.
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 1d617b40a2d51ee464b57234d248798aeb218643..816ef1bc358ec490aff184d5915d680dbd9f00cb 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -17,6 +17,17 @@ aliases {
chosen {
stdout-path = "serial0";
};
+
+ leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "sys-led";
+ gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "on";
+ };
+ };
};
&uart0 {
--
2.49.0
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC
2025-04-11 23:31 [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
` (4 preceding siblings ...)
2025-04-11 23:31 ` [PATCH v8 5/5] riscv: dts: spacemit: add gpio LED for system heartbeat Yixun Lan
@ 2025-04-15 2:32 ` Yixun Lan
2025-04-15 7:35 ` Linus Walleij
2025-04-17 12:35 ` (subset) " Bartosz Golaszewski
6 siblings, 1 reply; 9+ messages in thread
From: Yixun Lan @ 2025-04-15 2:32 UTC (permalink / raw)
To: Bartosz Golaszewski, Linus Walleij, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Conor Dooley, Paul Walmsley,
Palmer Dabbelt
Cc: Alex Elder, Yangyu Chen, Jisheng Zhang, Jesse Taube,
Inochi Amaoto, Icenowy Zheng, Meng Zhang, linux-gpio, devicetree,
linux-kernel, linux-riscv, spacemit
Hi Bartosz,
I think this version is good to go, if you agree,
can you take patch [1,2 / 5] through gpio tree?
Hi Palmer,
I believe the change to riscv's defconfig file should
go via riscv tree?
thanks
On 07:31 Sat 12 Apr , Yixun Lan wrote:
> The gpio controller of K1 support basic GPIO functions,
> which capable of enabling as input, output. It can also be used
> as GPIO interrupt which able to detect rising edge, falling edge,
> or both. There are four GPIO ports, each consisting of 32 pins and
> has indepedent register sets, while still sharing IRQ line and clocks.
> The GPIO controller request the two clock sources from APBC block.
>
> Due to first three GPIO ports has interleave register settings, some
> resources (IRQ, clock) are shared by all pins.
>
> The GPIO docs of K1 SoC can be found here, chapter 16.4 GPIO [1]
>
> This patch series has been tested on Bananapi-F3 board,
> with following GPIO cases passed:
> 1) gpio input
> 2) gpio output - set to high, low
> 3) gpio interrupt - rising trigger, falling trigger, both edge trigger
>
> This version should resolve DT related concern in V4, and register each bank as
> indepedent gpio chip in driver, no more sub children gpio DT node needed.
>
> Please notice in this version, the reset property is added, but optional.
> as I see no need to activate it in driver, instead I suspect it may
> break cases if bootloader did some prerequisite settings, so I'm leaving
> it for future implementation if really necessary.
>
> The DT part (patches 4, 5) has no clock property populated which result
> some DT warnings, I will fix it and re-spin the DT part once clock driver merged,
> so it's included here for completeness only, please ignore these warnings.
>
> Link: https://developer.spacemit.com/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf [1]
> Link: https://lore.kernel.org/all/20240730-k1-01-basic-dt-v5-0-98263aae83be@gentoo.org [2]
> Link: https://lore.kernel.org/all/20241016-02-k1-pinctrl-v5-0-03d395222e4f@gentoo.org/ [3]
> Link: https://lore.kernel.org/all/20250218-gpio-ranges-fourcell-v1-0-b1f3db6c8036@linaro.org [4]
> Link: https://lore.kernel.org/all/20250225-gpio-ranges-fourcell-v3-0-860382ba4713@linaro.org [5]
> Signed-off-by: Yixun Lan <dlan@gentoo.org>
> ---
> Changes in v8:
> - rebased to v6.15-rc1
> - adjust dt-binding/code to request clocks
> - add reset property
> - call irq_domain_update_bus_token() to support threecells interrupt mode
> - use devm_platform_ioremap_resource(), so drop "struct resource"
> - fix Kconfig
> - select GPIO_GENERIC as calling bgpio_init()
> - change to tristate, make it possible to build as module
> - adjust defconfig to enable gpio
> - Link to v7: https://lore.kernel.org/r/20250226-03-k1-gpio-v7-0-be489c4a609b@gentoo.org
>
> Changes in v7:
> - dt-binding: fix 80 column, drop unneeded dependencies
> - tested with patch v3 of "gpiolib: of: Handle threecell gpios" [5]
> - collect review tags
> - Link to v6: https://lore.kernel.org/r/20250223-03-k1-gpio-v6-0-db2e4adeef1c@gentoo.org
>
> Changes in v6:
> - rebase to threecell gpio patch which proposed by LinusW at [4],
> drop unneeded *xlate(), *add_pin_range() function
> - add SPACEMIT prefix to macro
> - adjust register comments
> - drop 'index' member, instead calculate from offset
> - add IRQCHIP_SKIP_SET_WAKE as gpio doesn't support irq wake up
> - drop #ifdef CONFIG_OF_GPIO
> - move interrupt mask disabling/enabling into irq_*mask()
> - Link to v5: https://lore.kernel.org/r/20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org
>
> Changes in v5:
> - export add_pin_range() from gpio core, support to add custom version
> - change to 3 gpio cells, model to <bank number>, <bank offset>, <gpio flag>
> - fold children DT nodes into parent
> - Link to v4: https://lore.kernel.org/r/20250121-03-k1-gpio-v4-0-4641c95c0194@gentoo.org
>
> Changes in v4:
> - gpio: re-construct gpio as four independent ports, also leverage gpio mmio API
> - gpio interrupt: convert to generic gpio irqchip
> - Link to v3: https://lore.kernel.org/r/20241225-03-k1-gpio-v3-0-27bb7b441d62@gentoo.org
>
> Changes in v3:
> - dt: drop ranges, interrupt-names property
> - Link to v2: https://lore.kernel.org/r/20241219-03-k1-gpio-v2-0-28444fd221cd@gentoo.org
>
> Changes in v2:
> - address dt-bindings comments, simplify example
> - rebase to 6.13-rc3
> - Link to v1: https://lore.kernel.org/r/20240904-03-k1-gpio-v1-0-6072ebeecae0@gentoo.org
>
> ---
> Yixun Lan (5):
> dt-bindings: gpio: spacemit: add support for K1 SoC
> gpio: spacemit: add support for K1 SoC
> riscv: defconfig: spacemit: enable gpio support for K1 SoC
> riscv: dts: spacemit: add gpio support for K1 SoC
> riscv: dts: spacemit: add gpio LED for system heartbeat
>
> .../devicetree/bindings/gpio/spacemit,k1-gpio.yaml | 96 +++++++
> arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 11 +
> arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 3 +
> arch/riscv/boot/dts/spacemit/k1.dtsi | 15 ++
> arch/riscv/configs/defconfig | 1 +
> drivers/gpio/Kconfig | 9 +
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-spacemit-k1.c | 293 +++++++++++++++++++++
> 8 files changed, 429 insertions(+)
> ---
> base-commit: 0af2f6be1b4281385b618cb86ad946eded089ac8
> change-id: 20240828-03-k1-gpio-61bf92f9032c
>
> Best regards,
> --
> Yixun Lan
>
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC
2025-04-15 2:32 ` [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
@ 2025-04-15 7:35 ` Linus Walleij
0 siblings, 0 replies; 9+ messages in thread
From: Linus Walleij @ 2025-04-15 7:35 UTC (permalink / raw)
To: Yixun Lan
Cc: Bartosz Golaszewski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Alex Elder, Yangyu Chen, Jisheng Zhang, Jesse Taube,
Inochi Amaoto, Icenowy Zheng, Meng Zhang, linux-gpio, devicetree,
linux-kernel, linux-riscv, spacemit
On Tue, Apr 15, 2025 at 4:32 AM Yixun Lan <dlan@gentoo.org> wrote:
> Hi Bartosz,
> I think this version is good to go, if you agree,
> can you take patch [1,2 / 5] through gpio tree?
I agree with this, it's the final piece making use of all the nice
infrastructure we put in for threecell GPIO and threecell
IRQ so let's merge patches 1+2!
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: (subset) [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC
2025-04-11 23:31 [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
` (5 preceding siblings ...)
2025-04-15 2:32 ` [PATCH v8 0/5] riscv: spacemit: add gpio support for K1 SoC Yixun Lan
@ 2025-04-17 12:35 ` Bartosz Golaszewski
6 siblings, 0 replies; 9+ messages in thread
From: Bartosz Golaszewski @ 2025-04-17 12:35 UTC (permalink / raw)
To: Linus Walleij, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Conor Dooley, Paul Walmsley, Palmer Dabbelt, Yixun Lan
Cc: Bartosz Golaszewski, Alex Elder, Yangyu Chen, Jisheng Zhang,
Jesse Taube, Inochi Amaoto, Icenowy Zheng, Meng Zhang, linux-gpio,
devicetree, linux-kernel, linux-riscv, spacemit
On Sat, 12 Apr 2025 07:31:27 +0800, Yixun Lan wrote:
> The gpio controller of K1 support basic GPIO functions,
> which capable of enabling as input, output. It can also be used
> as GPIO interrupt which able to detect rising edge, falling edge,
> or both. There are four GPIO ports, each consisting of 32 pins and
> has indepedent register sets, while still sharing IRQ line and clocks.
> The GPIO controller request the two clock sources from APBC block.
>
> [...]
Applied, thanks!
[1/5] dt-bindings: gpio: spacemit: add support for K1 SoC
https://git.kernel.org/brgl/linux/c/378ce04c79d14c730fcee6db9f3076da4078b65f
[2/5] gpio: spacemit: add support for K1 SoC
https://git.kernel.org/brgl/linux/c/6149376c9ad1777aa4214e13d844f12f88e22dea
Best regards,
--
Bartosz Golaszewski <brgl@bgdev.pl>
^ permalink raw reply [flat|nested] 9+ messages in thread