[PATCH v9 0/3] riscv: spacemit: add gpio support for K1 SoC

[PATCH v9 0/3] riscv: spacemit: add gpio support for K1 SoC

[Yixun Lan]

The gpio controller of K1 support basic GPIO functions,
which capable of enabling as input, output. It can also be used
as GPIO interrupt which able to detect rising edge, falling edge,
or both. There are four GPIO ports, each consisting of 32 pins and
has indepedent register sets, while still sharing IRQ line and clocks.
The GPIO controller request the two clock sources from APBC block.

Due to first three GPIO ports has interleave register settings, some
resources (IRQ, clock) are shared by all pins.

The GPIO docs of K1 SoC can be found here, chapter 16.4 GPIO [1]

This patch series has been tested on Bananapi-F3 board,
with following GPIO cases passed:
 1) gpio input
 2) gpio output - set to high, low
 3) gpio interrupt - rising trigger, falling trigger, both edge trigger

This version should resolve DT related concern in V4, and register each bank as
indepedent gpio chip in driver, no more sub children gpio DT node needed.

Please notice in this version, the reset property is added, but optional.
as I see no need to activate it in driver, instead I suspect it may
break cases if bootloader did some prerequisite settings, so I'm leaving
it for future implementation if really necessary.

Add clock property and rebase patch on top of SpacemiT's k1/dt-for-next branch

Link: https://developer.spacemit.com/documentation?token=Rn9Kw3iFHirAMgkIpTAcV2Arnkf [1]
Link: https://lore.kernel.org/all/20240730-k1-01-basic-dt-v5-0-98263aae83be@gentoo.org [2]
Link: https://lore.kernel.org/all/20241016-02-k1-pinctrl-v5-0-03d395222e4f@gentoo.org/ [3]
Link: https://lore.kernel.org/all/20250218-gpio-ranges-fourcell-v1-0-b1f3db6c8036@linaro.org [4]
Link: https://lore.kernel.org/all/20250225-gpio-ranges-fourcell-v3-0-860382ba4713@linaro.org [5]
Link: https://lore.kernel.org/all/2174489329731.7849.17910336598453828998.b4-ty@bgdev.pl [6]
Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
Changes in v9:
- drop patch 1,2 from v8 which already merged by gpio tree [6]
- add clock property to gpio node
- Link to v8: https://lore.kernel.org/r/20250412-03-k1-gpio-v8-0-1c6862d272ec@gentoo.org

Changes in v8:
- rebased to v6.15-rc1
- adjust dt-binding/code to request clocks
- add reset property
- call irq_domain_update_bus_token() to support threecells interrupt mode
- use devm_platform_ioremap_resource(), so drop "struct resource"
- fix Kconfig
  - select GPIO_GENERIC as calling bgpio_init()
  - change to tristate, make it possible to build as module
- adjust defconfig to enable gpio 
- Link to v7: https://lore.kernel.org/r/20250226-03-k1-gpio-v7-0-be489c4a609b@gentoo.org

Changes in v7:
- dt-binding: fix 80 column, drop unneeded dependencies
- tested with patch v3 of "gpiolib: of: Handle threecell gpios" [5]
- collect review tags
- Link to v6: https://lore.kernel.org/r/20250223-03-k1-gpio-v6-0-db2e4adeef1c@gentoo.org

Changes in v6:
- rebase to threecell gpio patch which proposed by LinusW at [4], 
  drop unneeded *xlate(), *add_pin_range() function
- add SPACEMIT prefix to macro
- adjust register comments
- drop 'index' member, instead calculate from offset
- add IRQCHIP_SKIP_SET_WAKE as gpio doesn't support irq wake up
- drop #ifdef CONFIG_OF_GPIO
- move interrupt mask disabling/enabling into irq_*mask()
- Link to v5: https://lore.kernel.org/r/20250217-03-k1-gpio-v5-0-2863ec3e7b67@gentoo.org

Changes in v5:
- export add_pin_range() from gpio core, support to add custom version
- change to 3 gpio cells, model to <bank number>, <bank offset>, <gpio flag>
- fold children DT nodes into parent
- Link to v4: https://lore.kernel.org/r/20250121-03-k1-gpio-v4-0-4641c95c0194@gentoo.org

Changes in v4:
- gpio: re-construct gpio as four independent ports, also leverage gpio mmio API
- gpio interrupt: convert to generic gpio irqchip
- Link to v3: https://lore.kernel.org/r/20241225-03-k1-gpio-v3-0-27bb7b441d62@gentoo.org

Changes in v3:
- dt: drop ranges, interrupt-names property
- Link to v2: https://lore.kernel.org/r/20241219-03-k1-gpio-v2-0-28444fd221cd@gentoo.org

Changes in v2:
- address dt-bindings comments, simplify example
- rebase to 6.13-rc3 
- Link to v1: https://lore.kernel.org/r/20240904-03-k1-gpio-v1-0-6072ebeecae0@gentoo.org

---
Yixun Lan (3):
      riscv: defconfig: spacemit: enable gpio support for K1 SoC
      riscv: dts: spacemit: add gpio support for K1 SoC
      riscv: dts: spacemit: add gpio LED for system heartbeat

 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 11 +++++++++++
 arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi    |  3 +++
 arch/riscv/boot/dts/spacemit/k1.dtsi            | 18 ++++++++++++++++++
 arch/riscv/configs/defconfig                    |  1 +
 4 files changed, 33 insertions(+)
---
base-commit: 279d51ad9f6dc0c667f6f141a669b2c921277d1a
change-id: 20240828-03-k1-gpio-61bf92f9032c

Best regards,
-- 
Yixun Lan

[PATCH v9 1/3] riscv: defconfig: spacemit: enable gpio support for K1 SoC

[Yixun Lan]

Enable GPIO support, in order to activate follow-up GPIO LED,
and ethernet reset pin.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 3c8e16d71e175e0e4c27136c31761127ce6e1602..b8899d59dd345c50d877829c05d0330f2986895c 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -169,6 +169,7 @@ CONFIG_PINCTRL_SOPHGO_SG2002=y
 CONFIG_PINCTRL_TH1520=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_SIFIVE=y
+CONFIG_GPIO_SPACEMIT_K1=y
 CONFIG_POWER_RESET_GPIO_RESTART=y
 CONFIG_SENSORS_SFCTEMP=m
 CONFIG_CPU_THERMAL=y

-- 
2.49.0

[PATCH v9 2/3] riscv: dts: spacemit: add gpio support for K1 SoC

[Yixun Lan]

Populate the GPIO node in the device tree for SpacemiT K1 SoC.
Each of 32 pins will act as one bank and map pins to pinctrl controller.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi |  3 +++
 arch/riscv/boot/dts/spacemit/k1.dtsi         | 18 ++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index a8eac5517f8578d60cb45214589ccb45ac376b9a..283663647a86ff137917ced8bfe79a129c86342a 100644
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -7,6 +7,9 @@
 
 #define K1_PADCONF(pin, func) (((pin) << 16) | (func))
 
+/* Map GPIO pin to each bank's <index, offset> */
+#define K1_GPIO(x)	(x / 32) (x % 32)
+
 &pinctrl {
 	uart0_2_cfg: uart0-2-cfg {
 		uart0-2-pins {
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 584f0dbc60f5b0d078c7127cc4021ad6022cb182..fbc4f1965c52c4f1aa80eaa0cda97a4be438c4f2 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -447,6 +447,24 @@ uart9: serial@d4017800 {
 			status = "disabled";
 		};
 
+		gpio: gpio@d4019000 {
+			compatible = "spacemit,k1-gpio";
+			reg = <0x0 0xd4019000 0x0 0x100>;
+			clocks = <&syscon_apbc CLK_GPIO>,
+				 <&syscon_apbc CLK_GPIO_BUS>;
+			clock-names = "core", "bus";
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupts = <58>;
+			interrupt-parent = <&plic>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			gpio-ranges = <&pinctrl 0 0 0 32>,
+				      <&pinctrl 1 0 32 32>,
+				      <&pinctrl 2 0 64 32>,
+				      <&pinctrl 3 0 96 32>;
+		};
+
 		pinctrl: pinctrl@d401e000 {
 			compatible = "spacemit,k1-pinctrl";
 			reg = <0x0 0xd401e000 0x0 0x400>;

-- 
2.49.0

[PATCH v9 3/3] riscv: dts: spacemit: add gpio LED for system heartbeat

[Yixun Lan]

Leverage GPIO to support system LED to indicate activity of CPUs.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
 arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 1d617b40a2d51ee464b57234d248798aeb218643..816ef1bc358ec490aff184d5915d680dbd9f00cb 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -17,6 +17,17 @@ aliases {
 	chosen {
 		stdout-path = "serial0";
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1 {
+			label = "sys-led";
+			gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+		};
+	};
 };
 
 &uart0 {

-- 
2.49.0

Re: [PATCH v9 1/3] riscv: defconfig: spacemit: enable gpio support for K1 SoC

[Conor Dooley]

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On Thu, Apr 24, 2025 at 05:40:49PM +0800, Yixun Lan wrote:
> Enable GPIO support, in order to activate follow-up GPIO LED,
> and ethernet reset pin.
> 
> Signed-off-by: Yixun Lan <dlan@gentoo.org>

Do you want me to grab this patch, or do you have a defconfig branch to
put it on?

> ---
>  arch/riscv/configs/defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index 3c8e16d71e175e0e4c27136c31761127ce6e1602..b8899d59dd345c50d877829c05d0330f2986895c 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -169,6 +169,7 @@ CONFIG_PINCTRL_SOPHGO_SG2002=y
>  CONFIG_PINCTRL_TH1520=y
>  CONFIG_GPIO_DWAPB=y
>  CONFIG_GPIO_SIFIVE=y
> +CONFIG_GPIO_SPACEMIT_K1=y
>  CONFIG_POWER_RESET_GPIO_RESTART=y
>  CONFIG_SENSORS_SFCTEMP=m
>  CONFIG_CPU_THERMAL=y
> 
> -- 
> 2.49.0
> 

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Re: [PATCH v9 1/3] riscv: defconfig: spacemit: enable gpio support for K1 SoC

[Yixun Lan]

Hi Conor,

On 16:22 Thu 24 Apr     , Conor Dooley wrote:
> On Thu, Apr 24, 2025 at 05:40:49PM +0800, Yixun Lan wrote:
> > Enable GPIO support, in order to activate follow-up GPIO LED,
> > and ethernet reset pin.
> > 
> > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> 
> Do you want me to grab this patch, or do you have a defconfig branch to
> put it on?
> 
Yes, I'd appreciate if you willing to pick it, to avoid potential conflicts?
(I currently do not maintain defconfig branch)

BTW, we might have few more in this cycle, e.g. - clock, reset

Thanks

-- 
Yixun Lan (dlan)

Re: [PATCH v9 1/3] riscv: defconfig: spacemit: enable gpio support for K1 SoC

[Conor Dooley]

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On Fri, Apr 25, 2025 at 12:04:06AM +0000, Yixun Lan wrote:
> Hi Conor,
> 
> On 16:22 Thu 24 Apr     , Conor Dooley wrote:
> > On Thu, Apr 24, 2025 at 05:40:49PM +0800, Yixun Lan wrote:
> > > Enable GPIO support, in order to activate follow-up GPIO LED,
> > > and ethernet reset pin.
> > > 
> > > Signed-off-by: Yixun Lan <dlan@gentoo.org>
> > 
> > Do you want me to grab this patch, or do you have a defconfig branch to
> > put it on?
> > 
> Yes, I'd appreciate if you willing to pick it, to avoid potential conflicts?

Sure, done.

> (I currently do not maintain defconfig branch)
> 
> BTW, we might have few more in this cycle, e.g. - clock, reset

Cool, just poke me if you need them picked up. I should see an email,
but failing that, @ me on your IRC channel.

Cheers,
Conor.

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Re: (subset) [PATCH v9 0/3] riscv: spacemit: add gpio support for K1 SoC

[Yixun Lan]

On Thu, 24 Apr 2025 17:40:48 +0800, Yixun Lan wrote:
> The gpio controller of K1 support basic GPIO functions,
> which capable of enabling as input, output. It can also be used
> as GPIO interrupt which able to detect rising edge, falling edge,
> or both. There are four GPIO ports, each consisting of 32 pins and
> has indepedent register sets, while still sharing IRQ line and clocks.
> The GPIO controller request the two clock sources from APBC block.
> 
> [...]

Applied, thanks!

[2/3] riscv: dts: spacemit: add gpio support for K1 SoC
      https://github.com/spacemit-com/linux/commit/39efc98da7c60cad066a18049a98d41b8542f44a
[3/3] riscv: dts: spacemit: add gpio LED for system heartbeat
      https://github.com/spacemit-com/linux/commit/cb9c3aeae509b36afbdf46942a7a0a0dfc856ce7

Best regards,
-- 
Yixun Lan