[PATCH v3 0/3] riscv: sophgo: add mailbox support for CV18XX series SoC

[PATCH v3 0/3] riscv: sophgo: add mailbox support for CV18XX series SoC

[Junhui Liu]

Sophgo CV18XX series SoC has a mailbox module used to pass messages to
asymmetric processors. It has a total of 8 channels, each channel has a
length of 64bit.

Tested on Milk-V Duo with CV1800B SoC, Milk-V Duo256M with SG2002 SoC
and Milk-V Duo S with SG2000 SoC by the mailbox-test client.

---
Changes in v3:
- Update cv18x to CV18XX in commit messages and descriptions.
- Remove the `interrupt-names` property in dt-bindings, dts and driver.
- Move the mailbox node in dts to satisfy the address order.
- Remove `OF` dependency in Kconfig and the driver.
- Add copyright in the driver.
- Reorder the processes in dt-bindings and change the `RECV_CPU` macro
  definition from 2 to 1 in the driver.
- Clean up and improve macro definitions and register access methods in
  the driver.
- Improve the return value handling in the interrupt handler functions.
- Implement the `cv1800_last_tx_done` function.
- Link to v2: https://lore.kernel.org/r/SYBP282MB223825D5903777B937A8A377C4A02@SYBP282MB2238.AUSP282.PROD.OUTLOOK.COM

Changes in v2:
- drop 'recvid' 'sender' in dt-bindings
- fix compatible to 'cv1800-mailbox', and change filenames too
- change #mbox-cell to 2, for <channel tagert_cpu>
- add struct cv1800_mbox_chan_priv and function cv1800_mbox_xlate to extract
  informations in mbox devicetree node of mailbox client
- Link to v1: https://lore.kernel.org/r/SYBP282MB2238DE0DA19C6EF411B2356CC4CE2@SYBP282MB2238.AUSP282.PROD.OUTLOOK.COM

---
Yuntao Dai (3):
      dt-bindings: mailbox: add Sophgo CV18XX series SoC
      riscv: dts: add mailbox for Sophgo CV18XX series SoC
      mailbox: sophgo: add mailbox driver for CV18XX series SoC

 .../bindings/mailbox/sophgo,cv1800b-mailbox.yaml   |  57 ++++++
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi             |   7 +
 drivers/mailbox/Kconfig                            |  10 +
 drivers/mailbox/Makefile                           |   2 +
 drivers/mailbox/cv1800-mailbox.c                   | 218 +++++++++++++++++++++
 5 files changed, 294 insertions(+)
---
base-commit: b4432656b36e5cc1d50a1f2dc15357543add530e
change-id: 20250421-cv18xx-mbox-6282d1e1734c

Best regards,
-- 
Junhui Liu <junhui.liu@pigmoral.tech>

[PATCH v3 1/3] dt-bindings: mailbox: add Sophgo CV18XX series SoC

[Junhui Liu]

From: Yuntao Dai <d1581209858@live.com>

Introduce the mailbox module for CV18XX series SoC, which is responsible
for interchanging messages between asymmetric processors.

Signed-off-by: Yuntao Dai <d1581209858@live.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 .../bindings/mailbox/sophgo,cv1800b-mailbox.yaml   | 57 ++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..5815dc02189c973d681f5b4ff22a9fb7536802b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sophgo CV1800/SG2000 mailbox controller
+
+maintainers:
+  - Yuntao Dai <d1581209858@live.com>
+  - Junhui Liu <junhui.liu@pigmoral.tech>
+
+description: |
+  Mailboxes integrated in Sophgo CV1800/SG2000 SoCs have 8 channels, each
+  shipping an 8-byte FIFO. Any processor can write to an arbitrary channel
+  and raise interrupts to receivers. Sending messages to itself is also
+  supported.
+  Sophgo CV1800/SG2000 SoCs include the following processors, numbered as:
+  <0> Cortex-A53 (Only available on CV181X/SG200X)
+  <1> C906B
+  <2> C906L
+  <3> 8051
+
+properties:
+  compatible:
+    const: sophgo,cv1800b-mailbox
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  "#mbox-cells":
+    const: 2
+    description:
+      The first cell indicates the channel index (0-7), the second cell
+      indicates the target processor ID (0-3) to which messages are sent.
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - "#mbox-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+
+    mailbox@1900000 {
+        compatible = "sophgo,cv1800b-mailbox";
+        reg = <0x01900000 0x1000>;
+        interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
+        #mbox-cells = <2>;
+    };

-- 
2.49.0

Re: [PATCH v3 1/3] dt-bindings: mailbox: add Sophgo CV18XX series SoC

[Conor Dooley]

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On Mon, Apr 28, 2025 at 08:39:44PM +0800, Junhui Liu wrote:
> From: Yuntao Dai <d1581209858@live.com>
> 
> Introduce the mailbox module for CV18XX series SoC, which is responsible
> for interchanging messages between asymmetric processors.
> 
> Signed-off-by: Yuntao Dai <d1581209858@live.com>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
>  .../bindings/mailbox/sophgo,cv1800b-mailbox.yaml   | 57 ++++++++++++++++++++++
>  1 file changed, 57 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..5815dc02189c973d681f5b4ff22a9fb7536802b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Sophgo CV1800/SG2000 mailbox controller
> +
> +maintainers:
> +  - Yuntao Dai <d1581209858@live.com>
> +  - Junhui Liu <junhui.liu@pigmoral.tech>
> +
> +description: |
> +  Mailboxes integrated in Sophgo CV1800/SG2000 SoCs have 8 channels, each
> +  shipping an 8-byte FIFO. Any processor can write to an arbitrary channel
> +  and raise interrupts to receivers. Sending messages to itself is also
> +  supported.

> +  Sophgo CV1800/SG2000 SoCs include the following processors, numbered as:
> +  <0> Cortex-A53 (Only available on CV181X/SG200X)
> +  <1> C906B
> +  <2> C906L
> +  <3> 8051

I think this section should be moved to the mbox-cells property, since it
is describing how to use the mboxes property.

> +
> +properties:
> +  compatible:
> +    const: sophgo,cv1800b-mailbox

Remind me, why only a cv1800b compatible when you also mention sg2000?
Rebranding of the same SoC, or something like that?

Cheers,
Conor.

> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  "#mbox-cells":
> +    const: 2
> +    description:
> +      The first cell indicates the channel index (0-7), the second cell
> +      indicates the target processor ID (0-3) to which messages are sent.
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - "#mbox-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +
> +    mailbox@1900000 {
> +        compatible = "sophgo,cv1800b-mailbox";
> +        reg = <0x01900000 0x1000>;
> +        interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
> +        #mbox-cells = <2>;
> +    };
> 
> -- 
> 2.49.0
> 

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Re: [PATCH v3 1/3] dt-bindings: mailbox: add Sophgo CV18XX series SoC

[Junhui Liu]

Hi Conor,
Thanks for your review.

On 28/04/2025 17:52, Conor Dooley wrote:
> On Mon, Apr 28, 2025 at 08:39:44PM +0800, Junhui Liu wrote:
>> From: Yuntao Dai <d1581209858@live.com>
>> 
>> Introduce the mailbox module for CV18XX series SoC, which is responsible
>> for interchanging messages between asymmetric processors.
>> 
>> Signed-off-by: Yuntao Dai <d1581209858@live.com>
>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>> ---
>>  .../bindings/mailbox/sophgo,cv1800b-mailbox.yaml   | 57 ++++++++++++++++++++++
>>  1 file changed, 57 insertions(+)
>> 
>> diff --git a/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..5815dc02189c973d681f5b4ff22a9fb7536802b9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mailbox/sophgo,cv1800b-mailbox.yaml
>> @@ -0,0 +1,57 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mailbox/sophgo,cv1800b-mailbox.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Sophgo CV1800/SG2000 mailbox controller
>> +
>> +maintainers:
>> +  - Yuntao Dai <d1581209858@live.com>
>> +  - Junhui Liu <junhui.liu@pigmoral.tech>
>> +
>> +description: |
>> +  Mailboxes integrated in Sophgo CV1800/SG2000 SoCs have 8 channels, each
>> +  shipping an 8-byte FIFO. Any processor can write to an arbitrary channel
>> +  and raise interrupts to receivers. Sending messages to itself is also
>> +  supported.
> 
>> +  Sophgo CV1800/SG2000 SoCs include the following processors, numbered as:
>> +  <0> Cortex-A53 (Only available on CV181X/SG200X)
>> +  <1> C906B
>> +  <2> C906L
>> +  <3> 8051
> 
> I think this section should be moved to the mbox-cells property, since it
> is describing how to use the mboxes property.

You're right. I will move it to the mbox-cells property.

> 
>> +
>> +properties:
>> +  compatible:
>> +    const: sophgo,cv1800b-mailbox
> 
> Remind me, why only a cv1800b compatible when you also mention sg2000?
> Rebranding of the same SoC, or something like that?

Yes, this is some kind of rebranding behavior, as discussed previously
in [1].

And since the behavior of mailbox is consistent between CV18XX/SG200X
when using C906B RISC-V core (Arm-A53 and C906B can't run at the same
time), I only added sophgo,cv1800b-mailbox as a common compatible.

Things will be slightly different when using Arm-A53 core, the receiver
id in the driver will be different. I think a compatible like
sophgo,sg2000-mailbox-a53 can be added to handle it when the A53 core is
ready [2].

link: https://lore.kernel.org/linux-riscv/20240116-music-luckiness-3220a9efdbbf@spud/ [1]
link: https://lore.kernel.org/all/20250316185640.3750873-1-alexander.sverdlin@gmail.com/ [2]

> 
> Cheers,
> Conor.
> 
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts:
>> +    maxItems: 1
>> +
>> +  "#mbox-cells":
>> +    const: 2
>> +    description:
>> +      The first cell indicates the channel index (0-7), the second cell
>> +      indicates the target processor ID (0-3) to which messages are sent.
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - interrupts
>> +  - "#mbox-cells"
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/irq.h>
>> +
>> +    mailbox@1900000 {
>> +        compatible = "sophgo,cv1800b-mailbox";
>> +        reg = <0x01900000 0x1000>;
>> +        interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
>> +        #mbox-cells = <2>;
>> +    };
>> 
>>

-- 
Best regards,
Junhui Liu

[PATCH v3 2/3] riscv: dts: add mailbox for Sophgo CV18XX series SoC

[Junhui Liu]

From: Yuntao Dai <d1581209858@live.com>

Add mailbox node for Sophgo CV18XX series SoC.

Signed-off-by: Yuntao Dai <d1581209858@live.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index c18822ec849f353bc296965d2d600a3df314cff6..f7277288f03c024039054bdc4176fc95c2c8be52 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -55,6 +55,13 @@ soc {
 		dma-noncoherent;
 		ranges;
 
+		mailbox: mailbox@1900000 {
+			compatible = "sophgo,cv1800b-mailbox";
+			reg = <0x01900000 0x1000>;
+			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
+			#mbox-cells = <2>;
+		};
+
 		clk: clock-controller@3002000 {
 			reg = <0x03002000 0x1000>;
 			clocks = <&osc>;

-- 
2.49.0

Re: [PATCH v3 2/3] riscv: dts: add mailbox for Sophgo CV18XX series SoC

[Conor Dooley]

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On Mon, Apr 28, 2025 at 08:39:45PM +0800, Junhui Liu wrote:
> From: Yuntao Dai <d1581209858@live.com>
> 
> Add mailbox node for Sophgo CV18XX series SoC.
> 
> Signed-off-by: Yuntao Dai <d1581209858@live.com>
> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> ---
>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index c18822ec849f353bc296965d2d600a3df314cff6..f7277288f03c024039054bdc4176fc95c2c8be52 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -55,6 +55,13 @@ soc {
>  		dma-noncoherent;
>  		ranges;
>  
> +		mailbox: mailbox@1900000 {
> +			compatible = "sophgo,cv1800b-mailbox";
> +			reg = <0x01900000 0x1000>;
> +			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
> +			#mbox-cells = <2>;
> +		};

No user added here, is there another series in the works that adds a
user of the mailbox?

> +
>  		clk: clock-controller@3002000 {
>  			reg = <0x03002000 0x1000>;
>  			clocks = <&osc>;
> 
> -- 
> 2.49.0
> 

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Re: [PATCH v3 2/3] riscv: dts: add mailbox for Sophgo CV18XX series SoC

[Junhui Liu]

Hi Conor,
Thanks for you review.

The previous email accidentally lost some Cc lists :(, I'm sorry to
harass you.

On 28/04/2025 17:55, Conor Dooley wrote:
> On Mon, Apr 28, 2025 at 08:39:45PM +0800, Junhui Liu wrote:
>> From: Yuntao Dai <d1581209858@live.com>
>> 
>> Add mailbox node for Sophgo CV18XX series SoC.
>> 
>> Signed-off-by: Yuntao Dai <d1581209858@live.com>
>> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>> ---
>>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 +++++++
>>  1 file changed, 7 insertions(+)
>> 
>> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> index c18822ec849f353bc296965d2d600a3df314cff6..f7277288f03c024039054bdc4176fc95c2c8be52 100644
>> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> @@ -55,6 +55,13 @@ soc {
>>  		dma-noncoherent;
>>  		ranges;
>>  
>> +		mailbox: mailbox@1900000 {
>> +			compatible = "sophgo,cv1800b-mailbox";
>> +			reg = <0x01900000 0x1000>;
>> +			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
>> +			#mbox-cells = <2>;
>> +		};
> 
> No user added here, is there another series in the works that adds a
> user of the mailbox?
> 

There isn't an actual user node in this specific patch. I used a
`mailbox-test` node to verify the functionality in this patch series.

The intended user for this mailbox is the `remoteproc` node. I plan to
submit the `remoteproc` driver patches once the corresponding reset
driver [1] is ready and merged.

link: https://lore.kernel.org/linux-riscv/20250209122936.2338821-1-inochiama@gmail.com/ [1]

>> +
>>  		clk: clock-controller@3002000 {
>>  			reg = <0x03002000 0x1000>;
>>  			clocks = <&osc>;
>> 
>>

-- 
Best regards,
Junhui Liu

Re: [PATCH v3 2/3] riscv: dts: add mailbox for Sophgo CV18XX series SoC

[Inochi Amaoto]

On Tue, Apr 29, 2025 at 02:44:10AM +0000, Junhui Liu wrote:
> Hi Conor,
> Thanks for you review.
> 
> The previous email accidentally lost some Cc lists :(, I'm sorry to
> harass you.
> 
> On 28/04/2025 17:55, Conor Dooley wrote:
> > On Mon, Apr 28, 2025 at 08:39:45PM +0800, Junhui Liu wrote:
> >> From: Yuntao Dai <d1581209858@live.com>
> >> 
> >> Add mailbox node for Sophgo CV18XX series SoC.
> >> 
> >> Signed-off-by: Yuntao Dai <d1581209858@live.com>
> >> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
> >> ---
> >>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 +++++++
> >>  1 file changed, 7 insertions(+)
> >> 
> >> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >> index c18822ec849f353bc296965d2d600a3df314cff6..f7277288f03c024039054bdc4176fc95c2c8be52 100644
> >> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> >> @@ -55,6 +55,13 @@ soc {
> >>  		dma-noncoherent;
> >>  		ranges;
> >>  
> >> +		mailbox: mailbox@1900000 {
> >> +			compatible = "sophgo,cv1800b-mailbox";
> >> +			reg = <0x01900000 0x1000>;
> >> +			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
> >> +			#mbox-cells = <2>;
> >> +		};
> > 
> > No user added here, is there another series in the works that adds a
> > user of the mailbox?
> > 
> 
> There isn't an actual user node in this specific patch. I used a
> `mailbox-test` node to verify the functionality in this patch series.
> 

I am happy to see the way you test it. Can you add it to the cover?

> The intended user for this mailbox is the `remoteproc` node. I plan to
> submit the `remoteproc` driver patches once the corresponding reset
> driver [1] is ready and merged.
> 
> link: https://lore.kernel.org/linux-riscv/20250209122936.2338821-1-inochiama@gmail.com/ [1]
> 

I will submit a version for this in the next rc1. I think you can submit
you remoteproc patch in RFC to get it reviewed.

Regards,
Inochi

Re: [PATCH v3 2/3] riscv: dts: add mailbox for Sophgo CV18XX series SoC

[Junhui Liu]

Hi Inochi,

On 07/05/2025 20:12, Inochi Amaoto wrote:
> On Tue, Apr 29, 2025 at 02:44:10AM +0000, Junhui Liu wrote:
>> Hi Conor,
>> Thanks for you review.
>> 
>> The previous email accidentally lost some Cc lists :(, I'm sorry to
>> harass you.
>> 
>> On 28/04/2025 17:55, Conor Dooley wrote:
>> > On Mon, Apr 28, 2025 at 08:39:45PM +0800, Junhui Liu wrote:
>> >> From: Yuntao Dai <d1581209858@live.com>
>> >> 
>> >> Add mailbox node for Sophgo CV18XX series SoC.
>> >> 
>> >> Signed-off-by: Yuntao Dai <d1581209858@live.com>
>> >> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
>> >> ---
>> >>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 7 +++++++
>> >>  1 file changed, 7 insertions(+)
>> >> 
>> >> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> >> index c18822ec849f353bc296965d2d600a3df314cff6..f7277288f03c024039054bdc4176fc95c2c8be52 100644
>> >> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> >> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> >> @@ -55,6 +55,13 @@ soc {
>> >>  		dma-noncoherent;
>> >>  		ranges;
>> >>  
>> >> +		mailbox: mailbox@1900000 {
>> >> +			compatible = "sophgo,cv1800b-mailbox";
>> >> +			reg = <0x01900000 0x1000>;
>> >> +			interrupts = <101 IRQ_TYPE_LEVEL_HIGH>;
>> >> +			#mbox-cells = <2>;
>> >> +		};
>> > 
>> > No user added here, is there another series in the works that adds a
>> > user of the mailbox?
>> > 
>> 
>> There isn't an actual user node in this specific patch. I used a
>> `mailbox-test` node to verify the functionality in this patch series.
>> 
> 
> I am happy to see the way you test it. Can you add it to the cover?

Sure, I will post the testing process to the cover letter in the next
version.

> 
>> The intended user for this mailbox is the `remoteproc` node. I plan to
>> submit the `remoteproc` driver patches once the corresponding reset
>> driver [1] is ready and merged.
>> 
>> link: https://lore.kernel.org/linux-riscv/20250209122936.2338821-1-inochiama@gmail.com/ [1]
>> 
> 
> I will submit a version for this in the next rc1. I think you can submit
> you remoteproc patch in RFC to get it reviewed.

ok, thanks.

> 
> Regards,
> Inochi

-- 
Best regards,
Junhui Liu

[PATCH v3 3/3] mailbox: sophgo: add mailbox driver for CV18XX series SoC

[Junhui Liu]

From: Yuntao Dai <d1581209858@live.com>

Add mailbox controller driver for CV18XX SoCs, which provides 8 channels
and each channel has an 8-byte FIFO.

Signed-off-by: Yuntao Dai <d1581209858@live.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
---
 drivers/mailbox/Kconfig          |  10 ++
 drivers/mailbox/Makefile         |   2 +
 drivers/mailbox/cv1800-mailbox.c | 218 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 230 insertions(+)

diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index ed52db272f4d059ff60d608f40e3845411bc63f7..fd3f28d705bc00166028c372d3398f2e225aa8a7 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -36,6 +36,16 @@ config ARM_MHU_V3
 	  that provides different means of transports: supported extensions
 	  will be discovered and possibly managed at probe-time.
 
+config CV1800_MBOX
+	tristate "cv1800 mailbox"
+	depends on ARCH_SOPHGO || COMPILE_TEST
+	help
+	  Mailbox driver implementation for Sophgo CV18XX SoCs. This driver
+	  can be used to send message between different processors in SoC. Any
+	  processer can write data in a channel, and set co-responding register
+	  to raise interrupt to notice another processor, and it is allowed to
+	  send data to itself.
+
 config EXYNOS_MBOX
 	tristate "Exynos Mailbox"
 	depends on ARCH_EXYNOS || COMPILE_TEST
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 9a1542b55539c673af874c5c37fbb3d438fd05d3..13a3448b327115add5ebb8c4f116e68dedd755cb 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -11,6 +11,8 @@ obj-$(CONFIG_ARM_MHU_V2)	+= arm_mhuv2.o
 
 obj-$(CONFIG_ARM_MHU_V3)	+= arm_mhuv3.o
 
+obj-$(CONFIG_CV1800_MBOX)	+= cv1800-mailbox.o
+
 obj-$(CONFIG_EXYNOS_MBOX)	+= exynos-mailbox.o
 
 obj-$(CONFIG_IMX_MBOX)	+= imx-mailbox.o
diff --git a/drivers/mailbox/cv1800-mailbox.c b/drivers/mailbox/cv1800-mailbox.c
new file mode 100644
index 0000000000000000000000000000000000000000..339c155fb98ddf4155a84d5208c595043fc7a7ce
--- /dev/null
+++ b/drivers/mailbox/cv1800-mailbox.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2024 Sophgo Technology Inc.
+ * Copyright (C) 2024 Yuntao Dai <d1581209858@live.com>
+ * Copyright (C) 2025 Junhui Liu <junhui.liu@pigmoral.tech>
+ */
+
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kfifo.h>
+#include <linux/mailbox_client.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define RECV_CPU		1
+
+#define MAILBOX_MAX_CHAN	8
+
+#define MBOX_EN_REG(cpu)	(cpu << 2)
+#define MBOX_DONE_REG(cpu)	((cpu << 2) + 2)
+#define MBOX_SET_CLR_REG(cpu)	(0x10 + (cpu << 4))
+#define MBOX_SET_INT_REG(cpu)	(0x18 + (cpu << 4))
+#define MBOX_SET_REG		0x60
+
+#define MAILBOX_CONTEXT_OFFSET	0x0400
+#define MAILBOX_CONTEXT_SIZE	0x0040
+
+#define MBOX_CONTEXT_BASE_INDEX(base, index) \
+	((u64 *)(base + MAILBOX_CONTEXT_OFFSET) + index)
+
+/**
+ * struct cv1800_mbox_chan_priv - cv1800 mailbox channel private data
+ * @idx: index of channel
+ * @cpu: send to which processor
+ */
+struct cv1800_mbox_chan_priv {
+	int idx;
+	int cpu;
+};
+
+struct cv1800_mbox {
+	struct mbox_controller mbox;
+	struct cv1800_mbox_chan_priv priv[MAILBOX_MAX_CHAN];
+	struct mbox_chan chans[MAILBOX_MAX_CHAN];
+	u64 __iomem *content[MAILBOX_MAX_CHAN];
+	void __iomem *mbox_base;
+	int recvid;
+};
+
+static irqreturn_t cv1800_mbox_isr(int irq, void *dev_id)
+{
+	struct cv1800_mbox *mbox = (struct cv1800_mbox *)dev_id;
+	size_t i;
+	int ret = IRQ_NONE;
+
+	for (i = 0; i < MAILBOX_MAX_CHAN; i++) {
+		if (mbox->content[i] && mbox->chans[i].cl) {
+			mbox_chan_received_data(&mbox->chans[i],
+						(void *)mbox->content[i]);
+			mbox->content[i] = NULL;
+			ret = IRQ_HANDLED;
+		}
+	}
+
+	return ret;
+}
+
+static irqreturn_t cv1800_mbox_irq(int irq, void *dev_id)
+{
+	struct cv1800_mbox *mbox = (struct cv1800_mbox *)dev_id;
+	u8 set, valid;
+	size_t i;
+	int ret = IRQ_NONE;
+
+	set = readb(mbox->mbox_base + MBOX_SET_INT_REG(RECV_CPU));
+
+	if (!set)
+		return ret;
+
+	for (i = 0; i < MAILBOX_MAX_CHAN; i++) {
+		valid = set & BIT(i);
+		if (valid) {
+			mbox->content[i] =
+				MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, i);
+			writeb(valid,
+			       mbox->mbox_base + MBOX_SET_CLR_REG(RECV_CPU));
+			writeb(~valid, mbox->mbox_base + MBOX_EN_REG(RECV_CPU));
+			ret = IRQ_WAKE_THREAD;
+		}
+	}
+
+	return ret;
+}
+
+static int cv1800_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+	struct cv1800_mbox_chan_priv *priv =
+		(struct cv1800_mbox_chan_priv *)chan->con_priv;
+	struct cv1800_mbox *mbox = dev_get_drvdata(chan->mbox->dev);
+	int idx = priv->idx;
+	int cpu = priv->cpu;
+	u8 en, valid;
+
+	memcpy_toio(MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, idx),
+		    data, 8);
+
+	valid = BIT(idx);
+	writeb(valid, mbox->mbox_base + MBOX_SET_CLR_REG(cpu));
+	en = readb(mbox->mbox_base + MBOX_EN_REG(cpu));
+	writeb(en | valid, mbox->mbox_base + MBOX_EN_REG(cpu));
+	writeb(valid, mbox->mbox_base + MBOX_SET_REG);
+
+	return 0;
+}
+
+static bool cv1800_last_tx_done(struct mbox_chan *chan)
+{
+	struct cv1800_mbox_chan_priv *priv =
+		(struct cv1800_mbox_chan_priv *)chan->con_priv;
+	struct cv1800_mbox *mbox = dev_get_drvdata(chan->mbox->dev);
+	u8 en;
+
+	en = readb(mbox->mbox_base + MBOX_EN_REG(priv->cpu));
+
+	return !(en & BIT(priv->idx));
+}
+
+static const struct mbox_chan_ops cv1800_mbox_chan_ops = {
+	.send_data = cv1800_mbox_send_data,
+	.last_tx_done = cv1800_last_tx_done,
+};
+
+static struct mbox_chan *cv1800_mbox_xlate(struct mbox_controller *mbox,
+					   const struct of_phandle_args *spec)
+{
+	struct cv1800_mbox_chan_priv *priv;
+
+	int idx = spec->args[0];
+	int cpu = spec->args[1];
+
+	if (idx >= mbox->num_chans)
+		return ERR_PTR(-EINVAL);
+
+	priv = mbox->chans[idx].con_priv;
+	priv->cpu = cpu;
+
+	return &mbox->chans[idx];
+}
+
+static const struct of_device_id cv1800_mbox_of_match[] = {
+	{ .compatible = "sophgo,cv1800b-mailbox", },
+	{},
+};
+MODULE_DEVICE_TABLE(of, cv1800_mbox_of_match);
+
+static int cv1800_mbox_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cv1800_mbox *mb;
+	int irq, idx, err;
+
+	mb = devm_kzalloc(dev, sizeof(*mb), GFP_KERNEL);
+	if (!mb)
+		return -ENOMEM;
+
+	mb->mbox_base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(mb->mbox_base))
+		return dev_err_probe(dev, PTR_ERR(mb->mbox_base),
+				     "Failed to map resource\n");
+
+	mb->mbox.dev = dev;
+	mb->mbox.chans = mb->chans;
+	mb->mbox.txdone_poll = true;
+	mb->mbox.ops = &cv1800_mbox_chan_ops;
+	mb->mbox.num_chans = MAILBOX_MAX_CHAN;
+	mb->mbox.of_xlate = cv1800_mbox_xlate;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return irq;
+
+	err = devm_request_threaded_irq(dev, irq, cv1800_mbox_irq,
+					cv1800_mbox_isr, IRQF_ONESHOT,
+					dev_name(&pdev->dev), mb);
+	if (err < 0)
+		return dev_err_probe(dev, err, "Failed to register irq\n");
+
+	for (idx = 0; idx < MAILBOX_MAX_CHAN; idx++) {
+		mb->priv[idx].idx = idx;
+		mb->mbox.chans[idx].con_priv = &mb->priv[idx];
+	}
+
+	platform_set_drvdata(pdev, mb);
+
+	err = devm_mbox_controller_register(dev, &mb->mbox);
+	if (err)
+		return dev_err_probe(dev, err, "Failed to register mailbox\n");
+
+	return 0;
+}
+
+static struct platform_driver cv1800_mbox_driver = {
+	.driver = {
+		.name = "cv1800-mbox",
+		.of_match_table = cv1800_mbox_of_match,
+	},
+	.probe	= cv1800_mbox_probe,
+};
+
+module_platform_driver(cv1800_mbox_driver);
+
+MODULE_DESCRIPTION("cv1800 mailbox driver");
+MODULE_LICENSE("GPL");

-- 
2.49.0

Re: [PATCH v3 3/3] mailbox: sophgo: add mailbox driver for CV18XX series SoC

[kernel test robot]

Hi Junhui,

kernel test robot noticed the following build warnings:

[auto build test WARNING on b4432656b36e5cc1d50a1f2dc15357543add530e]

url:    https://github.com/intel-lab-lkp/linux/commits/Junhui-Liu/dt-bindings-mailbox-add-Sophgo-CV18XX-series-SoC/20250428-221604
base:   b4432656b36e5cc1d50a1f2dc15357543add530e
patch link:    https://lore.kernel.org/r/20250428-cv18xx-mbox-v3-3-ed18dfd836d1%40pigmoral.tech
patch subject: [PATCH v3 3/3] mailbox: sophgo: add mailbox driver for CV18XX series SoC
config: m68k-randconfig-r121-20250429 (https://download.01.org/0day-ci/archive/20250507/202505071325.uHimwt0g-lkp@intel.com/config)
compiler: m68k-linux-gcc (GCC) 7.5.0
reproduce: (https://download.01.org/0day-ci/archive/20250507/202505071325.uHimwt0g-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505071325.uHimwt0g-lkp@intel.com/

sparse warnings: (new ones prefixed by >>)
>> drivers/mailbox/cv1800-mailbox.c:64:50: sparse: sparse: cast removes address space '__iomem' of expression
   drivers/mailbox/cv1800-mailbox.c:89:33: sparse: sparse: cast removes address space '__iomem' of expression
>> drivers/mailbox/cv1800-mailbox.c:88:42: sparse: sparse: incorrect type in assignment (different address spaces) @@     expected unsigned long long [noderef] [usertype] __iomem * @@     got unsigned long long [usertype] * @@
   drivers/mailbox/cv1800-mailbox.c:88:42: sparse:     expected unsigned long long [noderef] [usertype] __iomem *
   drivers/mailbox/cv1800-mailbox.c:88:42: sparse:     got unsigned long long [usertype] *
   drivers/mailbox/cv1800-mailbox.c:109:21: sparse: sparse: cast removes address space '__iomem' of expression
>> drivers/mailbox/cv1800-mailbox.c:109:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@     expected void volatile [noderef] __iomem *dst @@     got unsigned long long [usertype] * @@
   drivers/mailbox/cv1800-mailbox.c:109:21: sparse:     expected void volatile [noderef] __iomem *dst
   drivers/mailbox/cv1800-mailbox.c:109:21: sparse:     got unsigned long long [usertype] *

vim +/__iomem +64 drivers/mailbox/cv1800-mailbox.c

    54	
    55	static irqreturn_t cv1800_mbox_isr(int irq, void *dev_id)
    56	{
    57		struct cv1800_mbox *mbox = (struct cv1800_mbox *)dev_id;
    58		size_t i;
    59		int ret = IRQ_NONE;
    60	
    61		for (i = 0; i < MAILBOX_MAX_CHAN; i++) {
    62			if (mbox->content[i] && mbox->chans[i].cl) {
    63				mbox_chan_received_data(&mbox->chans[i],
  > 64							(void *)mbox->content[i]);
    65				mbox->content[i] = NULL;
    66				ret = IRQ_HANDLED;
    67			}
    68		}
    69	
    70		return ret;
    71	}
    72	
    73	static irqreturn_t cv1800_mbox_irq(int irq, void *dev_id)
    74	{
    75		struct cv1800_mbox *mbox = (struct cv1800_mbox *)dev_id;
    76		u8 set, valid;
    77		size_t i;
    78		int ret = IRQ_NONE;
    79	
    80		set = readb(mbox->mbox_base + MBOX_SET_INT_REG(RECV_CPU));
    81	
    82		if (!set)
    83			return ret;
    84	
    85		for (i = 0; i < MAILBOX_MAX_CHAN; i++) {
    86			valid = set & BIT(i);
    87			if (valid) {
  > 88				mbox->content[i] =
    89					MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, i);
    90				writeb(valid,
    91				       mbox->mbox_base + MBOX_SET_CLR_REG(RECV_CPU));
    92				writeb(~valid, mbox->mbox_base + MBOX_EN_REG(RECV_CPU));
    93				ret = IRQ_WAKE_THREAD;
    94			}
    95		}
    96	
    97		return ret;
    98	}
    99	
   100	static int cv1800_mbox_send_data(struct mbox_chan *chan, void *data)
   101	{
   102		struct cv1800_mbox_chan_priv *priv =
   103			(struct cv1800_mbox_chan_priv *)chan->con_priv;
   104		struct cv1800_mbox *mbox = dev_get_drvdata(chan->mbox->dev);
   105		int idx = priv->idx;
   106		int cpu = priv->cpu;
   107		u8 en, valid;
   108	
 > 109		memcpy_toio(MBOX_CONTEXT_BASE_INDEX(mbox->mbox_base, idx),
   110			    data, 8);
   111	
   112		valid = BIT(idx);
   113		writeb(valid, mbox->mbox_base + MBOX_SET_CLR_REG(cpu));
   114		en = readb(mbox->mbox_base + MBOX_EN_REG(cpu));
   115		writeb(en | valid, mbox->mbox_base + MBOX_EN_REG(cpu));
   116		writeb(valid, mbox->mbox_base + MBOX_SET_REG);
   117	
   118		return 0;
   119	}
   120	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki