* [PATCH 0/2] Add u-blox,neo-m9 compatible
@ 2025-05-14 11:55 Alejandro Enrique via B4 Relay
2025-05-14 11:55 ` [PATCH 1/2] dt-bindings: gnss: add u-blox,neo-9m compatible Alejandro Enrique via B4 Relay
2025-05-14 11:55 ` [PATCH 2/2] gnss: ubx: add u-blox,neo-m9 compatible Alejandro Enrique via B4 Relay
0 siblings, 2 replies; 20+ messages in thread
From: Alejandro Enrique via B4 Relay @ 2025-05-14 11:55 UTC (permalink / raw)
To: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, devicetree, Alejandro Enrique
This series just add the compatible string for u-blox NEO-9M module. I
have tested the driver with such a module and it is working fine.
Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
---
Alejandro Enrique (2):
dt-bindings: gnss: add u-blox,neo-9m compatible
gnss: ubx: add u-blox,neo-m9 compatible
Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
drivers/gnss/ubx.c | 1 +
2 files changed, 2 insertions(+)
---
base-commit: 9c32cda43eb78f78c73aee4aa344b777714e259b
change-id: 20250514-ubx-m9-70df0fd8c48b
Best regards,
--
Alejandro Enrique <alejandroe1@geotab.com>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/2] dt-bindings: gnss: add u-blox,neo-9m compatible
2025-05-14 11:55 [PATCH 0/2] Add u-blox,neo-m9 compatible Alejandro Enrique via B4 Relay
@ 2025-05-14 11:55 ` Alejandro Enrique via B4 Relay
2025-05-14 15:49 ` [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042 Conor Dooley
2025-05-14 11:55 ` [PATCH 2/2] gnss: ubx: add u-blox,neo-m9 compatible Alejandro Enrique via B4 Relay
1 sibling, 1 reply; 20+ messages in thread
From: Alejandro Enrique via B4 Relay @ 2025-05-14 11:55 UTC (permalink / raw)
To: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, devicetree, Alejandro Enrique
From: Alejandro Enrique <alejandroe1@geotab.com>
Add compatible for u-blox NEO-9M GPS module.
Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
---
Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
index 7d4b6d49e5eea2201ac05ba6d54b1c1721172f26..cf5ff051b9ab03e5bfed8156a72170965929bb7e 100644
--- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
+++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
@@ -22,6 +22,7 @@ properties:
- u-blox,neo-6m
- u-blox,neo-8
- u-blox,neo-m8
+ - u-blox,neo-m9
reg:
description: >
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/2] gnss: ubx: add u-blox,neo-m9 compatible
2025-05-14 11:55 [PATCH 0/2] Add u-blox,neo-m9 compatible Alejandro Enrique via B4 Relay
2025-05-14 11:55 ` [PATCH 1/2] dt-bindings: gnss: add u-blox,neo-9m compatible Alejandro Enrique via B4 Relay
@ 2025-05-14 11:55 ` Alejandro Enrique via B4 Relay
1 sibling, 0 replies; 20+ messages in thread
From: Alejandro Enrique via B4 Relay @ 2025-05-14 11:55 UTC (permalink / raw)
To: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-kernel, devicetree, Alejandro Enrique
From: Alejandro Enrique <alejandroe1@geotab.com>
Add compatible for u-blox NEO-M9 GPS module.
Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
---
drivers/gnss/ubx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gnss/ubx.c b/drivers/gnss/ubx.c
index 92402f6082c415c7b9051338eef5406b09e09455..2d69f1b4a5979f96d3d4ce72b122f3bd05892b55 100644
--- a/drivers/gnss/ubx.c
+++ b/drivers/gnss/ubx.c
@@ -124,6 +124,7 @@ static const struct of_device_id ubx_of_match[] = {
{ .compatible = "u-blox,neo-6m" },
{ .compatible = "u-blox,neo-8" },
{ .compatible = "u-blox,neo-m8" },
+ { .compatible = "u-blox,neo-m9" },
{},
};
MODULE_DEVICE_TABLE(of, ubx_of_match);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-14 15:15 [PATCH v2 0/3] riscv: dts: sophgo: add more sg2042 isa extension support Han Gao
@ 2025-05-14 15:15 ` Han Gao
2025-05-15 1:33 ` Chen Wang
0 siblings, 1 reply; 20+ messages in thread
From: Han Gao @ 2025-05-14 15:15 UTC (permalink / raw)
To: devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Chen Wang,
Inochi Amaoto, Han Gao, linux-riscv, sophgo, linux-kernel
sg2042 support Zfh ISA extension [1].
Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
1 file changed, 128 insertions(+), 128 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index f483f62ab0c4..8dd1a3c60bc4 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -256,11 +256,11 @@ core3 {
cpu0: cpu@0 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <0>;
@@ -283,11 +283,11 @@ cpu0_intc: interrupt-controller {
cpu1: cpu@1 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <1>;
@@ -310,11 +310,11 @@ cpu1_intc: interrupt-controller {
cpu2: cpu@2 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <2>;
@@ -337,11 +337,11 @@ cpu2_intc: interrupt-controller {
cpu3: cpu@3 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <3>;
@@ -364,11 +364,11 @@ cpu3_intc: interrupt-controller {
cpu4: cpu@4 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <4>;
@@ -391,11 +391,11 @@ cpu4_intc: interrupt-controller {
cpu5: cpu@5 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <5>;
@@ -418,11 +418,11 @@ cpu5_intc: interrupt-controller {
cpu6: cpu@6 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <6>;
@@ -445,11 +445,11 @@ cpu6_intc: interrupt-controller {
cpu7: cpu@7 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <7>;
@@ -472,11 +472,11 @@ cpu7_intc: interrupt-controller {
cpu8: cpu@8 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <8>;
@@ -499,11 +499,11 @@ cpu8_intc: interrupt-controller {
cpu9: cpu@9 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <9>;
@@ -526,11 +526,11 @@ cpu9_intc: interrupt-controller {
cpu10: cpu@10 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <10>;
@@ -553,11 +553,11 @@ cpu10_intc: interrupt-controller {
cpu11: cpu@11 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <11>;
@@ -580,11 +580,11 @@ cpu11_intc: interrupt-controller {
cpu12: cpu@12 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <12>;
@@ -607,11 +607,11 @@ cpu12_intc: interrupt-controller {
cpu13: cpu@13 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <13>;
@@ -634,11 +634,11 @@ cpu13_intc: interrupt-controller {
cpu14: cpu@14 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <14>;
@@ -661,11 +661,11 @@ cpu14_intc: interrupt-controller {
cpu15: cpu@15 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <15>;
@@ -688,11 +688,11 @@ cpu15_intc: interrupt-controller {
cpu16: cpu@16 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <16>;
@@ -715,11 +715,11 @@ cpu16_intc: interrupt-controller {
cpu17: cpu@17 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <17>;
@@ -742,11 +742,11 @@ cpu17_intc: interrupt-controller {
cpu18: cpu@18 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <18>;
@@ -769,11 +769,11 @@ cpu18_intc: interrupt-controller {
cpu19: cpu@19 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <19>;
@@ -796,11 +796,11 @@ cpu19_intc: interrupt-controller {
cpu20: cpu@20 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <20>;
@@ -823,11 +823,11 @@ cpu20_intc: interrupt-controller {
cpu21: cpu@21 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <21>;
@@ -850,11 +850,11 @@ cpu21_intc: interrupt-controller {
cpu22: cpu@22 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <22>;
@@ -877,11 +877,11 @@ cpu22_intc: interrupt-controller {
cpu23: cpu@23 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <23>;
@@ -904,11 +904,11 @@ cpu23_intc: interrupt-controller {
cpu24: cpu@24 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <24>;
@@ -931,11 +931,11 @@ cpu24_intc: interrupt-controller {
cpu25: cpu@25 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <25>;
@@ -958,11 +958,11 @@ cpu25_intc: interrupt-controller {
cpu26: cpu@26 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <26>;
@@ -985,11 +985,11 @@ cpu26_intc: interrupt-controller {
cpu27: cpu@27 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <27>;
@@ -1012,11 +1012,11 @@ cpu27_intc: interrupt-controller {
cpu28: cpu@28 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <28>;
@@ -1039,11 +1039,11 @@ cpu28_intc: interrupt-controller {
cpu29: cpu@29 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <29>;
@@ -1066,11 +1066,11 @@ cpu29_intc: interrupt-controller {
cpu30: cpu@30 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <30>;
@@ -1093,11 +1093,11 @@ cpu30_intc: interrupt-controller {
cpu31: cpu@31 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <31>;
@@ -1120,11 +1120,11 @@ cpu31_intc: interrupt-controller {
cpu32: cpu@32 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <32>;
@@ -1147,11 +1147,11 @@ cpu32_intc: interrupt-controller {
cpu33: cpu@33 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <33>;
@@ -1174,11 +1174,11 @@ cpu33_intc: interrupt-controller {
cpu34: cpu@34 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <34>;
@@ -1201,11 +1201,11 @@ cpu34_intc: interrupt-controller {
cpu35: cpu@35 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <35>;
@@ -1228,11 +1228,11 @@ cpu35_intc: interrupt-controller {
cpu36: cpu@36 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <36>;
@@ -1255,11 +1255,11 @@ cpu36_intc: interrupt-controller {
cpu37: cpu@37 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <37>;
@@ -1282,11 +1282,11 @@ cpu37_intc: interrupt-controller {
cpu38: cpu@38 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <38>;
@@ -1309,11 +1309,11 @@ cpu38_intc: interrupt-controller {
cpu39: cpu@39 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <39>;
@@ -1336,11 +1336,11 @@ cpu39_intc: interrupt-controller {
cpu40: cpu@40 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <40>;
@@ -1363,11 +1363,11 @@ cpu40_intc: interrupt-controller {
cpu41: cpu@41 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <41>;
@@ -1390,11 +1390,11 @@ cpu41_intc: interrupt-controller {
cpu42: cpu@42 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <42>;
@@ -1417,11 +1417,11 @@ cpu42_intc: interrupt-controller {
cpu43: cpu@43 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <43>;
@@ -1444,11 +1444,11 @@ cpu43_intc: interrupt-controller {
cpu44: cpu@44 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <44>;
@@ -1471,11 +1471,11 @@ cpu44_intc: interrupt-controller {
cpu45: cpu@45 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <45>;
@@ -1498,11 +1498,11 @@ cpu45_intc: interrupt-controller {
cpu46: cpu@46 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <46>;
@@ -1525,11 +1525,11 @@ cpu46_intc: interrupt-controller {
cpu47: cpu@47 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <47>;
@@ -1552,11 +1552,11 @@ cpu47_intc: interrupt-controller {
cpu48: cpu@48 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <48>;
@@ -1579,11 +1579,11 @@ cpu48_intc: interrupt-controller {
cpu49: cpu@49 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <49>;
@@ -1606,11 +1606,11 @@ cpu49_intc: interrupt-controller {
cpu50: cpu@50 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <50>;
@@ -1633,11 +1633,11 @@ cpu50_intc: interrupt-controller {
cpu51: cpu@51 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <51>;
@@ -1660,11 +1660,11 @@ cpu51_intc: interrupt-controller {
cpu52: cpu@52 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <52>;
@@ -1687,11 +1687,11 @@ cpu52_intc: interrupt-controller {
cpu53: cpu@53 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <53>;
@@ -1714,11 +1714,11 @@ cpu53_intc: interrupt-controller {
cpu54: cpu@54 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <54>;
@@ -1741,11 +1741,11 @@ cpu54_intc: interrupt-controller {
cpu55: cpu@55 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <55>;
@@ -1768,11 +1768,11 @@ cpu55_intc: interrupt-controller {
cpu56: cpu@56 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <56>;
@@ -1795,11 +1795,11 @@ cpu56_intc: interrupt-controller {
cpu57: cpu@57 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <57>;
@@ -1822,11 +1822,11 @@ cpu57_intc: interrupt-controller {
cpu58: cpu@58 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <58>;
@@ -1849,11 +1849,11 @@ cpu58_intc: interrupt-controller {
cpu59: cpu@59 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <59>;
@@ -1876,11 +1876,11 @@ cpu59_intc: interrupt-controller {
cpu60: cpu@60 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <60>;
@@ -1903,11 +1903,11 @@ cpu60_intc: interrupt-controller {
cpu61: cpu@61 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <61>;
@@ -1930,11 +1930,11 @@ cpu61_intc: interrupt-controller {
cpu62: cpu@62 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <62>;
@@ -1957,11 +1957,11 @@ cpu62_intc: interrupt-controller {
cpu63: cpu@63 {
compatible = "thead,c920", "riscv";
device_type = "cpu";
- riscv,isa = "rv64imafdc";
+ riscv,isa = "rv64imafdc_zfh";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"ziccrse", "zicntr", "zicsr",
- "zifencei", "zihpm",
+ "zifencei", "zihpm", "zfh",
"xtheadvector";
thead,vlenb = <16>;
reg = <63>;
--
2.47.2
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-14 11:55 ` [PATCH 1/2] dt-bindings: gnss: add u-blox,neo-9m compatible Alejandro Enrique via B4 Relay
@ 2025-05-14 15:49 ` Conor Dooley
[not found] ` <CAN=L63qsjEAvfocgP0tGrpe-x6Rx1gvTAkPE9i99Ai2zJj6ssA@mail.gmail.com>
2025-05-19 13:06 ` Johan Hovold
0 siblings, 2 replies; 20+ messages in thread
From: Conor Dooley @ 2025-05-14 15:49 UTC (permalink / raw)
To: alejandroe1
Cc: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 1003 bytes --]
On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay wrote:
> From: Alejandro Enrique <alejandroe1@geotab.com>
>
> Add compatible for u-blox NEO-9M GPS module.
>
> Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
> ---
> Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> index 7d4b6d49e5eea2201ac05ba6d54b1c1721172f26..cf5ff051b9ab03e5bfed8156a72170965929bb7e 100644
> --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> @@ -22,6 +22,7 @@ properties:
> - u-blox,neo-6m
> - u-blox,neo-8
> - u-blox,neo-m8
> + - u-blox,neo-m9
No match data in the driver, why is a fallback not sufficient?
>
> reg:
> description: >
>
> --
> 2.34.1
>
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-14 15:15 ` [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042 Han Gao
@ 2025-05-15 1:33 ` Chen Wang
2025-05-27 9:34 ` Han Gao
0 siblings, 1 reply; 20+ messages in thread
From: Chen Wang @ 2025-05-15 1:33 UTC (permalink / raw)
To: Han Gao, devicetree
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Paul Walmsley,
Palmer Dabbelt, Albert Ou, Alexandre Ghiti, Inochi Amaoto,
linux-riscv, sophgo, linux-kernel
On 2025/5/14 23:15, Han Gao wrote:
> sg2042 support Zfh ISA extension [1].
>
> Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> ---
> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
> 1 file changed, 128 insertions(+), 128 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> index f483f62ab0c4..8dd1a3c60bc4 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> @@ -256,11 +256,11 @@ core3 {
> cpu0: cpu@0 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
Need not touch this. "riscv,isa" is deprecated and replaced by
"riscv,isa-base" & "riscv,isa-extensions".
And only adding zfh for this looks a bit werid.
Actually, I plan to remove "riscv,isa" later, so please don't touch this
from now on.
Thanks,
Chen
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <0>;
> @@ -283,11 +283,11 @@ cpu0_intc: interrupt-controller {
> cpu1: cpu@1 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <1>;
> @@ -310,11 +310,11 @@ cpu1_intc: interrupt-controller {
> cpu2: cpu@2 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <2>;
> @@ -337,11 +337,11 @@ cpu2_intc: interrupt-controller {
> cpu3: cpu@3 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <3>;
> @@ -364,11 +364,11 @@ cpu3_intc: interrupt-controller {
> cpu4: cpu@4 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <4>;
> @@ -391,11 +391,11 @@ cpu4_intc: interrupt-controller {
> cpu5: cpu@5 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <5>;
> @@ -418,11 +418,11 @@ cpu5_intc: interrupt-controller {
> cpu6: cpu@6 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <6>;
> @@ -445,11 +445,11 @@ cpu6_intc: interrupt-controller {
> cpu7: cpu@7 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <7>;
> @@ -472,11 +472,11 @@ cpu7_intc: interrupt-controller {
> cpu8: cpu@8 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <8>;
> @@ -499,11 +499,11 @@ cpu8_intc: interrupt-controller {
> cpu9: cpu@9 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <9>;
> @@ -526,11 +526,11 @@ cpu9_intc: interrupt-controller {
> cpu10: cpu@10 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <10>;
> @@ -553,11 +553,11 @@ cpu10_intc: interrupt-controller {
> cpu11: cpu@11 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <11>;
> @@ -580,11 +580,11 @@ cpu11_intc: interrupt-controller {
> cpu12: cpu@12 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <12>;
> @@ -607,11 +607,11 @@ cpu12_intc: interrupt-controller {
> cpu13: cpu@13 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <13>;
> @@ -634,11 +634,11 @@ cpu13_intc: interrupt-controller {
> cpu14: cpu@14 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <14>;
> @@ -661,11 +661,11 @@ cpu14_intc: interrupt-controller {
> cpu15: cpu@15 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <15>;
> @@ -688,11 +688,11 @@ cpu15_intc: interrupt-controller {
> cpu16: cpu@16 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <16>;
> @@ -715,11 +715,11 @@ cpu16_intc: interrupt-controller {
> cpu17: cpu@17 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <17>;
> @@ -742,11 +742,11 @@ cpu17_intc: interrupt-controller {
> cpu18: cpu@18 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <18>;
> @@ -769,11 +769,11 @@ cpu18_intc: interrupt-controller {
> cpu19: cpu@19 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <19>;
> @@ -796,11 +796,11 @@ cpu19_intc: interrupt-controller {
> cpu20: cpu@20 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <20>;
> @@ -823,11 +823,11 @@ cpu20_intc: interrupt-controller {
> cpu21: cpu@21 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <21>;
> @@ -850,11 +850,11 @@ cpu21_intc: interrupt-controller {
> cpu22: cpu@22 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <22>;
> @@ -877,11 +877,11 @@ cpu22_intc: interrupt-controller {
> cpu23: cpu@23 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <23>;
> @@ -904,11 +904,11 @@ cpu23_intc: interrupt-controller {
> cpu24: cpu@24 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <24>;
> @@ -931,11 +931,11 @@ cpu24_intc: interrupt-controller {
> cpu25: cpu@25 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <25>;
> @@ -958,11 +958,11 @@ cpu25_intc: interrupt-controller {
> cpu26: cpu@26 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <26>;
> @@ -985,11 +985,11 @@ cpu26_intc: interrupt-controller {
> cpu27: cpu@27 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <27>;
> @@ -1012,11 +1012,11 @@ cpu27_intc: interrupt-controller {
> cpu28: cpu@28 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <28>;
> @@ -1039,11 +1039,11 @@ cpu28_intc: interrupt-controller {
> cpu29: cpu@29 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <29>;
> @@ -1066,11 +1066,11 @@ cpu29_intc: interrupt-controller {
> cpu30: cpu@30 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <30>;
> @@ -1093,11 +1093,11 @@ cpu30_intc: interrupt-controller {
> cpu31: cpu@31 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <31>;
> @@ -1120,11 +1120,11 @@ cpu31_intc: interrupt-controller {
> cpu32: cpu@32 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <32>;
> @@ -1147,11 +1147,11 @@ cpu32_intc: interrupt-controller {
> cpu33: cpu@33 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <33>;
> @@ -1174,11 +1174,11 @@ cpu33_intc: interrupt-controller {
> cpu34: cpu@34 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <34>;
> @@ -1201,11 +1201,11 @@ cpu34_intc: interrupt-controller {
> cpu35: cpu@35 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <35>;
> @@ -1228,11 +1228,11 @@ cpu35_intc: interrupt-controller {
> cpu36: cpu@36 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <36>;
> @@ -1255,11 +1255,11 @@ cpu36_intc: interrupt-controller {
> cpu37: cpu@37 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <37>;
> @@ -1282,11 +1282,11 @@ cpu37_intc: interrupt-controller {
> cpu38: cpu@38 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <38>;
> @@ -1309,11 +1309,11 @@ cpu38_intc: interrupt-controller {
> cpu39: cpu@39 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <39>;
> @@ -1336,11 +1336,11 @@ cpu39_intc: interrupt-controller {
> cpu40: cpu@40 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <40>;
> @@ -1363,11 +1363,11 @@ cpu40_intc: interrupt-controller {
> cpu41: cpu@41 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <41>;
> @@ -1390,11 +1390,11 @@ cpu41_intc: interrupt-controller {
> cpu42: cpu@42 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <42>;
> @@ -1417,11 +1417,11 @@ cpu42_intc: interrupt-controller {
> cpu43: cpu@43 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <43>;
> @@ -1444,11 +1444,11 @@ cpu43_intc: interrupt-controller {
> cpu44: cpu@44 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <44>;
> @@ -1471,11 +1471,11 @@ cpu44_intc: interrupt-controller {
> cpu45: cpu@45 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <45>;
> @@ -1498,11 +1498,11 @@ cpu45_intc: interrupt-controller {
> cpu46: cpu@46 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <46>;
> @@ -1525,11 +1525,11 @@ cpu46_intc: interrupt-controller {
> cpu47: cpu@47 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <47>;
> @@ -1552,11 +1552,11 @@ cpu47_intc: interrupt-controller {
> cpu48: cpu@48 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <48>;
> @@ -1579,11 +1579,11 @@ cpu48_intc: interrupt-controller {
> cpu49: cpu@49 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <49>;
> @@ -1606,11 +1606,11 @@ cpu49_intc: interrupt-controller {
> cpu50: cpu@50 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <50>;
> @@ -1633,11 +1633,11 @@ cpu50_intc: interrupt-controller {
> cpu51: cpu@51 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <51>;
> @@ -1660,11 +1660,11 @@ cpu51_intc: interrupt-controller {
> cpu52: cpu@52 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <52>;
> @@ -1687,11 +1687,11 @@ cpu52_intc: interrupt-controller {
> cpu53: cpu@53 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <53>;
> @@ -1714,11 +1714,11 @@ cpu53_intc: interrupt-controller {
> cpu54: cpu@54 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <54>;
> @@ -1741,11 +1741,11 @@ cpu54_intc: interrupt-controller {
> cpu55: cpu@55 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <55>;
> @@ -1768,11 +1768,11 @@ cpu55_intc: interrupt-controller {
> cpu56: cpu@56 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <56>;
> @@ -1795,11 +1795,11 @@ cpu56_intc: interrupt-controller {
> cpu57: cpu@57 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <57>;
> @@ -1822,11 +1822,11 @@ cpu57_intc: interrupt-controller {
> cpu58: cpu@58 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <58>;
> @@ -1849,11 +1849,11 @@ cpu58_intc: interrupt-controller {
> cpu59: cpu@59 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <59>;
> @@ -1876,11 +1876,11 @@ cpu59_intc: interrupt-controller {
> cpu60: cpu@60 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <60>;
> @@ -1903,11 +1903,11 @@ cpu60_intc: interrupt-controller {
> cpu61: cpu@61 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <61>;
> @@ -1930,11 +1930,11 @@ cpu61_intc: interrupt-controller {
> cpu62: cpu@62 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <62>;
> @@ -1957,11 +1957,11 @@ cpu62_intc: interrupt-controller {
> cpu63: cpu@63 {
> compatible = "thead,c920", "riscv";
> device_type = "cpu";
> - riscv,isa = "rv64imafdc";
> + riscv,isa = "rv64imafdc_zfh";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> "ziccrse", "zicntr", "zicsr",
> - "zifencei", "zihpm",
> + "zifencei", "zihpm", "zfh",
> "xtheadvector";
> thead,vlenb = <16>;
> reg = <63>;
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
[not found] ` <CAN=L63qsjEAvfocgP0tGrpe-x6Rx1gvTAkPE9i99Ai2zJj6ssA@mail.gmail.com>
@ 2025-05-15 15:02 ` Conor Dooley
2025-05-16 10:23 ` Alejandro Enrique
0 siblings, 1 reply; 20+ messages in thread
From: Conor Dooley @ 2025-05-15 15:02 UTC (permalink / raw)
To: Alejandro Enrique
Cc: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
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On Wed, May 14, 2025 at 06:53:25PM +0200, Alejandro Enrique wrote:
> On Wed, May 14, 2025 at 5:49 PM Conor Dooley <conor@kernel.org> wrote:
>
> > On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay
> > wrote:
> > > From: Alejandro Enrique <alejandroe1@geotab.com>
> > >
> > > Add compatible for u-blox NEO-9M GPS module.
> > >
> > > Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
> > > ---
> > > Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > index
> > 7d4b6d49e5eea2201ac05ba6d54b1c1721172f26..cf5ff051b9ab03e5bfed8156a72170965929bb7e
> > 100644
> > > --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > @@ -22,6 +22,7 @@ properties:
> > > - u-blox,neo-6m
> > > - u-blox,neo-8
> > > - u-blox,neo-m8
> > > + - u-blox,neo-m9
> >
> > No match data in the driver, why is a fallback not sufficient?
> >
>
> I added the match data in the driver in the PATCH 2/2 of this series
> in the same fashion as previously supported modules.
Did you? When I looked, there was just a compatible and no match data.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-15 15:02 ` Conor Dooley
@ 2025-05-16 10:23 ` Alejandro Enrique
2025-05-16 14:01 ` Conor Dooley
0 siblings, 1 reply; 20+ messages in thread
From: Alejandro Enrique @ 2025-05-16 10:23 UTC (permalink / raw)
To: Conor Dooley
Cc: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
On Thu, May 15, 2025 at 5:02 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Wed, May 14, 2025 at 06:53:25PM +0200, Alejandro Enrique wrote:
> > On Wed, May 14, 2025 at 5:49 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > > On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay
> > > wrote:
> > > > From: Alejandro Enrique <alejandroe1@geotab.com>
> > > >
> > > > Add compatible for u-blox NEO-9M GPS module.
> > > >
> > > > Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
> > > > ---
> > > > Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
> > > > 1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > index
> > > 7d4b6d49e5eea2201ac05ba6d54b1c1721172f26..cf5ff051b9ab03e5bfed8156a72170965929bb7e
> > > 100644
> > > > --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > @@ -22,6 +22,7 @@ properties:
> > > > - u-blox,neo-6m
> > > > - u-blox,neo-8
> > > > - u-blox,neo-m8
> > > > + - u-blox,neo-m9
> > >
> > > No match data in the driver, why is a fallback not sufficient?
> > >
> >
> > I added the match data in the driver in the PATCH 2/2 of this series
> > in the same fashion as previously supported modules.
>
> Did you? When I looked, there was just a compatible and no match data.
You are right. I just added a compatible string, no match data. Sorry,
I was not following.
I just added the neo-m9 compatible the same way the neo-6m was previously
added.
What do you mean by using a fallback? Using one of the existent
compatibles (none have match data) or adding a new fallback
compatible, something like just "u-blox,neo"?
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-16 10:23 ` Alejandro Enrique
@ 2025-05-16 14:01 ` Conor Dooley
2025-05-16 15:00 ` Alejandro Enrique
0 siblings, 1 reply; 20+ messages in thread
From: Conor Dooley @ 2025-05-16 14:01 UTC (permalink / raw)
To: Alejandro Enrique
Cc: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 2104 bytes --]
On Fri, May 16, 2025 at 12:23:35PM +0200, Alejandro Enrique wrote:
> On Thu, May 15, 2025 at 5:02 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Wed, May 14, 2025 at 06:53:25PM +0200, Alejandro Enrique wrote:
> > > On Wed, May 14, 2025 at 5:49 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > > On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay
> > > > wrote:
> > > > > From: Alejandro Enrique <alejandroe1@geotab.com>
> > > > >
> > > > > Add compatible for u-blox NEO-9M GPS module.
> > > > >
> > > > > Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
> > > > > ---
> > > > > Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
> > > > > 1 file changed, 1 insertion(+)
> > > > >
> > > > > diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > index
> > > > 7d4b6d49e5eea2201ac05ba6d54b1c1721172f26..cf5ff051b9ab03e5bfed8156a72170965929bb7e
> > > > 100644
> > > > > --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > @@ -22,6 +22,7 @@ properties:
> > > > > - u-blox,neo-6m
> > > > > - u-blox,neo-8
> > > > > - u-blox,neo-m8
> > > > > + - u-blox,neo-m9
> > > >
> > > > No match data in the driver, why is a fallback not sufficient?
> > > >
> > >
> > > I added the match data in the driver in the PATCH 2/2 of this series
> > > in the same fashion as previously supported modules.
> >
> > Did you? When I looked, there was just a compatible and no match data.
>
> You are right. I just added a compatible string, no match data. Sorry,
> I was not following.
> I just added the neo-m9 compatible the same way the neo-6m was previously
> added.
>
> What do you mean by using a fallback? Using one of the existent
> compatibles (none have match data) or adding a new fallback
> compatible, something like just "u-blox,neo"?
Falling back to one of the existing ones, like neo-m8.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-16 14:01 ` Conor Dooley
@ 2025-05-16 15:00 ` Alejandro Enrique
2025-05-19 12:37 ` Conor Dooley
2025-05-19 12:59 ` Johan Hovold
0 siblings, 2 replies; 20+ messages in thread
From: Alejandro Enrique @ 2025-05-16 15:00 UTC (permalink / raw)
To: Conor Dooley
Cc: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
On Fri, May 16, 2025 at 4:01 PM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, May 16, 2025 at 12:23:35PM +0200, Alejandro Enrique wrote:
> > On Thu, May 15, 2025 at 5:02 PM Conor Dooley <conor@kernel.org> wrote:
> > >
> > > On Wed, May 14, 2025 at 06:53:25PM +0200, Alejandro Enrique wrote:
> > > > On Wed, May 14, 2025 at 5:49 PM Conor Dooley <conor@kernel.org> wrote:
> > > >
> > > > > On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay
> > > > > wrote:
> > > > > > From: Alejandro Enrique <alejandroe1@geotab.com>
> > > > > >
> > > > > > Add compatible for u-blox NEO-9M GPS module.
> > > > > >
> > > > > > Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
> > > > > > ---
> > > > > > Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
> > > > > > 1 file changed, 1 insertion(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > index
> > > > > 7d4b6d49e5eea2201ac05ba6d54b1c1721172f26..cf5ff051b9ab03e5bfed8156a72170965929bb7e
> > > > > 100644
> > > > > > --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > @@ -22,6 +22,7 @@ properties:
> > > > > > - u-blox,neo-6m
> > > > > > - u-blox,neo-8
> > > > > > - u-blox,neo-m8
> > > > > > + - u-blox,neo-m9
> > > > >
> > > > > No match data in the driver, why is a fallback not sufficient?
> > > > >
> > > >
> > > > I added the match data in the driver in the PATCH 2/2 of this series
> > > > in the same fashion as previously supported modules.
> > >
> > > Did you? When I looked, there was just a compatible and no match data.
> >
> > You are right. I just added a compatible string, no match data. Sorry,
> > I was not following.
> > I just added the neo-m9 compatible the same way the neo-6m was previously
> > added.
> >
> > What do you mean by using a fallback? Using one of the existent
> > compatibles (none have match data) or adding a new fallback
> > compatible, something like just "u-blox,neo"?
>
> Falling back to one of the existing ones, like neo-m8.
That is perfectly possible. I added the new compatible string based
on what was previously done for the neo-6m one.
https://lore.kernel.org/lkml/20190401115616.21337-5-megous@megous.com/
If that is not a good approach I think this series can be discarded already.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-16 15:00 ` Alejandro Enrique
@ 2025-05-19 12:37 ` Conor Dooley
2025-05-19 12:59 ` Johan Hovold
1 sibling, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2025-05-19 12:37 UTC (permalink / raw)
To: Alejandro Enrique
Cc: Johan Hovold, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 2867 bytes --]
On Fri, May 16, 2025 at 05:00:50PM +0200, Alejandro Enrique wrote:
> On Fri, May 16, 2025 at 4:01 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Fri, May 16, 2025 at 12:23:35PM +0200, Alejandro Enrique wrote:
> > > On Thu, May 15, 2025 at 5:02 PM Conor Dooley <conor@kernel.org> wrote:
> > > >
> > > > On Wed, May 14, 2025 at 06:53:25PM +0200, Alejandro Enrique wrote:
> > > > > On Wed, May 14, 2025 at 5:49 PM Conor Dooley <conor@kernel.org> wrote:
> > > > >
> > > > > > On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay
> > > > > > wrote:
> > > > > > > From: Alejandro Enrique <alejandroe1@geotab.com>
> > > > > > >
> > > > > > > Add compatible for u-blox NEO-9M GPS module.
> > > > > > >
> > > > > > > Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
> > > > > > > ---
> > > > > > > Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
> > > > > > > 1 file changed, 1 insertion(+)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > > index
> > > > > > 7d4b6d49e5eea2201ac05ba6d54b1c1721172f26..cf5ff051b9ab03e5bfed8156a72170965929bb7e
> > > > > > 100644
> > > > > > > --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > > @@ -22,6 +22,7 @@ properties:
> > > > > > > - u-blox,neo-6m
> > > > > > > - u-blox,neo-8
> > > > > > > - u-blox,neo-m8
> > > > > > > + - u-blox,neo-m9
> > > > > >
> > > > > > No match data in the driver, why is a fallback not sufficient?
> > > > > >
> > > > >
> > > > > I added the match data in the driver in the PATCH 2/2 of this series
> > > > > in the same fashion as previously supported modules.
> > > >
> > > > Did you? When I looked, there was just a compatible and no match data.
> > >
> > > You are right. I just added a compatible string, no match data. Sorry,
> > > I was not following.
> > > I just added the neo-m9 compatible the same way the neo-6m was previously
> > > added.
> > >
> > > What do you mean by using a fallback? Using one of the existent
> > > compatibles (none have match data) or adding a new fallback
> > > compatible, something like just "u-blox,neo"?
> >
> > Falling back to one of the existing ones, like neo-m8.
>
> That is perfectly possible. I added the new compatible string based
> on what was previously done for the neo-6m one.
> https://lore.kernel.org/lkml/20190401115616.21337-5-megous@megous.com/
>
> If that is not a good approach I think this series can be discarded already.
If you did use a fallback, you still need to modify the binding to
permit it, so there'd be a different v2 rather than throwing it away.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-16 15:00 ` Alejandro Enrique
2025-05-19 12:37 ` Conor Dooley
@ 2025-05-19 12:59 ` Johan Hovold
2025-05-21 16:12 ` Alejandro Enrique
1 sibling, 1 reply; 20+ messages in thread
From: Johan Hovold @ 2025-05-19 12:59 UTC (permalink / raw)
To: Alejandro Enrique
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
On Fri, May 16, 2025 at 05:00:50PM +0200, Alejandro Enrique wrote:
> On Fri, May 16, 2025 at 4:01 PM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Fri, May 16, 2025 at 12:23:35PM +0200, Alejandro Enrique wrote:
> > > On Thu, May 15, 2025 at 5:02 PM Conor Dooley <conor@kernel.org> wrote:
> > > >
> > > > On Wed, May 14, 2025 at 06:53:25PM +0200, Alejandro Enrique wrote:
> > > > > On Wed, May 14, 2025 at 5:49 PM Conor Dooley <conor@kernel.org> wrote:
> > > > >
> > > > > > On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay
> > > > > > wrote:
> > > > > > > From: Alejandro Enrique <alejandroe1@geotab.com>
> > > > > > >
> > > > > > > Add compatible for u-blox NEO-9M GPS module.
> > > > > > >
> > > > > > > Signed-off-by: Alejandro Enrique <alejandroe1@geotab.com>
> > > > > > > ---
> > > > > > > Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml | 1 +
> > > > > > > 1 file changed, 1 insertion(+)
> > > > > > >
> > > > > > > diff --git a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > > index
> > > > > > 7d4b6d49e5eea2201ac05ba6d54b1c1721172f26..cf5ff051b9ab03e5bfed8156a72170965929bb7e
> > > > > > 100644
> > > > > > > --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > > +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > > > > > @@ -22,6 +22,7 @@ properties:
> > > > > > > - u-blox,neo-6m
> > > > > > > - u-blox,neo-8
> > > > > > > - u-blox,neo-m8
> > > > > > > + - u-blox,neo-m9
> > > > > >
> > > > > > No match data in the driver, why is a fallback not sufficient?
> > > > > >
> > > > >
> > > > > I added the match data in the driver in the PATCH 2/2 of this series
> > > > > in the same fashion as previously supported modules.
> > > >
> > > > Did you? When I looked, there was just a compatible and no match data.
> > >
> > > You are right. I just added a compatible string, no match data. Sorry,
> > > I was not following.
> > > I just added the neo-m9 compatible the same way the neo-6m was previously
> > > added.
> > >
> > > What do you mean by using a fallback? Using one of the existent
> > > compatibles (none have match data) or adding a new fallback
> > > compatible, something like just "u-blox,neo"?
> >
> > Falling back to one of the existing ones, like neo-m8.
>
> That is perfectly possible. I added the new compatible string based
> on what was previously done for the neo-6m one.
> https://lore.kernel.org/lkml/20190401115616.21337-5-megous@megous.com/
>
> If that is not a good approach I think this series can be discarded already.
We still want a new compatible string for the new device. Depending on
how similar these products are it may be possible to avoid adding a new
entry to the driver for now by specifying a fallback compatible, for
example, to neo-m8:
compatible = "u-blox,neo-m9", "u-blox,neo-m8";
This would then need to be encoded in the binding.
Johan
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-14 15:49 ` [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042 Conor Dooley
[not found] ` <CAN=L63qsjEAvfocgP0tGrpe-x6Rx1gvTAkPE9i99Ai2zJj6ssA@mail.gmail.com>
@ 2025-05-19 13:06 ` Johan Hovold
2025-05-19 15:12 ` Conor Dooley
1 sibling, 1 reply; 20+ messages in thread
From: Johan Hovold @ 2025-05-19 13:06 UTC (permalink / raw)
To: Conor Dooley
Cc: alejandroe1, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 694 bytes --]
On Wed, May 14, 2025 at 04:49:01PM +0100, Conor Dooley wrote:
> On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay wrote:
> > From: Alejandro Enrique <alejandroe1@geotab.com>
> >
> > Add compatible for u-blox NEO-9M GPS module.
> > --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > @@ -22,6 +22,7 @@ properties:
> > - u-blox,neo-6m
> > - u-blox,neo-8
> > - u-blox,neo-m8
> > + - u-blox,neo-m9
>
> No match data in the driver, why is a fallback not sufficient?
By the way, what happened with the Subject in your reply here, Conor?
Johan
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-19 13:06 ` Johan Hovold
@ 2025-05-19 15:12 ` Conor Dooley
0 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2025-05-19 15:12 UTC (permalink / raw)
To: Johan Hovold
Cc: alejandroe1, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
[-- Attachment #1: Type: text/plain, Size: 999 bytes --]
On Mon, May 19, 2025 at 03:06:02PM +0200, Johan Hovold wrote:
> On Wed, May 14, 2025 at 04:49:01PM +0100, Conor Dooley wrote:
> > On Wed, May 14, 2025 at 01:55:54PM +0200, Alejandro Enrique via B4 Relay wrote:
> > > From: Alejandro Enrique <alejandroe1@geotab.com>
> > >
> > > Add compatible for u-blox NEO-9M GPS module.
>
> > > --- a/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > +++ b/Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
> > > @@ -22,6 +22,7 @@ properties:
> > > - u-blox,neo-6m
> > > - u-blox,neo-8
> > > - u-blox,neo-m8
> > > + - u-blox,neo-m9
> >
> > No match data in the driver, why is a fallback not sufficient?
>
> By the way, what happened with the Subject in your reply here, Conor?
I dunno, I think it is possibly a bug in mutt. Not the first time I have
seen it. All I ever do is "g enter enter enter", I never paste into the
field and I would expect that pasting into the field would append.
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-19 12:59 ` Johan Hovold
@ 2025-05-21 16:12 ` Alejandro Enrique
0 siblings, 0 replies; 20+ messages in thread
From: Alejandro Enrique @ 2025-05-21 16:12 UTC (permalink / raw)
To: Johan Hovold
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-kernel, devicetree
On Mon, May 19, 2025 at 2:59 PM Johan Hovold <johan@kernel.org> wrote:
>
> We still want a new compatible string for the new device. Depending on
> how similar these products are it may be possible to avoid adding a new
> entry to the driver for now by specifying a fallback compatible, for
> example, to neo-m8:
>
> compatible = "u-blox,neo-m9", "u-blox,neo-m8";
>
> This would then need to be encoded in the binding.
OK, thanks. I will submit a v2 removing the new entry from the driver
and modifying the binding to permit the fallback.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-15 1:33 ` Chen Wang
@ 2025-05-27 9:34 ` Han Gao
2025-05-27 10:22 ` Chen Wang
0 siblings, 1 reply; 20+ messages in thread
From: Han Gao @ 2025-05-27 9:34 UTC (permalink / raw)
To: Chen Wang
Cc: devicetree, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Inochi Amaoto, linux-riscv, sophgo, linux-kernel
On Thu, May 15, 2025 at 9:33 AM Chen Wang <unicorn_wang@outlook.com> wrote:
>
>
> On 2025/5/14 23:15, Han Gao wrote:
> > sg2042 support Zfh ISA extension [1].
> >
> > Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
> >
> > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> > ---
> > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
> > 1 file changed, 128 insertions(+), 128 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > index f483f62ab0c4..8dd1a3c60bc4 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > @@ -256,11 +256,11 @@ core3 {
> > cpu0: cpu@0 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
>
> Need not touch this. "riscv,isa" is deprecated and replaced by
> "riscv,isa-base" & "riscv,isa-extensions".
>
> And only adding zfh for this looks a bit werid.
>
> Actually, I plan to remove "riscv,isa" later, so please don't touch this
> from now on.
I think that since the linux kernel is the upstream for devicetree, it
cannot yet remove riscv, isa needs to maintain compatibility.
>
> Thanks,
>
> Chen
>
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <0>;
> > @@ -283,11 +283,11 @@ cpu0_intc: interrupt-controller {
> > cpu1: cpu@1 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <1>;
> > @@ -310,11 +310,11 @@ cpu1_intc: interrupt-controller {
> > cpu2: cpu@2 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <2>;
> > @@ -337,11 +337,11 @@ cpu2_intc: interrupt-controller {
> > cpu3: cpu@3 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <3>;
> > @@ -364,11 +364,11 @@ cpu3_intc: interrupt-controller {
> > cpu4: cpu@4 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <4>;
> > @@ -391,11 +391,11 @@ cpu4_intc: interrupt-controller {
> > cpu5: cpu@5 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <5>;
> > @@ -418,11 +418,11 @@ cpu5_intc: interrupt-controller {
> > cpu6: cpu@6 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <6>;
> > @@ -445,11 +445,11 @@ cpu6_intc: interrupt-controller {
> > cpu7: cpu@7 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <7>;
> > @@ -472,11 +472,11 @@ cpu7_intc: interrupt-controller {
> > cpu8: cpu@8 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <8>;
> > @@ -499,11 +499,11 @@ cpu8_intc: interrupt-controller {
> > cpu9: cpu@9 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <9>;
> > @@ -526,11 +526,11 @@ cpu9_intc: interrupt-controller {
> > cpu10: cpu@10 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <10>;
> > @@ -553,11 +553,11 @@ cpu10_intc: interrupt-controller {
> > cpu11: cpu@11 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <11>;
> > @@ -580,11 +580,11 @@ cpu11_intc: interrupt-controller {
> > cpu12: cpu@12 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <12>;
> > @@ -607,11 +607,11 @@ cpu12_intc: interrupt-controller {
> > cpu13: cpu@13 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <13>;
> > @@ -634,11 +634,11 @@ cpu13_intc: interrupt-controller {
> > cpu14: cpu@14 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <14>;
> > @@ -661,11 +661,11 @@ cpu14_intc: interrupt-controller {
> > cpu15: cpu@15 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <15>;
> > @@ -688,11 +688,11 @@ cpu15_intc: interrupt-controller {
> > cpu16: cpu@16 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <16>;
> > @@ -715,11 +715,11 @@ cpu16_intc: interrupt-controller {
> > cpu17: cpu@17 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <17>;
> > @@ -742,11 +742,11 @@ cpu17_intc: interrupt-controller {
> > cpu18: cpu@18 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <18>;
> > @@ -769,11 +769,11 @@ cpu18_intc: interrupt-controller {
> > cpu19: cpu@19 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <19>;
> > @@ -796,11 +796,11 @@ cpu19_intc: interrupt-controller {
> > cpu20: cpu@20 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <20>;
> > @@ -823,11 +823,11 @@ cpu20_intc: interrupt-controller {
> > cpu21: cpu@21 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <21>;
> > @@ -850,11 +850,11 @@ cpu21_intc: interrupt-controller {
> > cpu22: cpu@22 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <22>;
> > @@ -877,11 +877,11 @@ cpu22_intc: interrupt-controller {
> > cpu23: cpu@23 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <23>;
> > @@ -904,11 +904,11 @@ cpu23_intc: interrupt-controller {
> > cpu24: cpu@24 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <24>;
> > @@ -931,11 +931,11 @@ cpu24_intc: interrupt-controller {
> > cpu25: cpu@25 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <25>;
> > @@ -958,11 +958,11 @@ cpu25_intc: interrupt-controller {
> > cpu26: cpu@26 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <26>;
> > @@ -985,11 +985,11 @@ cpu26_intc: interrupt-controller {
> > cpu27: cpu@27 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <27>;
> > @@ -1012,11 +1012,11 @@ cpu27_intc: interrupt-controller {
> > cpu28: cpu@28 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <28>;
> > @@ -1039,11 +1039,11 @@ cpu28_intc: interrupt-controller {
> > cpu29: cpu@29 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <29>;
> > @@ -1066,11 +1066,11 @@ cpu29_intc: interrupt-controller {
> > cpu30: cpu@30 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <30>;
> > @@ -1093,11 +1093,11 @@ cpu30_intc: interrupt-controller {
> > cpu31: cpu@31 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <31>;
> > @@ -1120,11 +1120,11 @@ cpu31_intc: interrupt-controller {
> > cpu32: cpu@32 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <32>;
> > @@ -1147,11 +1147,11 @@ cpu32_intc: interrupt-controller {
> > cpu33: cpu@33 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <33>;
> > @@ -1174,11 +1174,11 @@ cpu33_intc: interrupt-controller {
> > cpu34: cpu@34 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <34>;
> > @@ -1201,11 +1201,11 @@ cpu34_intc: interrupt-controller {
> > cpu35: cpu@35 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <35>;
> > @@ -1228,11 +1228,11 @@ cpu35_intc: interrupt-controller {
> > cpu36: cpu@36 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <36>;
> > @@ -1255,11 +1255,11 @@ cpu36_intc: interrupt-controller {
> > cpu37: cpu@37 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <37>;
> > @@ -1282,11 +1282,11 @@ cpu37_intc: interrupt-controller {
> > cpu38: cpu@38 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <38>;
> > @@ -1309,11 +1309,11 @@ cpu38_intc: interrupt-controller {
> > cpu39: cpu@39 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <39>;
> > @@ -1336,11 +1336,11 @@ cpu39_intc: interrupt-controller {
> > cpu40: cpu@40 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <40>;
> > @@ -1363,11 +1363,11 @@ cpu40_intc: interrupt-controller {
> > cpu41: cpu@41 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <41>;
> > @@ -1390,11 +1390,11 @@ cpu41_intc: interrupt-controller {
> > cpu42: cpu@42 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <42>;
> > @@ -1417,11 +1417,11 @@ cpu42_intc: interrupt-controller {
> > cpu43: cpu@43 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <43>;
> > @@ -1444,11 +1444,11 @@ cpu43_intc: interrupt-controller {
> > cpu44: cpu@44 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <44>;
> > @@ -1471,11 +1471,11 @@ cpu44_intc: interrupt-controller {
> > cpu45: cpu@45 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <45>;
> > @@ -1498,11 +1498,11 @@ cpu45_intc: interrupt-controller {
> > cpu46: cpu@46 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <46>;
> > @@ -1525,11 +1525,11 @@ cpu46_intc: interrupt-controller {
> > cpu47: cpu@47 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <47>;
> > @@ -1552,11 +1552,11 @@ cpu47_intc: interrupt-controller {
> > cpu48: cpu@48 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <48>;
> > @@ -1579,11 +1579,11 @@ cpu48_intc: interrupt-controller {
> > cpu49: cpu@49 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <49>;
> > @@ -1606,11 +1606,11 @@ cpu49_intc: interrupt-controller {
> > cpu50: cpu@50 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <50>;
> > @@ -1633,11 +1633,11 @@ cpu50_intc: interrupt-controller {
> > cpu51: cpu@51 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <51>;
> > @@ -1660,11 +1660,11 @@ cpu51_intc: interrupt-controller {
> > cpu52: cpu@52 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <52>;
> > @@ -1687,11 +1687,11 @@ cpu52_intc: interrupt-controller {
> > cpu53: cpu@53 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <53>;
> > @@ -1714,11 +1714,11 @@ cpu53_intc: interrupt-controller {
> > cpu54: cpu@54 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <54>;
> > @@ -1741,11 +1741,11 @@ cpu54_intc: interrupt-controller {
> > cpu55: cpu@55 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <55>;
> > @@ -1768,11 +1768,11 @@ cpu55_intc: interrupt-controller {
> > cpu56: cpu@56 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <56>;
> > @@ -1795,11 +1795,11 @@ cpu56_intc: interrupt-controller {
> > cpu57: cpu@57 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <57>;
> > @@ -1822,11 +1822,11 @@ cpu57_intc: interrupt-controller {
> > cpu58: cpu@58 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <58>;
> > @@ -1849,11 +1849,11 @@ cpu58_intc: interrupt-controller {
> > cpu59: cpu@59 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <59>;
> > @@ -1876,11 +1876,11 @@ cpu59_intc: interrupt-controller {
> > cpu60: cpu@60 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <60>;
> > @@ -1903,11 +1903,11 @@ cpu60_intc: interrupt-controller {
> > cpu61: cpu@61 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <61>;
> > @@ -1930,11 +1930,11 @@ cpu61_intc: interrupt-controller {
> > cpu62: cpu@62 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <62>;
> > @@ -1957,11 +1957,11 @@ cpu62_intc: interrupt-controller {
> > cpu63: cpu@63 {
> > compatible = "thead,c920", "riscv";
> > device_type = "cpu";
> > - riscv,isa = "rv64imafdc";
> > + riscv,isa = "rv64imafdc_zfh";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > "ziccrse", "zicntr", "zicsr",
> > - "zifencei", "zihpm",
> > + "zifencei", "zihpm", "zfh",
> > "xtheadvector";
> > thead,vlenb = <16>;
> > reg = <63>;
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-27 9:34 ` Han Gao
@ 2025-05-27 10:22 ` Chen Wang
2025-05-31 1:34 ` Inochi Amaoto
0 siblings, 1 reply; 20+ messages in thread
From: Chen Wang @ 2025-05-27 10:22 UTC (permalink / raw)
To: Han Gao
Cc: devicetree, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Inochi Amaoto, linux-riscv, sophgo, linux-kernel
On 2025/5/27 17:34, Han Gao wrote:
> On Thu, May 15, 2025 at 9:33 AM Chen Wang <unicorn_wang@outlook.com> wrote:
>>
>> On 2025/5/14 23:15, Han Gao wrote:
>>> sg2042 support Zfh ISA extension [1].
>>>
>>> Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
>>>
>>> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
>>> ---
>>> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
>>> 1 file changed, 128 insertions(+), 128 deletions(-)
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> index f483f62ab0c4..8dd1a3c60bc4 100644
>>> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> @@ -256,11 +256,11 @@ core3 {
>>> cpu0: cpu@0 {
>>> compatible = "thead,c920", "riscv";
>>> device_type = "cpu";
>>> - riscv,isa = "rv64imafdc";
>>> + riscv,isa = "rv64imafdc_zfh";
>> Need not touch this. "riscv,isa" is deprecated and replaced by
>> "riscv,isa-base" & "riscv,isa-extensions".
>>
>> And only adding zfh for this looks a bit werid.
>>
>> Actually, I plan to remove "riscv,isa" later, so please don't touch this
>> from now on.
> I think that since the linux kernel is the upstream for devicetree, it
> cannot yet remove riscv, isa needs to maintain compatibility.
OK, maybe it's not good to remove "riscv,isa".
Can this patch not modify "riscv,isa", but only add something for
"riscv,isa-extensions"?
Chen
>> Thanks,
>>
>> Chen
>>
>>> riscv,isa-base = "rv64i";
>>> riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>> "ziccrse", "zicntr", "zicsr",
>>> - "zifencei", "zihpm",
>>> + "zifencei", "zihpm", "zfh",
>>> "xtheadvector";
>>> thead,vlenb = <16>;
>>> reg = <0>;
[......]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-27 10:22 ` Chen Wang
@ 2025-05-31 1:34 ` Inochi Amaoto
2025-05-31 2:49 ` Chen Wang
0 siblings, 1 reply; 20+ messages in thread
From: Inochi Amaoto @ 2025-05-31 1:34 UTC (permalink / raw)
To: Chen Wang, Han Gao
Cc: devicetree, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Inochi Amaoto, linux-riscv, sophgo, linux-kernel
On Tue, May 27, 2025 at 06:22:05PM +0800, Chen Wang wrote:
>
> On 2025/5/27 17:34, Han Gao wrote:
> > On Thu, May 15, 2025 at 9:33 AM Chen Wang <unicorn_wang@outlook.com> wrote:
> > >
> > > On 2025/5/14 23:15, Han Gao wrote:
> > > > sg2042 support Zfh ISA extension [1].
> > > >
> > > > Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
> > > >
> > > > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> > > > ---
> > > > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
> > > > 1 file changed, 128 insertions(+), 128 deletions(-)
> > > >
> > > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > index f483f62ab0c4..8dd1a3c60bc4 100644
> > > > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > @@ -256,11 +256,11 @@ core3 {
> > > > cpu0: cpu@0 {
> > > > compatible = "thead,c920", "riscv";
> > > > device_type = "cpu";
> > > > - riscv,isa = "rv64imafdc";
> > > > + riscv,isa = "rv64imafdc_zfh";
> > > Need not touch this. "riscv,isa" is deprecated and replaced by
> > > "riscv,isa-base" & "riscv,isa-extensions".
> > >
> > > And only adding zfh for this looks a bit werid.
> > >
> > > Actually, I plan to remove "riscv,isa" later, so please don't touch this
> > > from now on.
> > I think that since the linux kernel is the upstream for devicetree, it
> > cannot yet remove riscv, isa needs to maintain compatibility.
>
> OK, maybe it's not good to remove "riscv,isa".
>
> Can this patch not modify "riscv,isa", but only add something for
> "riscv,isa-extensions"?
>
I can remove this while merging the patch, is it OK for you?
Regards,
Inochi
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-31 1:34 ` Inochi Amaoto
@ 2025-05-31 2:49 ` Chen Wang
2025-06-06 16:01 ` Conor Dooley
0 siblings, 1 reply; 20+ messages in thread
From: Chen Wang @ 2025-05-31 2:49 UTC (permalink / raw)
To: Inochi Amaoto, Han Gao
Cc: devicetree, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
linux-riscv, sophgo, linux-kernel
On 2025/5/31 9:34, Inochi Amaoto wrote:
> On Tue, May 27, 2025 at 06:22:05PM +0800, Chen Wang wrote:
>> On 2025/5/27 17:34, Han Gao wrote:
>>> On Thu, May 15, 2025 at 9:33 AM Chen Wang <unicorn_wang@outlook.com> wrote:
>>>> On 2025/5/14 23:15, Han Gao wrote:
>>>>> sg2042 support Zfh ISA extension [1].
>>>>>
>>>>> Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
>>>>>
>>>>> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
>>>>> ---
>>>>> arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
>>>>> 1 file changed, 128 insertions(+), 128 deletions(-)
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>>>> index f483f62ab0c4..8dd1a3c60bc4 100644
>>>>> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>>>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>>>> @@ -256,11 +256,11 @@ core3 {
>>>>> cpu0: cpu@0 {
>>>>> compatible = "thead,c920", "riscv";
>>>>> device_type = "cpu";
>>>>> - riscv,isa = "rv64imafdc";
>>>>> + riscv,isa = "rv64imafdc_zfh";
>>>> Need not touch this. "riscv,isa" is deprecated and replaced by
>>>> "riscv,isa-base" & "riscv,isa-extensions".
>>>>
>>>> And only adding zfh for this looks a bit werid.
>>>>
>>>> Actually, I plan to remove "riscv,isa" later, so please don't touch this
>>>> from now on.
>>> I think that since the linux kernel is the upstream for devicetree, it
>>> cannot yet remove riscv, isa needs to maintain compatibility.
>> OK, maybe it's not good to remove "riscv,isa".
>>
>> Can this patch not modify "riscv,isa", but only add something for
>> "riscv,isa-extensions"?
>>
> I can remove this while merging the patch, is it OK for you?
>
> Regards,
> Inochi
@Inochi,
Han does not want to remove this "riscv,isa"，he said some other
components, such as u-boot may have dependency on this.
@Han, please provide more info if needed.
Thanks,
Chen
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042
2025-05-31 2:49 ` Chen Wang
@ 2025-06-06 16:01 ` Conor Dooley
0 siblings, 0 replies; 20+ messages in thread
From: Conor Dooley @ 2025-06-06 16:01 UTC (permalink / raw)
To: Chen Wang
Cc: Inochi Amaoto, Han Gao, devicetree, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, linux-riscv, sophgo, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2400 bytes --]
On Sat, May 31, 2025 at 10:49:58AM +0800, Chen Wang wrote:
>
> On 2025/5/31 9:34, Inochi Amaoto wrote:
> > On Tue, May 27, 2025 at 06:22:05PM +0800, Chen Wang wrote:
> > > On 2025/5/27 17:34, Han Gao wrote:
> > > > On Thu, May 15, 2025 at 9:33 AM Chen Wang <unicorn_wang@outlook.com> wrote:
> > > > > On 2025/5/14 23:15, Han Gao wrote:
> > > > > > sg2042 support Zfh ISA extension [1].
> > > > > >
> > > > > > Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1]
> > > > > >
> > > > > > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> > > > > > ---
> > > > > > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 256 ++++++++++----------
> > > > > > 1 file changed, 128 insertions(+), 128 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > > > index f483f62ab0c4..8dd1a3c60bc4 100644
> > > > > > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > > > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > > > > > @@ -256,11 +256,11 @@ core3 {
> > > > > > cpu0: cpu@0 {
> > > > > > compatible = "thead,c920", "riscv";
> > > > > > device_type = "cpu";
> > > > > > - riscv,isa = "rv64imafdc";
> > > > > > + riscv,isa = "rv64imafdc_zfh";
> > > > > Need not touch this. "riscv,isa" is deprecated and replaced by
> > > > > "riscv,isa-base" & "riscv,isa-extensions".
> > > > >
> > > > > And only adding zfh for this looks a bit werid.
> > > > >
> > > > > Actually, I plan to remove "riscv,isa" later, so please don't touch this
> > > > > from now on.
> > > > I think that since the linux kernel is the upstream for devicetree, it
> > > > cannot yet remove riscv, isa needs to maintain compatibility.
> > > OK, maybe it's not good to remove "riscv,isa".
> > >
> > > Can this patch not modify "riscv,isa", but only add something for
> > > "riscv,isa-extensions"?
> > >
> > I can remove this while merging the patch, is it OK for you?
> Han does not want to remove this "riscv,isa"，he said some other components,
> such as u-boot may have dependency on this.
U-Boot shouldn't, what actually needs it, opensbi?
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^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2025-06-06 16:01 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-14 11:55 [PATCH 0/2] Add u-blox,neo-m9 compatible Alejandro Enrique via B4 Relay
2025-05-14 11:55 ` [PATCH 1/2] dt-bindings: gnss: add u-blox,neo-9m compatible Alejandro Enrique via B4 Relay
2025-05-14 15:49 ` [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042 Conor Dooley
[not found] ` <CAN=L63qsjEAvfocgP0tGrpe-x6Rx1gvTAkPE9i99Ai2zJj6ssA@mail.gmail.com>
2025-05-15 15:02 ` Conor Dooley
2025-05-16 10:23 ` Alejandro Enrique
2025-05-16 14:01 ` Conor Dooley
2025-05-16 15:00 ` Alejandro Enrique
2025-05-19 12:37 ` Conor Dooley
2025-05-19 12:59 ` Johan Hovold
2025-05-21 16:12 ` Alejandro Enrique
2025-05-19 13:06 ` Johan Hovold
2025-05-19 15:12 ` Conor Dooley
2025-05-14 11:55 ` [PATCH 2/2] gnss: ubx: add u-blox,neo-m9 compatible Alejandro Enrique via B4 Relay
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2025-05-14 15:15 [PATCH v2 0/3] riscv: dts: sophgo: add more sg2042 isa extension support Han Gao
2025-05-14 15:15 ` [PATCH v2 3/3] riscv: dts: sophgo: add zfh for sg2042 Han Gao
2025-05-15 1:33 ` Chen Wang
2025-05-27 9:34 ` Han Gao
2025-05-27 10:22 ` Chen Wang
2025-05-31 1:34 ` Inochi Amaoto
2025-05-31 2:49 ` Chen Wang
2025-06-06 16:01 ` Conor Dooley
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