[PATCH v2] dt-bindings: riscv: Add SiFive vendor extensions description

[PATCH v2] dt-bindings: riscv: Add SiFive vendor extensions description

[Nick Hu]

Add description for SiFive vendor extensions "xsfcflushdlone",
"xsfpgflushdlone" and "xsfcease". This is used in the SBI
implementation [1].

[1] https://lore.kernel.org/opensbi/20250708074940.10904-1-nick.hu@sifive.com/

Changes in v2:
- Update the message to indicate the user of the extensions.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
---
 .../devicetree/bindings/riscv/extensions.yaml  | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ede6a58ccf53..5638297759df 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -663,6 +663,24 @@ properties:
             https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
 
         # SiFive
+        - const: xsfcease
+          description:
+            SiFive CEASE Instruction Extensions Specification.
+            See more details in
+            https://www.sifive.com/document-file/freedom-u740-c000-manual
+
+        - const: xsfcflushdlone
+          description:
+            SiFive L1D Cache Flush Instruction Extensions Specification.
+            See more details in
+            https://www.sifive.com/document-file/freedom-u740-c000-manual
+
+        - const: xsfpgflushdlone
+          description:
+            SiFive PGFLUSH Instruction Extensions for the power management. The
+            CPU will flush the L1D and enter the cease state after executing
+            the instruction.
+
         - const: xsfvqmaccdod
           description:
             SiFive Int8 Matrix Multiplication Extensions Specification.
-- 
2.17.1

Re: [PATCH v2] dt-bindings: riscv: Add SiFive vendor extensions description

[Conor Dooley]

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On Fri, Aug 01, 2025 at 03:01:12PM +0800, Nick Hu wrote:
> Add description for SiFive vendor extensions "xsfcflushdlone",
> "xsfpgflushdlone" and "xsfcease". This is used in the SBI
> implementation [1].
> 
> [1] https://lore.kernel.org/opensbi/20250708074940.10904-1-nick.hu@sifive.com/
> 

> Changes in v2:
> - Update the message to indicate the user of the extensions.

This should be below the --- line.
With that,
Acked-by: Conor Dooley <conor.dooley@microchip.com>
although I suppose it'll be me taking this and I can fix it up on
application?

> 
> Signed-off-by: Nick Hu <nick.hu@sifive.com>
> ---
>  .../devicetree/bindings/riscv/extensions.yaml  | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index ede6a58ccf53..5638297759df 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -663,6 +663,24 @@ properties:
>              https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>  
>          # SiFive
> +        - const: xsfcease
> +          description:
> +            SiFive CEASE Instruction Extensions Specification.
> +            See more details in
> +            https://www.sifive.com/document-file/freedom-u740-c000-manual
> +
> +        - const: xsfcflushdlone
> +          description:
> +            SiFive L1D Cache Flush Instruction Extensions Specification.
> +            See more details in
> +            https://www.sifive.com/document-file/freedom-u740-c000-manual
> +
> +        - const: xsfpgflushdlone
> +          description:
> +            SiFive PGFLUSH Instruction Extensions for the power management. The
> +            CPU will flush the L1D and enter the cease state after executing
> +            the instruction.
> +
>          - const: xsfvqmaccdod
>            description:
>              SiFive Int8 Matrix Multiplication Extensions Specification.
> -- 
> 2.17.1
> 

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Re: [PATCH v2] dt-bindings: riscv: Add SiFive vendor extensions description

[Nick Hu]

On Sat, Aug 2, 2025 at 3:31 AM Conor Dooley <conor@kernel.org> wrote:
>
> On Fri, Aug 01, 2025 at 03:01:12PM +0800, Nick Hu wrote:
> > Add description for SiFive vendor extensions "xsfcflushdlone",
> > "xsfpgflushdlone" and "xsfcease". This is used in the SBI
> > implementation [1].
> >
> > [1] https://lore.kernel.org/opensbi/20250708074940.10904-1-nick.hu@sifive.com/
> >
>
> > Changes in v2:
> > - Update the message to indicate the user of the extensions.
>
> This should be below the --- line.
> With that,
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> although I suppose it'll be me taking this and I can fix it up on
> application?
>
Thanks! That would be really helpful.

Best Regards,
Nick
> >
> > Signed-off-by: Nick Hu <nick.hu@sifive.com>
> > ---
> >  .../devicetree/bindings/riscv/extensions.yaml  | 18 ++++++++++++++++++
> >  1 file changed, 18 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > index ede6a58ccf53..5638297759df 100644
> > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> > @@ -663,6 +663,24 @@ properties:
> >              https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> >
> >          # SiFive
> > +        - const: xsfcease
> > +          description:
> > +            SiFive CEASE Instruction Extensions Specification.
> > +            See more details in
> > +            https://www.sifive.com/document-file/freedom-u740-c000-manual
> > +
> > +        - const: xsfcflushdlone
> > +          description:
> > +            SiFive L1D Cache Flush Instruction Extensions Specification.
> > +            See more details in
> > +            https://www.sifive.com/document-file/freedom-u740-c000-manual
> > +
> > +        - const: xsfpgflushdlone
> > +          description:
> > +            SiFive PGFLUSH Instruction Extensions for the power management. The
> > +            CPU will flush the L1D and enter the cease state after executing
> > +            the instruction.
> > +
> >          - const: xsfvqmaccdod
> >            description:
> >              SiFive Int8 Matrix Multiplication Extensions Specification.
> > --
> > 2.17.1
> >

Re: [PATCH v2] dt-bindings: riscv: Add SiFive vendor extensions description

[Conor Dooley]

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On Tue, Aug 05, 2025 at 11:38:34AM +0800, Nick Hu wrote:
> On Sat, Aug 2, 2025 at 3:31 AM Conor Dooley <conor@kernel.org> wrote:
> >
> > On Fri, Aug 01, 2025 at 03:01:12PM +0800, Nick Hu wrote:
> > > Add description for SiFive vendor extensions "xsfcflushdlone",
> > > "xsfpgflushdlone" and "xsfcease". This is used in the SBI
> > > implementation [1].
> > >
> > > [1] https://lore.kernel.org/opensbi/20250708074940.10904-1-nick.hu@sifive.com/
> > >
> >
> > > Changes in v2:
> > > - Update the message to indicate the user of the extensions.
> >
> > This should be below the --- line.
> > With that,
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > although I suppose it'll be me taking this and I can fix it up on
> > application?
> >
> Thanks! That would be really helpful.

Done, applied for 6.18 material.

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