* [PATCH 1/7] clk: renesas: r9a09g077: Add ADC modules clock
2025-09-23 16:05 [PATCH 0/7] Add ADCs support for RZ/T2H and RZ/N2H Cosmin Tanislav
@ 2025-09-23 16:05 ` Cosmin Tanislav
2025-09-24 11:49 ` Geert Uytterhoeven
2025-09-23 16:05 ` [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC Cosmin Tanislav
` (5 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Cosmin Tanislav @ 2025-09-23 16:05 UTC (permalink / raw)
Cc: Cosmin Tanislav, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three 12bit
ADC peripherals, each with its own peripheral clock.
For conversion, they use the PCLKL clock.
Add their clocks to the list of module clocks.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
drivers/clk/renesas/r9a09g077-cpg.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g077-cpg.c b/drivers/clk/renesas/r9a09g077-cpg.c
index 3aaa154102d5..5dca5c44043e 100644
--- a/drivers/clk/renesas/r9a09g077-cpg.c
+++ b/drivers/clk/renesas/r9a09g077-cpg.c
@@ -192,6 +192,9 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
+ DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
+ DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
+ DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),
DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),
DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),
--
2.51.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/7] clk: renesas: r9a09g077: Add ADC modules clock
2025-09-23 16:05 ` [PATCH 1/7] clk: renesas: r9a09g077: Add ADC modules clock Cosmin Tanislav
@ 2025-09-24 11:49 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-09-24 11:49 UTC (permalink / raw)
To: Cosmin Tanislav
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Magnus Damm,
Michael Turquette, Stephen Boyd, Lad Prabhakar, linux-iio,
linux-renesas-soc, devicetree, linux-kernel, linux-clk
On Tue, 23 Sept 2025 at 18:06, Cosmin Tanislav
<cosmin-gabriel.tanislav.xa@renesas.com> wrote:
> Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs have three 12bit
> ADC peripherals, each with its own peripheral clock.
>
> For conversion, they use the PCLKL clock.
>
> Add their clocks to the list of module clocks.
>
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
2025-09-23 16:05 [PATCH 0/7] Add ADCs support for RZ/T2H and RZ/N2H Cosmin Tanislav
2025-09-23 16:05 ` [PATCH 1/7] clk: renesas: r9a09g077: Add ADC modules clock Cosmin Tanislav
@ 2025-09-23 16:05 ` Cosmin Tanislav
2025-09-23 18:41 ` Conor Dooley
2025-09-24 7:51 ` Geert Uytterhoeven
2025-09-23 16:05 ` [PATCH 3/7] iio: adc: add RZ/T2H / RZ/N2H ADC driver Cosmin Tanislav
` (4 subsequent siblings)
6 siblings, 2 replies; 17+ messages in thread
From: Cosmin Tanislav @ 2025-09-23 16:05 UTC (permalink / raw)
Cc: Cosmin Tanislav, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
Document the A/D 12-Bit successive approximation converters found in the
Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
RZ/T2H has two ADCs with 4 channels and one with 6.
RZ/N2H has two ADCs with 4 channels and one with 15.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../iio/adc/renesas,r9a09g077-adc.yaml | 170 ++++++++++++++++++
MAINTAINERS | 7 +
2 files changed, 177 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
new file mode 100644
index 000000000000..840108cd317e
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
@@ -0,0 +1,170 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/T2H / RZ/N2H ADC12
+
+maintainers:
+ - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
+
+description: |
+ A/D Converter block is a successive approximation analog-to-digital converter
+ with a 12-bit accuracy. Up to 15 analog input channels can be selected.
+ Conversions can be performed in single or continuous mode. Result of the ADC
+ is stored in a 16-bit data register corresponding to each channel.
+
+properties:
+ compatible:
+ enum:
+ - renesas,r9a09g077-adc # RZ/T2H
+ - renesas,r9a09g087-adc # RZ/N2H
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: A/D scan end interrupt
+ - description: A/D scan end interrupt for Group B
+ - description: A/D scan end interrupt for Group C
+ - description: Window A compare match
+ - description: Window B compare match
+ - description: Compare match
+ - description: Compare mismatch
+
+ interrupt-names:
+ items:
+ - const: adi
+ - const: gbadi
+ - const: gcadi
+ - const: cmpai
+ - const: cmpbi
+ - const: wcmpm
+ - const: wcmpum
+
+ clocks:
+ items:
+ - description: converter clock
+ - description: peripheral clock
+
+ clock-names:
+ items:
+ - const: adclk
+ - const: pclk
+
+ power-domains:
+ maxItems: 1
+
+ renesas,max-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Maximum number of channels supported by the ADC.
+ RZ/T2H has two ADCs with 4 channels and one with 6 channels.
+ RZ/N2H has two ADCs with 4 channels and one with 15 channels.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ "#io-channel-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - power-domains
+ - renesas,max-channels
+
+patternProperties:
+ "^channel@[0-9a-e]$":
+ $ref: adc.yaml
+ type: object
+ description: The external channels which are connected to the ADC.
+
+ properties:
+ reg:
+ description: The channel number.
+ maximum: 14
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,r9a09g077-adc
+ then:
+ properties:
+ renesas,max-channels:
+ enum: [4, 6]
+
+ patternProperties:
+ "^channel@[6-9a-e]$": false
+ "^channel@[0-5]$":
+ properties:
+ reg:
+ maximum: 5
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,r9a09g087-adc
+ then:
+ properties:
+ renesas,max-channels:
+ enum: [4, 15]
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ adc@80008000 {
+ compatible = "renesas,r9a09g077-adc";
+ reg = <0x80008000 0x400>;
+ interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adi", "gbadi", "gcadi",
+ "cmpai", "cmpbi", "wcmpm", "wcmpum";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
+ <&cpg CPG_MOD 225>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ renesas,max-channels = <6>;
+
+ channel@0 {
+ reg = <0x0>;
+ };
+ channel@1 {
+ reg = <0x1>;
+ };
+ channel@2 {
+ reg = <0x2>;
+ };
+ channel@3 {
+ reg = <0x3>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 9f4b48801879..07e0d37cf468 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21822,6 +21822,13 @@ S: Supported
F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
F: drivers/counter/rz-mtu3-cnt.c
+RENESAS RZ/T2H / RZ/N2H A/D DRIVER
+M: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
+L: linux-iio@vger.kernel.org
+L: linux-renesas-soc@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
+
RENESAS RTCA-3 RTC DRIVER
M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
L: linux-rtc@vger.kernel.org
--
2.51.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
2025-09-23 16:05 ` [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC Cosmin Tanislav
@ 2025-09-23 18:41 ` Conor Dooley
2025-09-23 20:14 ` Cosmin-Gabriel Tanislav
2025-09-24 7:51 ` Geert Uytterhoeven
1 sibling, 1 reply; 17+ messages in thread
From: Conor Dooley @ 2025-09-23 18:41 UTC (permalink / raw)
To: Cosmin Tanislav
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
[-- Attachment #1: Type: text/plain, Size: 6879 bytes --]
On Tue, Sep 23, 2025 at 07:05:16PM +0300, Cosmin Tanislav wrote:
> Document the A/D 12-Bit successive approximation converters found in the
> Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
>
> RZ/T2H has two ADCs with 4 channels and one with 6.
> RZ/N2H has two ADCs with 4 channels and one with 15.
>
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> ---
> .../iio/adc/renesas,r9a09g077-adc.yaml | 170 ++++++++++++++++++
> MAINTAINERS | 7 +
> 2 files changed, 177 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> new file mode 100644
> index 000000000000..840108cd317e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> @@ -0,0 +1,170 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/T2H / RZ/N2H ADC12
> +
> +maintainers:
> + - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> +
> +description: |
> + A/D Converter block is a successive approximation analog-to-digital converter
> + with a 12-bit accuracy. Up to 15 analog input channels can be selected.
> + Conversions can be performed in single or continuous mode. Result of the ADC
> + is stored in a 16-bit data register corresponding to each channel.
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,r9a09g077-adc # RZ/T2H
> + - renesas,r9a09g087-adc # RZ/N2H
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: A/D scan end interrupt
> + - description: A/D scan end interrupt for Group B
> + - description: A/D scan end interrupt for Group C
> + - description: Window A compare match
> + - description: Window B compare match
> + - description: Compare match
> + - description: Compare mismatch
> +
> + interrupt-names:
> + items:
> + - const: adi
> + - const: gbadi
> + - const: gcadi
> + - const: cmpai
> + - const: cmpbi
> + - const: wcmpm
> + - const: wcmpum
> +
> + clocks:
> + items:
> + - description: converter clock
> + - description: peripheral clock
> +
> + clock-names:
> + items:
> + - const: adclk
> + - const: pclk
> +
> + power-domains:
> + maxItems: 1
> +
> + renesas,max-channels:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Maximum number of channels supported by the ADC.
> + RZ/T2H has two ADCs with 4 channels and one with 6 channels.
> + RZ/N2H has two ADCs with 4 channels and one with 15 channels.
What is the point of this? Why do you need to know how many channels
there can be in the driver, isn't it enough to just figure out how many
child nodes you have?
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + "#io-channel-cells":
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - power-domains
> + - renesas,max-channels
This should be after patternProperties.
> +
> +patternProperties:
> + "^channel@[0-9a-e]$":
> + $ref: adc.yaml
> + type: object
> + description: The external channels which are connected to the ADC.
> +
> + properties:
> + reg:
> + description: The channel number.
> + maximum: 14
> +
> + required:
> + - reg
> +
> + additionalProperties: false
You don't include any properties other than reg from adc.yaml, and using
additionalProperties: false blocks their use. Is that intentional or
should this be unevaluatedProperties: false?
Cheers,
Conor.
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g077-adc
> + then:
> + properties:
> + renesas,max-channels:
> + enum: [4, 6]
> +
> + patternProperties:
> + "^channel@[6-9a-e]$": false
> + "^channel@[0-5]$":
> + properties:
> + reg:
> + maximum: 5
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,r9a09g087-adc
> + then:
> + properties:
> + renesas,max-channels:
> + enum: [4, 15]
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + adc@80008000 {
> + compatible = "renesas,r9a09g077-adc";
> + reg = <0x80008000 0x400>;
> + interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "adi", "gbadi", "gcadi",
> + "cmpai", "cmpbi", "wcmpm", "wcmpum";
> + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
> + <&cpg CPG_MOD 225>;
> + clock-names = "adclk", "pclk";
> + power-domains = <&cpg>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + renesas,max-channels = <6>;
> +
> + channel@0 {
> + reg = <0x0>;
> + };
> + channel@1 {
> + reg = <0x1>;
> + };
> + channel@2 {
> + reg = <0x2>;
> + };
> + channel@3 {
> + reg = <0x3>;
> + };
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 9f4b48801879..07e0d37cf468 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21822,6 +21822,13 @@ S: Supported
> F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
> F: drivers/counter/rz-mtu3-cnt.c
>
> +RENESAS RZ/T2H / RZ/N2H A/D DRIVER
> +M: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> +L: linux-iio@vger.kernel.org
> +L: linux-renesas-soc@vger.kernel.org
> +S: Supported
> +F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> +
> RENESAS RTCA-3 RTC DRIVER
> M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> L: linux-rtc@vger.kernel.org
> --
> 2.51.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
2025-09-23 18:41 ` Conor Dooley
@ 2025-09-23 20:14 ` Cosmin-Gabriel Tanislav
2025-09-23 23:07 ` Conor Dooley
0 siblings, 1 reply; 17+ messages in thread
From: Cosmin-Gabriel Tanislav @ 2025-09-23 20:14 UTC (permalink / raw)
To: Conor Dooley
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, Michael Turquette, Stephen Boyd,
Prabhakar Mahadev Lad, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: Tuesday, September 23, 2025 9:42 PM
> To: Cosmin-Gabriel Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> Cc: Jonathan Cameron <jic23@kernel.org>; David Lechner
> <dlechner@baylibre.com>; Nuno Sá <nuno.sa@analog.com>; Andy Shevchenko
> <andy@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Geert
> Uytterhoeven <geert+renesas@glider.be>; magnus.damm
> <magnus.damm@gmail.com>; Michael Turquette <mturquette@baylibre.com>;
> Stephen Boyd <sboyd@kernel.org>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; linux-iio@vger.kernel.org; linux-renesas-
> soc@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-clk@vger.kernel.org
> Subject: Re: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H
> ADC
>
> On Tue, Sep 23, 2025 at 07:05:16PM +0300, Cosmin Tanislav wrote:
> > Document the A/D 12-Bit successive approximation converters found in the
> > Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
> >
> > RZ/T2H has two ADCs with 4 channels and one with 6.
> > RZ/N2H has two ADCs with 4 channels and one with 15.
> >
> > Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > ---
> > .../iio/adc/renesas,r9a09g077-adc.yaml | 170 ++++++++++++++++++
> > MAINTAINERS | 7 +
> > 2 files changed, 177 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-
> adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-
> adc.yaml
> > new file mode 100644
> > index 000000000000..840108cd317e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-
> adc.yaml
> > @@ -0,0 +1,170 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Renesas RZ/T2H / RZ/N2H ADC12
> > +
> > +maintainers:
> > + - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > +
> > +description: |
> > + A/D Converter block is a successive approximation analog-to-digital
> converter
> > + with a 12-bit accuracy. Up to 15 analog input channels can be
> selected.
> > + Conversions can be performed in single or continuous mode. Result of
> the ADC
> > + is stored in a 16-bit data register corresponding to each channel.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - renesas,r9a09g077-adc # RZ/T2H
> > + - renesas,r9a09g087-adc # RZ/N2H
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + items:
> > + - description: A/D scan end interrupt
> > + - description: A/D scan end interrupt for Group B
> > + - description: A/D scan end interrupt for Group C
> > + - description: Window A compare match
> > + - description: Window B compare match
> > + - description: Compare match
> > + - description: Compare mismatch
> > +
> > + interrupt-names:
> > + items:
> > + - const: adi
> > + - const: gbadi
> > + - const: gcadi
> > + - const: cmpai
> > + - const: cmpbi
> > + - const: wcmpm
> > + - const: wcmpum
> > +
> > + clocks:
> > + items:
> > + - description: converter clock
> > + - description: peripheral clock
> > +
> > + clock-names:
> > + items:
> > + - const: adclk
> > + - const: pclk
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + renesas,max-channels:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + Maximum number of channels supported by the ADC.
> > + RZ/T2H has two ADCs with 4 channels and one with 6 channels.
> > + RZ/N2H has two ADCs with 4 channels and one with 15 channels.
>
> What is the point of this? Why do you need to know how many channels
> there can be in the driver, isn't it enough to just figure out how many
> child nodes you have?
>
The idea here was that the SoC dtsi file would define the number of
channels supported by each instance of the ADC peripheral, while the
board dtsi (which includes the SoC dtsi) would define the number of
channels actually wired up on the.
Alternatively, we could have multiple compatibles for each SoC, like
renesas,r9a09g077-adc-4, which would only have 4 channels, while
the main renesas,r9a09g077-adc compatible would be the one with the
most channels, 6.
There might exist instances where knowing how many channels the chip
has might be useful inside the driver, but the bindings themselves
shouldn't really be addressing driver requirements, they should be
describing the hardware properties.
The maximum number of supported channels of each ADC instance is a
property of the hardware, which is fine to have in the bindings.
Also, it is useful to know the maximum number of channels,
otherwise, we would have to iterate over the iio_chan_spec
populated by devm_iio_adc_device_alloc_chaninfo_se() to figure out
what is the maximum used channel. We will surely need this
information when implementing buffered mode, to know up to which
register to read data from, and we already need it when iterating
over the enabled channels for the same reason.
All things considered, I think it is useful to have this property
here, considering the separation between SoC capabilities and board
implementation.
> > +
> > + '#address-cells':
> > + const: 1
> > +
> > + '#size-cells':
> > + const: 0
> > +
> > + "#io-channel-cells":
> > + const: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - renesas,max-channels
>
> This should be after patternProperties.
>
Ack.
> > +
> > +patternProperties:
> > + "^channel@[0-9a-e]$":
> > + $ref: adc.yaml
> > + type: object
> > + description: The external channels which are connected to the ADC.
> > +
> > + properties:
> > + reg:
> > + description: The channel number.
> > + maximum: 14
> > +
> > + required:
> > + - reg
> > +
>
> > + additionalProperties: false
>
> You don't include any properties other than reg from adc.yaml, and using
> additionalProperties: false blocks their use. Is that intentional or
> should this be unevaluatedProperties: false?
>
I don't think we need any other properties besides reg at this point,
and reg is the only property actually handled by the driver, via
devm_iio_adc_device_alloc_chaninfo_se().
> Cheers,
> Conor.
>
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a09g077-adc
> > + then:
> > + properties:
> > + renesas,max-channels:
> > + enum: [4, 6]
> > +
> > + patternProperties:
> > + "^channel@[6-9a-e]$": false
> > + "^channel@[0-5]$":
> > + properties:
> > + reg:
> > + maximum: 5
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - renesas,r9a09g087-adc
> > + then:
> > + properties:
> > + renesas,max-channels:
> > + enum: [4, 15]
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + adc@80008000 {
> > + compatible = "renesas,r9a09g077-adc";
> > + reg = <0x80008000 0x400>;
> > + interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "adi", "gbadi", "gcadi",
> > + "cmpai", "cmpbi", "wcmpm", "wcmpum";
> > + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
> > + <&cpg CPG_MOD 225>;
> > + clock-names = "adclk", "pclk";
> > + power-domains = <&cpg>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #io-channel-cells = <1>;
> > + renesas,max-channels = <6>;
> > +
> > + channel@0 {
> > + reg = <0x0>;
> > + };
> > + channel@1 {
> > + reg = <0x1>;
> > + };
> > + channel@2 {
> > + reg = <0x2>;
> > + };
> > + channel@3 {
> > + reg = <0x3>;
> > + };
> > + };
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 9f4b48801879..07e0d37cf468 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -21822,6 +21822,13 @@ S: Supported
> > F: Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
> > F: drivers/counter/rz-mtu3-cnt.c
> >
> > +RENESAS RZ/T2H / RZ/N2H A/D DRIVER
> > +M: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > +L: linux-iio@vger.kernel.org
> > +L: linux-renesas-soc@vger.kernel.org
> > +S: Supported
> > +F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> > +
> > RENESAS RTCA-3 RTC DRIVER
> > M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > L: linux-rtc@vger.kernel.org
> > --
> > 2.51.0
> >
________________________________
Renesas Electronics Europe GmbH
Registered Office: Arcadiastrasse 10
DE-40472 Duesseldorf
Commercial Registry: Duesseldorf, HRB 3708
Managing Director: Carsten Jauch
VAT-No.: DE 14978647
Tax-ID-No: 105/5839/1793
Legal Disclaimer: This e-mail communication (and any attachment/s) is confidential and contains proprietary information, some or all of which may be legally privileged. It is intended solely for the use of the individual or entity to which it is addressed. Access to this email by anyone else is unauthorized. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited and may be unlawful.
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
2025-09-23 20:14 ` Cosmin-Gabriel Tanislav
@ 2025-09-23 23:07 ` Conor Dooley
0 siblings, 0 replies; 17+ messages in thread
From: Conor Dooley @ 2025-09-23 23:07 UTC (permalink / raw)
To: Cosmin-Gabriel Tanislav
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, Michael Turquette, Stephen Boyd,
Prabhakar Mahadev Lad, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
[-- Attachment #1: Type: text/plain, Size: 4451 bytes --]
On Tue, Sep 23, 2025 at 08:14:09PM +0000, Cosmin-Gabriel Tanislav wrote:
> > From: Conor Dooley <conor@kernel.org>
> > On Tue, Sep 23, 2025 at 07:05:16PM +0300, Cosmin Tanislav wrote:
> > > Document the A/D 12-Bit successive approximation converters found in the
> > > Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
> > >
> > > RZ/T2H has two ADCs with 4 channels and one with 6.
> > > RZ/N2H has two ADCs with 4 channels and one with 15.
> > >
> > > Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > > ---
> > > .../iio/adc/renesas,r9a09g077-adc.yaml | 170 ++++++++++++++++++
> > > MAINTAINERS | 7 +
> > > 2 files changed, 177 insertions(+)
> > > create mode 100644
> > Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-
> > adc.yaml b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-
> > adc.yaml
> > > new file mode 100644
> > > index 000000000000..840108cd317e
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-
> > adc.yaml
> > > @@ -0,0 +1,170 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Renesas RZ/T2H / RZ/N2H ADC12
> > > +
> > > +maintainers:
> > > + - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > > +
> > > +description: |
> > > + A/D Converter block is a successive approximation analog-to-digital
> > converter
> > > + with a 12-bit accuracy. Up to 15 analog input channels can be
> > selected.
> > > + Conversions can be performed in single or continuous mode. Result of
> > the ADC
Your mail client is screwing up quoting somehow. Please fix it.
> > > + renesas,max-channels:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + description: |
> > > + Maximum number of channels supported by the ADC.
> > > + RZ/T2H has two ADCs with 4 channels and one with 6 channels.
> > > + RZ/N2H has two ADCs with 4 channels and one with 15 channels.
> >
> > What is the point of this? Why do you need to know how many channels
> > there can be in the driver, isn't it enough to just figure out how many
> > child nodes you have?
> >
>
> The idea here was that the SoC dtsi file would define the number of
> channels supported by each instance of the ADC peripheral, while the
> board dtsi (which includes the SoC dtsi) would define the number of
> channels actually wired up on the.
>
> Alternatively, we could have multiple compatibles for each SoC, like
> renesas,r9a09g077-adc-4, which would only have 4 channels, while
> the main renesas,r9a09g077-adc compatible would be the one with the
> most channels, 6.
>
> There might exist instances where knowing how many channels the chip
> has might be useful inside the driver, but the bindings themselves
> shouldn't really be addressing driver requirements, they should be
> describing the hardware properties.
"There might", so in other words: have written the driver and have not
had any need for this information. ;)
> The maximum number of supported channels of each ADC instance is a
> property of the hardware, which is fine to have in the bindings.
That is true, but also there's no interest in having properties that
you can obtain by other means - or don't need at all.
> Also, it is useful to know the maximum number of channels,
> otherwise, we would have to iterate over the iio_chan_spec
> populated by devm_iio_adc_device_alloc_chaninfo_se() to figure out
> what is the maximum used channel. We will surely need this
Right, you can get the information from another source. You only need to
do that exactly once, during probe, so whatever overhead that produces
isn't meaningful. I think this property should be removed.
> information when implementing buffered mode, to know up to which
> register to read data from, and we already need it when iterating
> over the enabled channels for the same reason.
>
> All things considered, I think it is useful to have this property
> here, considering the separation between SoC capabilities and board
> implementation.
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
2025-09-23 16:05 ` [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC Cosmin Tanislav
2025-09-23 18:41 ` Conor Dooley
@ 2025-09-24 7:51 ` Geert Uytterhoeven
2025-09-24 11:33 ` Cosmin-Gabriel Tanislav
1 sibling, 1 reply; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-09-24 7:51 UTC (permalink / raw)
To: Cosmin Tanislav
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
Hi Cosmin,
On Tue, 23 Sept 2025 at 18:06, Cosmin Tanislav
<cosmin-gabriel.tanislav.xa@renesas.com> wrote:
> Document the A/D 12-Bit successive approximation converters found in the
> Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
>
> RZ/T2H has two ADCs with 4 channels and one with 6.
> RZ/N2H has two ADCs with 4 channels and one with 15.
>
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> @@ -0,0 +1,170 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/adc/renesas,r9a09g077-adc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/T2H / RZ/N2H ADC12
> +
> +maintainers:
> + - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> +
> +description: |
> + A/D Converter block is a successive approximation analog-to-digital converter
> + with a 12-bit accuracy. Up to 15 analog input channels can be selected.
The documentation for several registers talks about bitmasks for ch0-ch15,
so the actual hardware block supports up to 16 channels.
> + Conversions can be performed in single or continuous mode. Result of the ADC
> + is stored in a 16-bit data register corresponding to each channel.
> +
> +properties:
> + compatible:
> + enum:
> + - renesas,r9a09g077-adc # RZ/T2H
> + - renesas,r9a09g087-adc # RZ/N2H
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + items:
> + - description: A/D scan end interrupt
> + - description: A/D scan end interrupt for Group B
> + - description: A/D scan end interrupt for Group C
> + - description: Window A compare match
> + - description: Window B compare match
> + - description: Compare match
> + - description: Compare mismatch
> +
> + interrupt-names:
> + items:
> + - const: adi
> + - const: gbadi
> + - const: gcadi
> + - const: cmpai
> + - const: cmpbi
> + - const: wcmpm
> + - const: wcmpum
> +
> + clocks:
> + items:
> + - description: converter clock
Converter
> + - description: peripheral clock
Peripheral
> +
> + clock-names:
> + items:
> + - const: adclk
> + - const: pclk
> +
> + power-domains:
> + maxItems: 1
> +
> + renesas,max-channels:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + Maximum number of channels supported by the ADC.
> + RZ/T2H has two ADCs with 4 channels and one with 6 channels.
> + RZ/N2H has two ADCs with 4 channels and one with 15 channels.
According to the documentation, both SoCs have three instances?
I agree with Connor that this should be dropped: the same information
is available from the channel@N subnodes, and future SoCs could have
gaps in the numbering.
FTR, from a quick glance, it looks like this module is very similar
to the ADC on RZ/A2M, so I hope we can reuse the driver for that SoC.
> +patternProperties:
> + "^channel@[0-9a-e]$":
0-9a-f
> + $ref: adc.yaml
> + type: object
> + description: The external channels which are connected to the ADC.
> +
> + properties:
> + reg:
> + description: The channel number.
> + maximum: 14
15
But I don't think it is needed, as the dtc check for non-matching unit
addresses and reg properties should already enforce this.
> +
> + required:
> + - reg
> +
> + additionalProperties: false
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: renesas,r9a09g077-adc
> + then:
> + properties:
> + renesas,max-channels:
> + enum: [4, 6]
> +
> + patternProperties:
> + "^channel@[6-9a-e]$": false
6-9a-f
> + "^channel@[0-5]$":
> + properties:
> + reg:
> + maximum: 5
Not needed as per above.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
2025-09-24 7:51 ` Geert Uytterhoeven
@ 2025-09-24 11:33 ` Cosmin-Gabriel Tanislav
2025-09-24 11:47 ` Geert Uytterhoeven
0 siblings, 1 reply; 17+ messages in thread
From: Cosmin-Gabriel Tanislav @ 2025-09-24 11:33 UTC (permalink / raw)
To: geert
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, Michael Turquette, Stephen Boyd,
Prabhakar Mahadev Lad, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Wednesday, September 24, 2025 10:51 AM
> To: Cosmin-Gabriel Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> Cc: Jonathan Cameron <jic23@kernel.org>; David Lechner <dlechner@baylibre.com>; Nuno Sá
> <nuno.sa@analog.com>; Andy Shevchenko <andy@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof
> Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; magnus.damm <magnus.damm@gmail.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; linux-iio@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org
> Subject: Re: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
>
> Hi Cosmin,
>
> On Tue, 23 Sept 2025 at 18:06, Cosmin Tanislav
> <cosmin-gabriel.tanislav.xa@renesas.com> wrote:
> > Document the A/D 12-Bit successive approximation converters found in the
> > Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
> >
> > RZ/T2H has two ADCs with 4 channels and one with 6.
> > RZ/N2H has two ADCs with 4 channels and one with 15.
> >
> > Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> > @@ -0,0 +1,170 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> http://devicetree.org/schemas/iio/adc%252
> Frenesas%2Cr9a09g077-adc.yaml%23&data=05%7C02%7Ccosmin-
> gabriel.tanislav.xa%40renesas.com%7C8c536bc422b9440a018708ddfb401335%7C53d82571da1947e49cb4625a166a4a2a
> %7C0%7C0%7C638942974801495945%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiO
> iJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=0zAY5VARxHP%2FN0wV7Gv1%2B9DZi%2Bg8JzBbi%
> 2BkzCDdN59M%3D&reserved=0
> > +$schema: http://devicetree.org/meta-
> schemas%2Fcore.yaml%23&data=05%7C02%7Ccosmin-
> gabriel.tanislav.xa%40renesas.com%7C8c536bc422b9440a018708ddfb401335%7C53d82571da1947e49cb4625a166a4a2a
> %7C0%7C0%7C638942974801538982%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiO
> iJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=VlYwNJVc7W%2BnLFKHf%2FG2Gk0HfWSsQ58cR0a8
> fQpckwE%3D&reserved=0
> > +
> > +title: Renesas RZ/T2H / RZ/N2H ADC12
> > +
> > +maintainers:
> > + - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > +
> > +description: |
> > + A/D Converter block is a successive approximation analog-to-digital converter
> > + with a 12-bit accuracy. Up to 15 analog input channels can be selected.
>
> The documentation for several registers talks about bitmasks for ch0-ch15,
> so the actual hardware block supports up to 16 channels.
>
Maybe the hardware block can support up to 16 channels, but on T2H,
which uses a 729-pin FCBGA pacakge, ADC2 only exposes 6 channels,
and on N2H, which uses a 576-pin FCBGA package, ADC2 only exposes 15
channels. On both of them, only 4 channels are exposed for ADC0 and
ADC1. As of this moment, this binding describes the ADC hardware blocks
of T2H and N2H, why would we use 16 here?
> > + Conversions can be performed in single or continuous mode. Result of the ADC
> > + is stored in a 16-bit data register corresponding to each channel.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - renesas,r9a09g077-adc # RZ/T2H
> > + - renesas,r9a09g087-adc # RZ/N2H
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + items:
> > + - description: A/D scan end interrupt
> > + - description: A/D scan end interrupt for Group B
> > + - description: A/D scan end interrupt for Group C
> > + - description: Window A compare match
> > + - description: Window B compare match
> > + - description: Compare match
> > + - description: Compare mismatch
> > +
> > + interrupt-names:
> > + items:
> > + - const: adi
> > + - const: gbadi
> > + - const: gcadi
> > + - const: cmpai
> > + - const: cmpbi
> > + - const: wcmpm
> > + - const: wcmpum
> > +
> > + clocks:
> > + items:
> > + - description: converter clock
>
> Converter
>
Ack.
> > + - description: peripheral clock
>
> Peripheral
>
Ack.
> > +
> > + clock-names:
> > + items:
> > + - const: adclk
> > + - const: pclk
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + renesas,max-channels:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: |
> > + Maximum number of channels supported by the ADC.
> > + RZ/T2H has two ADCs with 4 channels and one with 6 channels.
> > + RZ/N2H has two ADCs with 4 channels and one with 15 channels.
>
> According to the documentation, both SoCs have three instances?
>
Yes, both SoCs have three instances and (obviously) we've tested all
of them, as they're exposed on the evaluation board, as defined in
the dts patches in this series.
T2H: ADC0 - 4, ADC1 - 4, ADC2 - 6
N2H: ADC0 - 4, ADC1 - 4, ADC2 - 15
> I agree with Connor that this should be dropped: the same information
> is available from the channel@N subnodes, and future SoCs could have
> gaps in the numbering.
>
Ack.
> FTR, from a quick glance, it looks like this module is very similar
> to the ADC on RZ/A2M, so I hope we can reuse the driver for that SoC.
>
> > +patternProperties:
> > + "^channel@[0-9a-e]$":
>
> 0-9a-f
>
15 channels max for N2H, which is where 0-9a-e comes from. f is not valid.
Do you want to document 16 channels on the presumption that the hardware
block has 16 channels, even though only up to 15 are ever exposed out of
any SoC currently supported? This can be amended when/if we add support
for an SoC with 16 channels using the same ADC IP.
> > + $ref: adc.yaml
> > + type: object
> > + description: The external channels which are connected to the ADC.
> > +
> > + properties:
> > + reg:
> > + description: The channel number.
> > + maximum: 14
>
> 15
> But I don't think it is needed, as the dtc check for non-matching unit
> addresses and reg properties should already enforce this.
>
Other bindings have it like this. Is it not worth matching the address?
Can't ever have enough checks.
> > +
> > + required:
> > + - reg
> > +
> > + additionalProperties: false
> > +
> > +allOf:
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: renesas,r9a09g077-adc
> > + then:
> > + properties:
> > + renesas,max-channels:
> > + enum: [4, 6]
> > +
> > + patternProperties:
> > + "^channel@[6-9a-e]$": false
>
> 6-9a-f
>
Same as above.
> > + "^channel@[0-5]$":
> > + properties:
> > + reg:
> > + maximum: 5
>
> Not needed as per above.
>
Same as above.
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
________________________________
Renesas Electronics Europe GmbH
Registered Office: Arcadiastrasse 10
DE-40472 Duesseldorf
Commercial Registry: Duesseldorf, HRB 3708
Managing Director: Carsten Jauch
VAT-No.: DE 14978647
Tax-ID-No: 105/5839/1793
Legal Disclaimer: This e-mail communication (and any attachment/s) is confidential and contains proprietary information, some or all of which may be legally privileged. It is intended solely for the use of the individual or entity to which it is addressed. Access to this email by anyone else is unauthorized. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited and may be unlawful.
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC
2025-09-24 11:33 ` Cosmin-Gabriel Tanislav
@ 2025-09-24 11:47 ` Geert Uytterhoeven
0 siblings, 0 replies; 17+ messages in thread
From: Geert Uytterhoeven @ 2025-09-24 11:47 UTC (permalink / raw)
To: Cosmin-Gabriel Tanislav
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, Michael Turquette, Stephen Boyd,
Prabhakar Mahadev Lad, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Hi Cosmin,
On Wed, 24 Sept 2025 at 13:33, Cosmin-Gabriel Tanislav
<cosmin-gabriel.tanislav.xa@renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Tue, 23 Sept 2025 at 18:06, Cosmin Tanislav
> > <cosmin-gabriel.tanislav.xa@renesas.com> wrote:
> > > Document the A/D 12-Bit successive approximation converters found in the
> > > Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
> > >
> > > RZ/T2H has two ADCs with 4 channels and one with 6.
> > > RZ/N2H has two ADCs with 4 channels and one with 15.
> > >
> > > Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> > > @@ -0,0 +1,170 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > http://devicetree.org/schemas/iio/adc%252
> > Frenesas%2Cr9a09g077-adc.yaml%23&data=05%7C02%7Ccosmin-
> > gabriel.tanislav.xa%40renesas.com%7C8c536bc422b9440a018708ddfb401335%7C53d82571da1947e49cb4625a166a4a2a
> > %7C0%7C0%7C638942974801495945%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiO
> > iJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=0zAY5VARxHP%2FN0wV7Gv1%2B9DZi%2Bg8JzBbi%
> > 2BkzCDdN59M%3D&reserved=0
> > > +$schema: http://devicetree.org/meta-
> > schemas%2Fcore.yaml%23&data=05%7C02%7Ccosmin-
> > gabriel.tanislav.xa%40renesas.com%7C8c536bc422b9440a018708ddfb401335%7C53d82571da1947e49cb4625a166a4a2a
> > %7C0%7C0%7C638942974801538982%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiO
> > iJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=VlYwNJVc7W%2BnLFKHf%2FG2Gk0HfWSsQ58cR0a8
> > fQpckwE%3D&reserved=0
> > > +
> > > +title: Renesas RZ/T2H / RZ/N2H ADC12
> > > +
> > > +maintainers:
> > > + - Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > > +
> > > +description: |
> > > + A/D Converter block is a successive approximation analog-to-digital converter
> > > + with a 12-bit accuracy. Up to 15 analog input channels can be selected.
> >
> > The documentation for several registers talks about bitmasks for ch0-ch15,
> > so the actual hardware block supports up to 16 channels.
>
> Maybe the hardware block can support up to 16 channels, but on T2H,
> which uses a 729-pin FCBGA pacakge, ADC2 only exposes 6 channels,
> and on N2H, which uses a 576-pin FCBGA package, ADC2 only exposes 15
> channels. On both of them, only 4 channels are exposed for ADC0 and
> ADC1. As of this moment, this binding describes the ADC hardware blocks
> of T2H and N2H, why would we use 16 here?
Because the description at the top describes the hardware block,
not the restrictions in the integration in specific SoCs.
> > > + renesas,max-channels:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + description: |
> > > + Maximum number of channels supported by the ADC.
> > > + RZ/T2H has two ADCs with 4 channels and one with 6 channels.
> > > + RZ/N2H has two ADCs with 4 channels and one with 15 channels.
> >
> > According to the documentation, both SoCs have three instances?
>
> Yes, both SoCs have three instances and (obviously) we've tested all
> of them, as they're exposed on the evaluation board, as defined in
> the dts patches in this series.
My apologies, I misread.
> > > +patternProperties:
> > > + "^channel@[0-9a-e]$":
> >
> > 0-9a-f
> >
>
> 15 channels max for N2H, which is where 0-9a-e comes from. f is not valid.
> Do you want to document 16 channels on the presumption that the hardware
> block has 16 channels, even though only up to 15 are ever exposed out of
> any SoC currently supported?
Exactly...
> This can be amended when/if we add support
> for an SoC with 16 channels using the same ADC IP.
We can do that later, more churn...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 3/7] iio: adc: add RZ/T2H / RZ/N2H ADC driver
2025-09-23 16:05 [PATCH 0/7] Add ADCs support for RZ/T2H and RZ/N2H Cosmin Tanislav
2025-09-23 16:05 ` [PATCH 1/7] clk: renesas: r9a09g077: Add ADC modules clock Cosmin Tanislav
2025-09-23 16:05 ` [PATCH 2/7] dt-bindings: iio: adc: document RZ/T2H and RZ/N2H ADC Cosmin Tanislav
@ 2025-09-23 16:05 ` Cosmin Tanislav
2025-09-24 14:34 ` Nuno Sá
2025-09-23 16:05 ` [PATCH 4/7] arm64: dts: renesas: r9a09g077: Add ADCs support Cosmin Tanislav
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Cosmin Tanislav @ 2025-09-23 16:05 UTC (permalink / raw)
Cc: Cosmin Tanislav, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
Add support for the A/D 12-Bit successive approximation converters found
in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
RZ/T2H has two ADCs with 4 channels and one with 6.
RZ/N2H has two ADCs with 4 channels and one with 15.
Conversions can be performed in single or continuous mode. Result of the
conversion is stored in a 16-bit data register corresponding to each
channel.
The conversions can be started by a software trigger, a synchronous
trigger (from MTU or from ELC) or an asynchronous external trigger (from
ADTRGn# pin).
Only single mode with software trigger is supported for now.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
MAINTAINERS | 1 +
drivers/iio/adc/Kconfig | 10 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/rzt2h_adc.c | 328 ++++++++++++++++++++++++++++++++++++
4 files changed, 340 insertions(+)
create mode 100644 drivers/iio/adc/rzt2h_adc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 07e0d37cf468..d550399dc390 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21828,6 +21828,7 @@ L: linux-iio@vger.kernel.org
L: linux-renesas-soc@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
+F: drivers/iio/adc/rzt2h_adc.c
RENESAS RTCA-3 RTC DRIVER
M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 58a14e6833f6..cab5eeba48fe 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -1403,6 +1403,16 @@ config RZG2L_ADC
To compile this driver as a module, choose M here: the
module will be called rzg2l_adc.
+config RZT2H_ADC
+ tristate "Renesas RZ/T2H / RZ/N2H ADC driver"
+ select IIO_ADC_HELPER
+ help
+ Say yes here to build support for the ADC found in Renesas
+ RZ/T2H / RZ/N2H SoCs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called rzt2h_adc.
+
config SC27XX_ADC
tristate "Spreadtrum SC27xx series PMICs ADC"
depends on MFD_SC27XX_PMIC || COMPILE_TEST
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index d008f78dc010..ed647a734c51 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -123,6 +123,7 @@ obj-$(CONFIG_ROHM_BD79112) += rohm-bd79112.o
obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124.o
obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
+obj-$(CONFIG_RZT2H_ADC) += rzt2h_adc.o
obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o
obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
obj-$(CONFIG_SOPHGO_CV1800B_ADC) += sophgo-cv1800b-adc.o
diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c
new file mode 100644
index 000000000000..d855a79b3d96
--- /dev/null
+++ b/drivers/iio/adc/rzt2h_adc.c
@@ -0,0 +1,328 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/iio/adc-helpers.h>
+#include <linux/iio/iio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+
+#define RZT2H_NAME "rzt2h-adc"
+
+#define RZT2H_ADCSR_REG 0x00
+#define RZT2H_ADCSR_ADIE_MASK BIT(12)
+#define RZT2H_ADCSR_ADCS_MASK GENMASK(14, 13)
+#define RZT2H_ADCSR_ADCS_SINGLE 0b00
+#define RZT2H_ADCSR_ADST_MASK BIT(15)
+
+#define RZT2H_ADANSA0_REG 0x04
+#define RZT2H_ADANSA0_CH_MASK(x) BIT(x)
+
+#define RZT2H_ADDR_REG(x) (0x20 + 0x2 * (x))
+
+#define RZT2H_ADCALCTL_REG 0x1f0
+#define RZT2H_ADCALCTL_CAL_MASK BIT(0)
+#define RZT2H_ADCALCTL_CAL_RDY_MASK BIT(1)
+#define RZT2H_ADCALCTL_CAL_ERR_MASK BIT(2)
+
+#define RZT2H_ADC_MAX_CHANNELS 16
+#define RZT2H_ADC_VREF_MV 1800
+#define RZT2H_ADC_RESOLUTION 12
+
+struct rzt2h_adc {
+ void __iomem *base;
+ struct device *dev;
+
+ struct completion completion;
+ /* lock to protect against multiple access to the device */
+ struct mutex lock;
+
+ const struct iio_chan_spec *channels;
+ unsigned int num_channels;
+
+ u16 data[RZT2H_ADC_MAX_CHANNELS];
+};
+
+static void rzt2h_adc_start_stop(struct rzt2h_adc *adc, bool start,
+ unsigned int conversion_type)
+{
+ u16 mask;
+ u16 reg;
+
+ reg = readw(adc->base + RZT2H_ADCSR_REG);
+
+ if (start) {
+ /* Set conversion type */
+ reg &= ~RZT2H_ADCSR_ADCS_MASK;
+ reg |= FIELD_PREP(RZT2H_ADCSR_ADCS_MASK, conversion_type);
+ }
+
+ /* Toggle end of conversion interrupt and start bit. */
+ mask = RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK;
+ if (start)
+ reg |= mask;
+ else
+ reg &= ~mask;
+
+ writew(reg, adc->base + RZT2H_ADCSR_REG);
+}
+
+static void rzt2h_adc_start(struct rzt2h_adc *adc, unsigned int conversion_type)
+{
+ rzt2h_adc_start_stop(adc, true, conversion_type);
+}
+
+static void rzt2h_adc_stop(struct rzt2h_adc *adc)
+{
+ rzt2h_adc_start_stop(adc, false, 0);
+}
+
+static int rzt2h_adc_read_single(struct rzt2h_adc *adc, unsigned int ch, int *val)
+{
+ int ret;
+
+ ret = pm_runtime_resume_and_get(adc->dev);
+ if (ret)
+ return ret;
+
+ guard(mutex)(&adc->lock);
+
+ reinit_completion(&adc->completion);
+
+ /* Enable a single channel */
+ writew(RZT2H_ADANSA0_CH_MASK(ch), adc->base + RZT2H_ADANSA0_REG);
+
+ rzt2h_adc_start(adc, RZT2H_ADCSR_ADCS_SINGLE);
+
+ /*
+ * Datasheet Page 2770, Table 41.1:
+ * 0.32us per channel when sample-and-hold circuits are not in use.
+ */
+ ret = wait_for_completion_timeout(&adc->completion, usecs_to_jiffies(1));
+ if (!ret) {
+ ret = -ETIMEDOUT;
+ goto disable;
+ }
+
+ *val = adc->data[ch];
+ ret = IIO_VAL_INT;
+
+disable:
+ rzt2h_adc_stop(adc);
+
+ pm_runtime_put_autosuspend(adc->dev);
+
+ return ret;
+}
+
+static void rzt2h_adc_set_cal(struct rzt2h_adc *adc, bool cal)
+{
+ u16 val;
+
+ val = readw(adc->base + RZT2H_ADCALCTL_REG);
+ if (cal)
+ val |= RZT2H_ADCALCTL_CAL_MASK;
+ else
+ val &= ~RZT2H_ADCALCTL_CAL_MASK;
+
+ writew(val, adc->base + RZT2H_ADCALCTL_REG);
+}
+
+static int rzt2h_adc_calibrate(struct rzt2h_adc *adc)
+{
+ u16 val;
+ int ret;
+
+ rzt2h_adc_set_cal(adc, true);
+
+ ret = read_poll_timeout(readw, val, val & RZT2H_ADCALCTL_CAL_RDY_MASK,
+ 200, 1000, true, adc->base + RZT2H_ADCALCTL_REG);
+ if (ret) {
+ dev_err(adc->dev, "Calibration timed out: %d\n", ret);
+ return ret;
+ }
+
+ if (val & RZT2H_ADCALCTL_CAL_ERR_MASK) {
+ dev_err(adc->dev, "Calibration failed\n");
+ return -EINVAL;
+ }
+
+ rzt2h_adc_set_cal(adc, false);
+
+ return 0;
+}
+
+static int rzt2h_adc_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ struct rzt2h_adc *adc = iio_priv(indio_dev);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ return rzt2h_adc_read_single(adc, chan->channel, val);
+ case IIO_CHAN_INFO_SCALE:
+ *val = RZT2H_ADC_VREF_MV;
+ *val2 = RZT2H_ADC_RESOLUTION;
+ return IIO_VAL_FRACTIONAL_LOG2;
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct iio_info rzt2h_adc_iio_info = {
+ .read_raw = rzt2h_adc_read_raw,
+};
+
+static irqreturn_t rzt2h_adc_isr(int irq, void *private)
+{
+ struct rzt2h_adc *adc = private;
+ unsigned long enabled_channels;
+ unsigned int ch;
+
+ enabled_channels = readw(adc->base + RZT2H_ADANSA0_REG);
+ if (!enabled_channels)
+ return IRQ_NONE;
+
+ for_each_set_bit(ch, &enabled_channels, adc->num_channels)
+ adc->data[ch] = readw(adc->base + RZT2H_ADDR_REG(ch));
+
+ complete(&adc->completion);
+
+ return IRQ_HANDLED;
+}
+
+static const struct iio_chan_spec rzt2h_adc_chan_template = {
+ .indexed = 1,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+ BIT(IIO_CHAN_INFO_SCALE),
+ .type = IIO_VOLTAGE,
+};
+
+static int rzt2h_adc_parse_properties(struct rzt2h_adc *adc)
+{
+ struct iio_chan_spec *chan_array;
+ u32 max_channels;
+ int ret;
+
+ ret = device_property_read_u32(adc->dev, "renesas,max-channels",
+ &max_channels);
+ if (ret)
+ return dev_err_probe(adc->dev, ret,
+ "Failed to find max-channels property");
+
+ ret = devm_iio_adc_device_alloc_chaninfo_se(adc->dev,
+ &rzt2h_adc_chan_template,
+ max_channels - 1,
+ &chan_array);
+ if (ret < 0)
+ return dev_err_probe(adc->dev, ret, "Failed to read channel info");
+
+ adc->num_channels = ret;
+ adc->channels = chan_array;
+
+ return 0;
+}
+
+static int rzt2h_adc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iio_dev *indio_dev;
+ struct rzt2h_adc *adc;
+ int ret;
+ int irq;
+
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ adc = iio_priv(indio_dev);
+ adc->dev = dev;
+ init_completion(&adc->completion);
+
+ ret = devm_mutex_init(dev, &adc->lock);
+ if (ret)
+ return ret;
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ ret = rzt2h_adc_parse_properties(adc);
+ if (ret)
+ return ret;
+
+ adc->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(adc->base))
+ return PTR_ERR(adc->base);
+
+ pm_runtime_set_autosuspend_delay(dev, 300);
+ pm_runtime_use_autosuspend(dev);
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ irq = platform_get_irq_byname(pdev, "adi");
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_irq(dev, irq, rzt2h_adc_isr, 0, dev_name(dev), adc);
+ if (ret)
+ return ret;
+
+ indio_dev->name = RZT2H_NAME;
+ indio_dev->info = &rzt2h_adc_iio_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = adc->channels;
+ indio_dev->num_channels = adc->num_channels;
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static const struct of_device_id rzt2h_adc_match[] = {
+ { .compatible = "renesas,r9a09g077-adc" },
+ { .compatible = "renesas,r9a09g087-adc" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, rzt2h_adc_match);
+
+static int rzt2h_adc_pm_runtime_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct rzt2h_adc *adc = iio_priv(indio_dev);
+
+ /*
+ * Datasheet Page 2810, Section 41.5.6:
+ * After release from the module-stop state, wait for at least
+ * 0.5 µs before starting A/D conversion.
+ */
+ fsleep(1);
+
+ return rzt2h_adc_calibrate(adc);
+}
+
+static const struct dev_pm_ops rzt2h_adc_pm_ops = {
+ RUNTIME_PM_OPS(NULL, rzt2h_adc_pm_runtime_resume, NULL)
+};
+
+static struct platform_driver rzt2h_adc_driver = {
+ .probe = rzt2h_adc_probe,
+ .driver = {
+ .name = RZT2H_NAME,
+ .of_match_table = rzt2h_adc_match,
+ .pm = pm_ptr(&rzt2h_adc_pm_ops),
+ },
+};
+
+module_platform_driver(rzt2h_adc_driver);
+
+MODULE_AUTHOR("Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/T2H / RZ/N2H ADC driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("IIO_DRIVER");
--
2.51.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/7] iio: adc: add RZ/T2H / RZ/N2H ADC driver
2025-09-23 16:05 ` [PATCH 3/7] iio: adc: add RZ/T2H / RZ/N2H ADC driver Cosmin Tanislav
@ 2025-09-24 14:34 ` Nuno Sá
2025-09-24 16:38 ` Cosmin-Gabriel Tanislav
0 siblings, 1 reply; 17+ messages in thread
From: Nuno Sá @ 2025-09-24 14:34 UTC (permalink / raw)
To: Cosmin Tanislav
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
Hi Cosmin,
Some comments/questions from me...
On Tue, 2025-09-23 at 19:05 +0300, Cosmin Tanislav wrote:
> Add support for the A/D 12-Bit successive approximation converters found
> in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
>
> RZ/T2H has two ADCs with 4 channels and one with 6.
> RZ/N2H has two ADCs with 4 channels and one with 15.
>
> Conversions can be performed in single or continuous mode. Result of the
> conversion is stored in a 16-bit data register corresponding to each
> channel.
>
> The conversions can be started by a software trigger, a synchronous
> trigger (from MTU or from ELC) or an asynchronous external trigger (from
> ADTRGn# pin).
>
> Only single mode with software trigger is supported for now.
>
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> ---
> MAINTAINERS | 1 +
> drivers/iio/adc/Kconfig | 10 ++
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/rzt2h_adc.c | 328 ++++++++++++++++++++++++++++++++++++
> 4 files changed, 340 insertions(+)
> create mode 100644 drivers/iio/adc/rzt2h_adc.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 07e0d37cf468..d550399dc390 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21828,6 +21828,7 @@ L: linux-iio@vger.kernel.org
> L: linux-renesas-soc@vger.kernel.org
> S: Supported
> F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> +F: drivers/iio/adc/rzt2h_adc.c
>
> RENESAS RTCA-3 RTC DRIVER
> M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 58a14e6833f6..cab5eeba48fe 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -1403,6 +1403,16 @@ config RZG2L_ADC
> To compile this driver as a module, choose M here: the
> module will be called rzg2l_adc.
>
> +config RZT2H_ADC
> + tristate "Renesas RZ/T2H / RZ/N2H ADC driver"
> + select IIO_ADC_HELPER
> + help
> + Say yes here to build support for the ADC found in Renesas
> + RZ/T2H / RZ/N2H SoCs.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rzt2h_adc.
> +
> config SC27XX_ADC
> tristate "Spreadtrum SC27xx series PMICs ADC"
> depends on MFD_SC27XX_PMIC || COMPILE_TEST
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index d008f78dc010..ed647a734c51 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -123,6 +123,7 @@ obj-$(CONFIG_ROHM_BD79112) += rohm-bd79112.o
> obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124.o
> obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
> obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
> +obj-$(CONFIG_RZT2H_ADC) += rzt2h_adc.o
> obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o
> obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
> obj-$(CONFIG_SOPHGO_CV1800B_ADC) += sophgo-cv1800b-adc.o
> diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c
> new file mode 100644
> index 000000000000..d855a79b3d96
> --- /dev/null
> +++ b/drivers/iio/adc/rzt2h_adc.c
> @@ -0,0 +1,328 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <linux/bitfield.h>
> +#include <linux/cleanup.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/iio/adc-helpers.h>
> +#include <linux/iio/iio.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/property.h>
> +
> +#define RZT2H_NAME "rzt2h-adc"
> +
> +#define RZT2H_ADCSR_REG 0x00
> +#define RZT2H_ADCSR_ADIE_MASK BIT(12)
> +#define RZT2H_ADCSR_ADCS_MASK GENMASK(14, 13)
> +#define RZT2H_ADCSR_ADCS_SINGLE 0b00
> +#define RZT2H_ADCSR_ADST_MASK BIT(15)
> +
> +#define RZT2H_ADANSA0_REG 0x04
> +#define RZT2H_ADANSA0_CH_MASK(x) BIT(x)
> +
> +#define RZT2H_ADDR_REG(x) (0x20 + 0x2 * (x))
> +
> +#define RZT2H_ADCALCTL_REG 0x1f0
> +#define RZT2H_ADCALCTL_CAL_MASK BIT(0)
> +#define RZT2H_ADCALCTL_CAL_RDY_MASK BIT(1)
> +#define RZT2H_ADCALCTL_CAL_ERR_MASK BIT(2)
> +
> +#define RZT2H_ADC_MAX_CHANNELS 16
> +#define RZT2H_ADC_VREF_MV 1800
> +#define RZT2H_ADC_RESOLUTION 12
> +
> +struct rzt2h_adc {
> + void __iomem *base;
> + struct device *dev;
> +
> + struct completion completion;
> + /* lock to protect against multiple access to the device */
> + struct mutex lock;
> +
> + const struct iio_chan_spec *channels;
> + unsigned int num_channels;
> +
> + u16 data[RZT2H_ADC_MAX_CHANNELS];
> +};
> +
> +static void rzt2h_adc_start_stop(struct rzt2h_adc *adc, bool start,
> + unsigned int conversion_type)
> +{
> + u16 mask;
> + u16 reg;
> +
> + reg = readw(adc->base + RZT2H_ADCSR_REG);
> +
> + if (start) {
> + /* Set conversion type */
> + reg &= ~RZT2H_ADCSR_ADCS_MASK;
> + reg |= FIELD_PREP(RZT2H_ADCSR_ADCS_MASK, conversion_type);
> + }
> +
> + /* Toggle end of conversion interrupt and start bit. */
> + mask = RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK;
> + if (start)
> + reg |= mask;
> + else
> + reg &= ~mask;
> +
> + writew(reg, adc->base + RZT2H_ADCSR_REG);
> +}
> +
> +static void rzt2h_adc_start(struct rzt2h_adc *adc, unsigned int
> conversion_type)
> +{
> + rzt2h_adc_start_stop(adc, true, conversion_type);
> +}
> +
> +static void rzt2h_adc_stop(struct rzt2h_adc *adc)
> +{
> + rzt2h_adc_start_stop(adc, false, 0);
> +}
> +
I'm not 100% convince the above two helpers add much value given the usage they
have. I do understand that they make things a bit more readable but still...
rzt2h_adc_start_stop(adc, false/true, ...) is already fairly clear about it's
happening. Dont't feel strong about it anyways so up to you.
> +static int rzt2h_adc_read_single(struct rzt2h_adc *adc, unsigned int ch, int
> *val)
> +{
> + int ret;
> +
> + ret = pm_runtime_resume_and_get(adc->dev);
> + if (ret)
> + return ret;
> +
> + guard(mutex)(&adc->lock);
> +
> + reinit_completion(&adc->completion);
> +
> + /* Enable a single channel */
> + writew(RZT2H_ADANSA0_CH_MASK(ch), adc->base + RZT2H_ADANSA0_REG);
> +
> + rzt2h_adc_start(adc, RZT2H_ADCSR_ADCS_SINGLE);
This is the only place where this is called. So we could just pass
RZT2H_ADCSR_ADCS_SINGLE inside the function. Unless this will be extended in the
near future?
> +
> + /*
> + * Datasheet Page 2770, Table 41.1:
> + * 0.32us per channel when sample-and-hold circuits are not in use.
> + */
> + ret = wait_for_completion_timeout(&adc->completion,
> usecs_to_jiffies(1));
> + if (!ret) {
> + ret = -ETIMEDOUT;
> + goto disable;
> + }
> +
> + *val = adc->data[ch];
> + ret = IIO_VAL_INT;
> +
> +disable:
> + rzt2h_adc_stop(adc);
> +
> + pm_runtime_put_autosuspend(adc->dev);
> +
> + return ret;
> +}
> +
> +static void rzt2h_adc_set_cal(struct rzt2h_adc *adc, bool cal)
> +{
> + u16 val;
> +
> + val = readw(adc->base + RZT2H_ADCALCTL_REG);
> + if (cal)
> + val |= RZT2H_ADCALCTL_CAL_MASK;
> + else
> + val &= ~RZT2H_ADCALCTL_CAL_MASK;
> +
> + writew(val, adc->base + RZT2H_ADCALCTL_REG);
> +}
> +
> +static int rzt2h_adc_calibrate(struct rzt2h_adc *adc)
> +{
> + u16 val;
> + int ret;
> +
> + rzt2h_adc_set_cal(adc, true);
> +
> + ret = read_poll_timeout(readw, val, val &
> RZT2H_ADCALCTL_CAL_RDY_MASK,
> + 200, 1000, true, adc->base +
> RZT2H_ADCALCTL_REG);
> + if (ret) {
> + dev_err(adc->dev, "Calibration timed out: %d\n", ret);
> + return ret;
> + }
> +
> + if (val & RZT2H_ADCALCTL_CAL_ERR_MASK) {
> + dev_err(adc->dev, "Calibration failed\n");
> + return -EINVAL;
> + }
> +
> + rzt2h_adc_set_cal(adc, false);
Should we disable calibrations in the error path (or right after
read_poll_timeout()) or it does not really matter?
> +
> + return 0;
> +}
> +
> +static int rzt2h_adc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + struct rzt2h_adc *adc = iio_priv(indio_dev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + return rzt2h_adc_read_single(adc, chan->channel, val);
> + case IIO_CHAN_INFO_SCALE:
> + *val = RZT2H_ADC_VREF_MV;
> + *val2 = RZT2H_ADC_RESOLUTION;
> + return IIO_VAL_FRACTIONAL_LOG2;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct iio_info rzt2h_adc_iio_info = {
> + .read_raw = rzt2h_adc_read_raw,
> +};
> +
> +static irqreturn_t rzt2h_adc_isr(int irq, void *private)
> +{
> + struct rzt2h_adc *adc = private;
> + unsigned long enabled_channels;
> + unsigned int ch;
> +
> + enabled_channels = readw(adc->base + RZT2H_ADANSA0_REG);
> + if (!enabled_channels)
> + return IRQ_NONE;
Is the above possible at all? In rzt2h_adc_read_single() we do write the same
register...
> +
> + for_each_set_bit(ch, &enabled_channels, adc->num_channels)
> + adc->data[ch] = readw(adc->base + RZT2H_ADDR_REG(ch));
> +
Is there any particular reason for reading all enabled channels in the IRQ when
we kind of just care for one channel? If there's nothing non obvious happening
It seems that the IRQ could just do complete(...) and reading the result in
rzt2h_adc_read_single()
- Nuno Sá
^ permalink raw reply [flat|nested] 17+ messages in thread* RE: [PATCH 3/7] iio: adc: add RZ/T2H / RZ/N2H ADC driver
2025-09-24 14:34 ` Nuno Sá
@ 2025-09-24 16:38 ` Cosmin-Gabriel Tanislav
0 siblings, 0 replies; 17+ messages in thread
From: Cosmin-Gabriel Tanislav @ 2025-09-24 16:38 UTC (permalink / raw)
To: Nuno Sá
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, magnus.damm, Michael Turquette, Stephen Boyd,
Prabhakar Mahadev Lad, linux-iio@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
> -----Original Message-----
> From: Nuno Sá <noname.nuno@gmail.com>
> Sent: Wednesday, September 24, 2025 5:35 PM
> To: Cosmin-Gabriel Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> Cc: Jonathan Cameron <jic23@kernel.org>; David Lechner <dlechner@baylibre.com>; Nuno Sá
> <nuno.sa@analog.com>; Andy Shevchenko <andy@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof
> Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Geert Uytterhoeven
> <geert+renesas@glider.be>; magnus.damm <magnus.damm@gmail.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; linux-iio@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-clk@vger.kernel.org
> Subject: Re: [PATCH 3/7] iio: adc: add RZ/T2H / RZ/N2H ADC driver
>
> Hi Cosmin,
>
> Some comments/questions from me...
>
> On Tue, 2025-09-23 at 19:05 +0300, Cosmin Tanislav wrote:
> > Add support for the A/D 12-Bit successive approximation converters found
> > in the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs.
> >
> > RZ/T2H has two ADCs with 4 channels and one with 6.
> > RZ/N2H has two ADCs with 4 channels and one with 15.
> >
> > Conversions can be performed in single or continuous mode. Result of the
> > conversion is stored in a 16-bit data register corresponding to each
> > channel.
> >
> > The conversions can be started by a software trigger, a synchronous
> > trigger (from MTU or from ELC) or an asynchronous external trigger (from
> > ADTRGn# pin).
> >
> > Only single mode with software trigger is supported for now.
> >
> > Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> > ---
> > MAINTAINERS | 1 +
> > drivers/iio/adc/Kconfig | 10 ++
> > drivers/iio/adc/Makefile | 1 +
> > drivers/iio/adc/rzt2h_adc.c | 328 ++++++++++++++++++++++++++++++++++++
> > 4 files changed, 340 insertions(+)
> > create mode 100644 drivers/iio/adc/rzt2h_adc.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 07e0d37cf468..d550399dc390 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -21828,6 +21828,7 @@ L: linux-iio@vger.kernel.org
> > L: linux-renesas-soc@vger.kernel.org
> > S: Supported
> > F: Documentation/devicetree/bindings/iio/adc/renesas,r9a09g077-adc.yaml
> > +F: drivers/iio/adc/rzt2h_adc.c
> >
> > RENESAS RTCA-3 RTC DRIVER
> > M: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> > index 58a14e6833f6..cab5eeba48fe 100644
> > --- a/drivers/iio/adc/Kconfig
> > +++ b/drivers/iio/adc/Kconfig
> > @@ -1403,6 +1403,16 @@ config RZG2L_ADC
> > To compile this driver as a module, choose M here: the
> > module will be called rzg2l_adc.
> >
> > +config RZT2H_ADC
> > + tristate "Renesas RZ/T2H / RZ/N2H ADC driver"
> > + select IIO_ADC_HELPER
> > + help
> > + Say yes here to build support for the ADC found in Renesas
> > + RZ/T2H / RZ/N2H SoCs.
> > +
> > + To compile this driver as a module, choose M here: the
> > + module will be called rzt2h_adc.
> > +
> > config SC27XX_ADC
> > tristate "Spreadtrum SC27xx series PMICs ADC"
> > depends on MFD_SC27XX_PMIC || COMPILE_TEST
> > diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> > index d008f78dc010..ed647a734c51 100644
> > --- a/drivers/iio/adc/Makefile
> > +++ b/drivers/iio/adc/Makefile
> > @@ -123,6 +123,7 @@ obj-$(CONFIG_ROHM_BD79112) += rohm-bd79112.o
> > obj-$(CONFIG_ROHM_BD79124) += rohm-bd79124.o
> > obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
> > obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
> > +obj-$(CONFIG_RZT2H_ADC) += rzt2h_adc.o
> > obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o
> > obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o
> > obj-$(CONFIG_SOPHGO_CV1800B_ADC) += sophgo-cv1800b-adc.o
> > diff --git a/drivers/iio/adc/rzt2h_adc.c b/drivers/iio/adc/rzt2h_adc.c
> > new file mode 100644
> > index 000000000000..d855a79b3d96
> > --- /dev/null
> > +++ b/drivers/iio/adc/rzt2h_adc.c
> > @@ -0,0 +1,328 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/cleanup.h>
> > +#include <linux/completion.h>
> > +#include <linux/delay.h>
> > +#include <linux/iio/adc-helpers.h>
> > +#include <linux/iio/iio.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/io.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/property.h>
> > +
> > +#define RZT2H_NAME "rzt2h-adc"
> > +
> > +#define RZT2H_ADCSR_REG 0x00
> > +#define RZT2H_ADCSR_ADIE_MASK BIT(12)
> > +#define RZT2H_ADCSR_ADCS_MASK GENMASK(14, 13)
> > +#define RZT2H_ADCSR_ADCS_SINGLE 0b00
> > +#define RZT2H_ADCSR_ADST_MASK BIT(15)
> > +
> > +#define RZT2H_ADANSA0_REG 0x04
> > +#define RZT2H_ADANSA0_CH_MASK(x) BIT(x)
> > +
> > +#define RZT2H_ADDR_REG(x) (0x20 + 0x2 * (x))
> > +
> > +#define RZT2H_ADCALCTL_REG 0x1f0
> > +#define RZT2H_ADCALCTL_CAL_MASK BIT(0)
> > +#define RZT2H_ADCALCTL_CAL_RDY_MASK BIT(1)
> > +#define RZT2H_ADCALCTL_CAL_ERR_MASK BIT(2)
> > +
> > +#define RZT2H_ADC_MAX_CHANNELS 16
> > +#define RZT2H_ADC_VREF_MV 1800
> > +#define RZT2H_ADC_RESOLUTION 12
> > +
> > +struct rzt2h_adc {
> > + void __iomem *base;
> > + struct device *dev;
> > +
> > + struct completion completion;
> > + /* lock to protect against multiple access to the device */
> > + struct mutex lock;
> > +
> > + const struct iio_chan_spec *channels;
> > + unsigned int num_channels;
> > +
> > + u16 data[RZT2H_ADC_MAX_CHANNELS];
> > +};
> > +
> > +static void rzt2h_adc_start_stop(struct rzt2h_adc *adc, bool start,
> > + unsigned int conversion_type)
> > +{
> > + u16 mask;
> > + u16 reg;
> > +
> > + reg = readw(adc->base + RZT2H_ADCSR_REG);
> > +
> > + if (start) {
> > + /* Set conversion type */
> > + reg &= ~RZT2H_ADCSR_ADCS_MASK;
> > + reg |= FIELD_PREP(RZT2H_ADCSR_ADCS_MASK, conversion_type);
> > + }
> > +
> > + /* Toggle end of conversion interrupt and start bit. */
> > + mask = RZT2H_ADCSR_ADIE_MASK | RZT2H_ADCSR_ADST_MASK;
> > + if (start)
> > + reg |= mask;
> > + else
> > + reg &= ~mask;
> > +
> > + writew(reg, adc->base + RZT2H_ADCSR_REG);
> > +}
> > +
> > +static void rzt2h_adc_start(struct rzt2h_adc *adc, unsigned int
> > conversion_type)
> > +{
> > + rzt2h_adc_start_stop(adc, true, conversion_type);
> > +}
> > +
> > +static void rzt2h_adc_stop(struct rzt2h_adc *adc)
> > +{
> > + rzt2h_adc_start_stop(adc, false, 0);
> > +}
> > +
>
> I'm not 100% convince the above two helpers add much value given the usage they
> have. I do understand that they make things a bit more readable but still...
>
> rzt2h_adc_start_stop(adc, false/true, ...) is already fairly clear about it's
> happening. Dont't feel strong about it anyways so up to you.
>
Agree. I will inline the contents of rzt2h_adc_start()/rzt2h_adc_stop().
> > +static int rzt2h_adc_read_single(struct rzt2h_adc *adc, unsigned int ch, int
> > *val)
> > +{
> > + int ret;
> > +
> > + ret = pm_runtime_resume_and_get(adc->dev);
> > + if (ret)
> > + return ret;
> > +
> > + guard(mutex)(&adc->lock);
> > +
> > + reinit_completion(&adc->completion);
> > +
> > + /* Enable a single channel */
> > + writew(RZT2H_ADANSA0_CH_MASK(ch), adc->base + RZT2H_ADANSA0_REG);
> > +
> > + rzt2h_adc_start(adc, RZT2H_ADCSR_ADCS_SINGLE);
>
> This is the only place where this is called. So we could just pass
> RZT2H_ADCSR_ADCS_SINGLE inside the function. Unless this will be extended in the
> near future?
>
We do plan on adding continuous mode support eventually.
> > +
> > + /*
> > + * Datasheet Page 2770, Table 41.1:
> > + * 0.32us per channel when sample-and-hold circuits are not in use.
> > + */
> > + ret = wait_for_completion_timeout(&adc->completion,
> > usecs_to_jiffies(1));
> > + if (!ret) {
> > + ret = -ETIMEDOUT;
> > + goto disable;
> > + }
> > +
> > + *val = adc->data[ch];
> > + ret = IIO_VAL_INT;
> > +
> > +disable:
> > + rzt2h_adc_stop(adc);
> > +
> > + pm_runtime_put_autosuspend(adc->dev);
> > +
> > + return ret;
> > +}
> > +
> > +static void rzt2h_adc_set_cal(struct rzt2h_adc *adc, bool cal)
> > +{
> > + u16 val;
> > +
> > + val = readw(adc->base + RZT2H_ADCALCTL_REG);
> > + if (cal)
> > + val |= RZT2H_ADCALCTL_CAL_MASK;
> > + else
> > + val &= ~RZT2H_ADCALCTL_CAL_MASK;
> > +
> > + writew(val, adc->base + RZT2H_ADCALCTL_REG);
> > +}
> > +
> > +static int rzt2h_adc_calibrate(struct rzt2h_adc *adc)
> > +{
> > + u16 val;
> > + int ret;
> > +
> > + rzt2h_adc_set_cal(adc, true);
> > +
> > + ret = read_poll_timeout(readw, val, val &
> > RZT2H_ADCALCTL_CAL_RDY_MASK,
> > + 200, 1000, true, adc->base +
> > RZT2H_ADCALCTL_REG);
> > + if (ret) {
> > + dev_err(adc->dev, "Calibration timed out: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + if (val & RZT2H_ADCALCTL_CAL_ERR_MASK) {
> > + dev_err(adc->dev, "Calibration failed\n");
> > + return -EINVAL;
> > + }
> > +
> > + rzt2h_adc_set_cal(adc, false);
>
> Should we disable calibrations in the error path (or right after
> read_poll_timeout()) or it does not really matter?
>
Yes, we should. I'll do that for the next version.
> > +
> > + return 0;
> > +}
> > +
> > +static int rzt2h_adc_read_raw(struct iio_dev *indio_dev,
> > + struct iio_chan_spec const *chan,
> > + int *val, int *val2, long mask)
> > +{
> > + struct rzt2h_adc *adc = iio_priv(indio_dev);
> > +
> > + switch (mask) {
> > + case IIO_CHAN_INFO_RAW:
> > + return rzt2h_adc_read_single(adc, chan->channel, val);
> > + case IIO_CHAN_INFO_SCALE:
> > + *val = RZT2H_ADC_VREF_MV;
> > + *val2 = RZT2H_ADC_RESOLUTION;
> > + return IIO_VAL_FRACTIONAL_LOG2;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +static const struct iio_info rzt2h_adc_iio_info = {
> > + .read_raw = rzt2h_adc_read_raw,
> > +};
> > +
> > +static irqreturn_t rzt2h_adc_isr(int irq, void *private)
> > +{
> > + struct rzt2h_adc *adc = private;
> > + unsigned long enabled_channels;
> > + unsigned int ch;
> > +
> > + enabled_channels = readw(adc->base + RZT2H_ADANSA0_REG);
> > + if (!enabled_channels)
> > + return IRQ_NONE;
>
> Is the above possible at all? In rzt2h_adc_read_single() we do write the same
> register...
>
No, it shouldn't happen normally.
> > +
> > + for_each_set_bit(ch, &enabled_channels, adc->num_channels)
> > + adc->data[ch] = readw(adc->base + RZT2H_ADDR_REG(ch));
> > +
>
> Is there any particular reason for reading all enabled channels in the IRQ when
> we kind of just care for one channel? If there's nothing non obvious happening
> It seems that the IRQ could just do complete(...) and reading the result in
> rzt2h_adc_read_single()
>
For single conversion mode, no, since we can't have multiple enabled
channels. And for continuous conversion we would be using triggers, and
data reading will be in the trigger handler, so I think it is safe to
move the data reading into rzt2h_adc_read_single().
Will do that for next version.
> - Nuno Sá
________________________________
Renesas Electronics Europe GmbH
Registered Office: Arcadiastrasse 10
DE-40472 Duesseldorf
Commercial Registry: Duesseldorf, HRB 3708
Managing Director: Carsten Jauch
VAT-No.: DE 14978647
Tax-ID-No: 105/5839/1793
Legal Disclaimer: This e-mail communication (and any attachment/s) is confidential and contains proprietary information, some or all of which may be legally privileged. It is intended solely for the use of the individual or entity to which it is addressed. Access to this email by anyone else is unauthorized. If you are not the intended recipient, any disclosure, copying, distribution or any action taken or omitted to be taken in reliance on it, is prohibited and may be unlawful.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/7] arm64: dts: renesas: r9a09g077: Add ADCs support
2025-09-23 16:05 [PATCH 0/7] Add ADCs support for RZ/T2H and RZ/N2H Cosmin Tanislav
` (2 preceding siblings ...)
2025-09-23 16:05 ` [PATCH 3/7] iio: adc: add RZ/T2H / RZ/N2H ADC driver Cosmin Tanislav
@ 2025-09-23 16:05 ` Cosmin Tanislav
2025-09-23 16:05 ` [PATCH 5/7] arm64: dts: renesas: r9a09g087: " Cosmin Tanislav
` (2 subsequent siblings)
6 siblings, 0 replies; 17+ messages in thread
From: Cosmin Tanislav @ 2025-09-23 16:05 UTC (permalink / raw)
Cc: Cosmin Tanislav, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
Renesas RZ/T2H (R9A09G077) includes three 12-Bit successive
approximation A/D converters, two 4-channel ADCs, and one 6-channel ADC.
Add support for all of them.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
index 37a696d8ec6d..bfb317d7066c 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
@@ -666,6 +666,75 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ adc0: adc@90014000 {
+ compatible = "renesas,r9a09g077-adc";
+ reg = <0 0x90014000 0 0x400>;
+ interrupts = <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 852 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adi", "gbadi", "gcadi",
+ "cmpai", "cmpbi", "wcmpm", "wcmpum";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
+ <&cpg CPG_MOD 206>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ renesas,max-channels = <4>;
+ status = "disabled";
+ };
+
+ adc1: adc@90014400 {
+ compatible = "renesas,r9a09g077-adc";
+ reg = <0 0x90014400 0 0x400>;
+ interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 704 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 705 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 854 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adi", "gbadi", "gcadi",
+ "cmpai", "cmpbi", "wcmpm", "wcmpum";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
+ <&cpg CPG_MOD 207>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ renesas,max-channels = <4>;
+ status = "disabled";
+ };
+
+ adc2: adc@80008000 {
+ compatible = "renesas,r9a09g077-adc";
+ reg = <0 0x80008000 0 0x400>;
+ interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adi", "gbadi", "gcadi",
+ "cmpai", "cmpbi", "wcmpm", "wcmpum";
+ clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>,
+ <&cpg CPG_MOD 225>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ renesas,max-channels = <6>;
+ status = "disabled";
+ };
+
ohci: usb@92040000 {
compatible = "generic-ohci";
reg = <0 0x92040000 0 0x100>;
--
2.51.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 5/7] arm64: dts: renesas: r9a09g087: Add ADCs support
2025-09-23 16:05 [PATCH 0/7] Add ADCs support for RZ/T2H and RZ/N2H Cosmin Tanislav
` (3 preceding siblings ...)
2025-09-23 16:05 ` [PATCH 4/7] arm64: dts: renesas: r9a09g077: Add ADCs support Cosmin Tanislav
@ 2025-09-23 16:05 ` Cosmin Tanislav
2025-09-23 16:05 ` [PATCH 6/7] arm64: dts: renesas: rzt2h/rzn2h-evk: enable ADCs Cosmin Tanislav
2025-09-23 16:05 ` [PATCH 7/7] arm64: defconfig: enable RZ/T2H / RZ/N2H ADC driver Cosmin Tanislav
6 siblings, 0 replies; 17+ messages in thread
From: Cosmin Tanislav @ 2025-09-23 16:05 UTC (permalink / raw)
Cc: Cosmin Tanislav, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
Renesas RZ/T2H (R9A09G087) includes three 12-Bit successive
approximation A/D converters, two 4-channel ADCs, and one 15-channel
ADC.
Add support for all of them.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g087.dtsi | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
index 88669868f0ee..faca2fd47257 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g087.dtsi
@@ -666,6 +666,75 @@ gic: interrupt-controller@83000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ adc0: adc@90014000 {
+ compatible = "renesas,r9a09g087-adc";
+ reg = <0 0x90014000 0 0x400>;
+ interrupts = <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 699 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 700 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 852 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adi", "gbadi", "gcadi",
+ "cmpai", "cmpbi", "wcmpm", "wcmpum";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
+ <&cpg CPG_MOD 206>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ renesas,max-channels = <4>;
+ status = "disabled";
+ };
+
+ adc1: adc@90014400 {
+ compatible = "renesas,r9a09g087-adc";
+ reg = <0 0x90014400 0 0x400>;
+ interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 704 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 705 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 854 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adi", "gbadi", "gcadi",
+ "cmpai", "cmpbi", "wcmpm", "wcmpum";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
+ <&cpg CPG_MOD 207>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ renesas,max-channels = <4>;
+ status = "disabled";
+ };
+
+ adc2: adc@80008000 {
+ compatible = "renesas,r9a09g087-adc";
+ reg = <0 0x80008000 0 0x400>;
+ interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "adi", "gbadi", "gcadi",
+ "cmpai", "cmpbi", "wcmpm", "wcmpum";
+ clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>,
+ <&cpg CPG_MOD 225>;
+ clock-names = "adclk", "pclk";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ renesas,max-channels = <15>;
+ status = "disabled";
+ };
+
ohci: usb@92040000 {
compatible = "generic-ohci";
reg = <0 0x92040000 0 0x100>;
--
2.51.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 6/7] arm64: dts: renesas: rzt2h/rzn2h-evk: enable ADCs
2025-09-23 16:05 [PATCH 0/7] Add ADCs support for RZ/T2H and RZ/N2H Cosmin Tanislav
` (4 preceding siblings ...)
2025-09-23 16:05 ` [PATCH 5/7] arm64: dts: renesas: r9a09g087: " Cosmin Tanislav
@ 2025-09-23 16:05 ` Cosmin Tanislav
2025-09-23 16:05 ` [PATCH 7/7] arm64: defconfig: enable RZ/T2H / RZ/N2H ADC driver Cosmin Tanislav
6 siblings, 0 replies; 17+ messages in thread
From: Cosmin Tanislav @ 2025-09-23 16:05 UTC (permalink / raw)
Cc: Cosmin Tanislav, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
The ADCs on RZ/T2H and RZ/N2H are exposed on the evaluation kit boards.
Enable them.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
.../dts/renesas/r9a09g077m44-rzt2h-evk.dts | 28 +++++++
.../dts/renesas/r9a09g087m44-rzn2h-evk.dts | 64 +++++++++++++++
.../dts/renesas/rzt2h-n2h-evk-common.dtsi | 79 +++++++++++++++++++
3 files changed, 171 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
index 9170c563208a..e94b84393bd9 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g077m44-rzt2h-evk.dts
@@ -252,3 +252,31 @@ usb_pins: usb-pins {
<RZT2H_PORT_PINMUX(0, 1, 0x13)>; /* OVRCUR */
};
};
+
+&adc2 {
+ status = "okay";
+
+ channel@0 {
+ reg = <0x0>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ };
+
+ channel@5 {
+ reg = <0x5>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
index 279f2510044b..d27da157c6d6 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g087m44-rzn2h-evk.dts
@@ -305,3 +305,67 @@ usb_pins: usb-pins {
<RZT2H_PORT_PINMUX(2, 3, 0x13)>; /* OVRCUR */
};
};
+
+&adc2 {
+ status = "okay";
+
+ channel@0 {
+ reg = <0x0>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ };
+
+ channel@4 {
+ reg = <0x4>;
+ };
+
+ channel@5 {
+ reg = <0x5>;
+ };
+
+ channel@6 {
+ reg = <0x6>;
+ };
+
+ channel@7 {
+ reg = <0x7>;
+ };
+
+ channel@8 {
+ reg = <0x8>;
+ };
+
+ channel@9 {
+ reg = <0x9>;
+ };
+
+ channel@a {
+ reg = <0xa>;
+ };
+
+ channel@b {
+ reg = <0xb>;
+ };
+
+ channel@c {
+ reg = <0xc>;
+ };
+
+ channel@d {
+ reg = <0xd>;
+ };
+
+ channel@e {
+ reg = <0xe>;
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
index 9ca26725a3e9..a7123a9ec684 100644
--- a/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzt2h-n2h-evk-common.dtsi
@@ -338,3 +338,82 @@ &wdt2 {
status = "okay";
timeout-sec = <60>;
};
+
+/*
+ * ADC0 AN000 can be connected to a potentiometer on the board or
+ * exposed on ADC header.
+ *
+ * T2H:
+ * SW17[1] = ON, SW17[2] = OFF - Potentiometer
+ * SW17[1] = OFF, SW17[2] = ON - CN41 header
+ * N2H:
+ * DSW6[1] = OFF, DSW6[2] = ON - Potentiometer
+ * DSW6[1] = ON, DSW6[2] = OFF - CN3 header
+ */
+&adc0 {
+ status = "okay";
+
+ channel@0 {
+ reg = <0x0>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ };
+};
+
+/*
+ * ADC1 AN100 can be exposed on ADC header or on mikroBUS connector.
+ *
+ * T2H:
+ * SW18[1] = ON, SW18[2] = OFF - CN42 header
+ * SW18[1] = OFF, SW18[2] = ON - mikroBUS
+ * N2H:
+ * DSW6[3] = ON, DSW6[4] = OFF - CN4 header
+ * DSW6[3] = OFF, DSW6[4] = ON - mikroBUS
+ *
+ * ADC1 AN101 can be exposed on ADC header or on Grove2 connector.
+ *
+ * T2H:
+ * SW18[3] = ON, SW18[4] = OFF - CN42 header
+ * SW18[3] = OFF, SW18[4] = ON - Grove2
+ * N2H:
+ * DSW6[5] = ON, DSW6[6] = OFF - CN4 header
+ * DSW6[5] = OFF, DSW6[6] = ON - Grove2
+ *
+ * ADC1 AN102 can be exposed on ADC header or on Grove2 connector.
+ *
+ * T2H:
+ * SW18[5] = ON, SW18[6] = OFF - CN42 header
+ * SW18[5] = OFF, SW18[6] = ON - Grove2
+ * N2H:
+ * DSW6[7] = ON, DSW6[8] = OFF - CN4 header
+ * DSW6[7] = OFF, DSW6[8] = ON - Grove2
+ */
+&adc1 {
+ status = "okay";
+
+ channel@0 {
+ reg = <0x0>;
+ };
+
+ channel@1 {
+ reg = <0x1>;
+ };
+
+ channel@2 {
+ reg = <0x2>;
+ };
+
+ channel@3 {
+ reg = <0x3>;
+ };
+};
--
2.51.0
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 7/7] arm64: defconfig: enable RZ/T2H / RZ/N2H ADC driver
2025-09-23 16:05 [PATCH 0/7] Add ADCs support for RZ/T2H and RZ/N2H Cosmin Tanislav
` (5 preceding siblings ...)
2025-09-23 16:05 ` [PATCH 6/7] arm64: dts: renesas: rzt2h/rzn2h-evk: enable ADCs Cosmin Tanislav
@ 2025-09-23 16:05 ` Cosmin Tanislav
6 siblings, 0 replies; 17+ messages in thread
From: Cosmin Tanislav @ 2025-09-23 16:05 UTC (permalink / raw)
Cc: Cosmin Tanislav, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Michael Turquette, Stephen Boyd,
Lad Prabhakar, linux-iio, linux-renesas-soc, devicetree,
linux-kernel, linux-clk
Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs include three
12-Bit successive approximation A/D converters.
RZ/T2H has two ADCs with 4 channels and one with 6.
RZ/N2H has two ADCs with 4 channels and one with 15.
Enable the driver for them.
Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 8fd1bf869942..3a1326652d47 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1581,6 +1581,7 @@ CONFIG_QCOM_SPMI_VADC=m
CONFIG_QCOM_SPMI_ADC5=m
CONFIG_ROCKCHIP_SARADC=m
CONFIG_RZG2L_ADC=m
+CONFIG_RZT2H_ADC=m
CONFIG_SOPHGO_CV1800B_ADC=m
CONFIG_TI_ADS1015=m
CONFIG_TI_AM335X_ADC=m
--
2.51.0
^ permalink raw reply related [flat|nested] 17+ messages in thread