[PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Biju Das]

Drop "uart-has-rtscts: false" from binding as the IP support hardware
flow control.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 Documentation/devicetree/bindings/serial/renesas,rsci.yaml | 2 --
 1 file changed, 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index f50d8e02f476..6b1f827a335b 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -54,8 +54,6 @@ properties:
   power-domains:
     maxItems: 1
 
-  uart-has-rtscts: false
-
 required:
   - compatible
   - reg
-- 
2.43.0

[PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Biju Das]

Add documentation for the serial communication interface (RSCI) found on
the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../bindings/serial/renesas,rsci.yaml         | 82 ++++++++++++++++---
 1 file changed, 71 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
index 6b1f827a335b..7cf6348e2b5b 100644
--- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
@@ -10,17 +10,16 @@ maintainers:
   - Geert Uytterhoeven <geert+renesas@glider.be>
   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
 
-allOf:
-  - $ref: serial.yaml#
-
 properties:
   compatible:
     oneOf:
-      - items:
-          - const: renesas,r9a09g087-rsci # RZ/N2H
-          - const: renesas,r9a09g077-rsci # RZ/T2H
+      - enum:
+          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
+          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
+          - renesas,r9a09g077-rsci # RZ/T2H
 
       - items:
+          - const: renesas,r9a09g087-rsci # RZ/N2H
           - const: renesas,r9a09g077-rsci # RZ/T2H
 
   reg:
@@ -42,14 +41,40 @@ properties:
 
   clocks:
     minItems: 2
-    maxItems: 3
+    maxItems: 6
 
   clock-names:
-    minItems: 2
+    oneOf:
+      - items:
+          - const: operation
+          - const: bus
+      - items:
+          - const: operation
+          - const: bus
+          - const: sck # optional external clock input
+      - items:
+          - const: bus
+          - const: tclk
+          - const: tclk_div64
+          - const: tclk_div16
+          - const: tclk_div4
+      - items:
+          - const: bus
+          - const: tclk
+          - const: tclk_div64
+          - const: tclk_div16
+          - const: tclk_div4
+          - const: sck # optional external clock input
+
+  resets:
+    items:
+      - description: Input for resetting the APB clock
+      - description: Input for resetting TCLK
+
+  reset-names:
     items:
-      - const: operation
-      - const: bus
-      - const: sck # optional external clock input
+      - const: presetn
+      - const: tresetn
 
   power-domains:
     maxItems: 1
@@ -62,6 +87,41 @@ required:
   - clock-names
   - power-domains
 
+allOf:
+  - $ref: serial.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g077-rsci
+    then:
+      properties:
+        clocks:
+          maxItems: 3
+
+        clock-names:
+          maxItems: 3
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a09g047-rsci
+              - renesas,r9a09g047-rscif
+    then:
+      properties:
+        clocks:
+          minItems: 5
+
+        clock-names:
+          minItems: 5
+
+      required:
+        - resets
+        - reset-names
+
 unevaluatedProperties: false
 
 examples:
-- 
2.43.0

[PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes

[Biju Das]

Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 190 +++++++++++++++++++++
 1 file changed, 190 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index 7a469de3bb62..2cc950d99bd3 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -823,6 +823,196 @@ i2c8: i2c@11c01000 {
 			status = "disabled";
 		};
 
+		rsci0: serial@12800c00 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12800c00 0 0x400>;
+			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 93>, <&cpg CPG_MOD 94>,
+				 <&cpg CPG_MOD 95>, <&cpg CPG_MOD 96>,
+				 <&cpg CPG_MOD 97>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 129>, <&cpg 130>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci1: serial@12801000 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12801000 0 0x400>;
+			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 98>, <&cpg CPG_MOD 99>,
+				 <&cpg CPG_MOD 100>, <&cpg CPG_MOD 101>,
+				 <&cpg CPG_MOD 102>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 131>, <&cpg 132>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci2: serial@12801400 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12801400 0 0x400>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 103>, <&cpg CPG_MOD 104>,
+				 <&cpg CPG_MOD 105>, <&cpg CPG_MOD 106>,
+				 <&cpg CPG_MOD 107>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 133>, <&cpg 134>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci3: serial@12801800 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12801800 0 0x400>;
+			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 108>, <&cpg CPG_MOD 109>,
+				 <&cpg CPG_MOD 110>, <&cpg CPG_MOD 111>,
+				 <&cpg CPG_MOD 112>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 135>, <&cpg 136>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci4: serial@12801c00 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12801c00 0 0x400>;
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 113>, <&cpg CPG_MOD 114>,
+				 <&cpg CPG_MOD 115>, <&cpg CPG_MOD 116>,
+				 <&cpg CPG_MOD 117>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 137>, <&cpg 138>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci5: serial@12802000 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12802000 0 0x400>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 118>, <&cpg CPG_MOD 119>,
+				 <&cpg CPG_MOD 120>, <&cpg CPG_MOD 121>,
+				 <&cpg CPG_MOD 122>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 139>, <&cpg 140>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci6: serial@12802400 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12802400 0 0x400>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 123>, <&cpg CPG_MOD 124>,
+				 <&cpg CPG_MOD 125>, <&cpg CPG_MOD 126>,
+				 <&cpg CPG_MOD 127>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 141>, <&cpg 142>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci7: serial@12802800 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12802800 0 0x400>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 128>, <&cpg CPG_MOD 129>,
+				 <&cpg CPG_MOD 130>, <&cpg CPG_MOD 131>,
+				 <&cpg CPG_MOD 132>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 143>, <&cpg 144>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci8: serial@12802c00 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12802c00 0 0x400>;
+			interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 133>, <&cpg CPG_MOD 134>,
+				 <&cpg CPG_MOD 135>, <&cpg CPG_MOD 136>,
+				 <&cpg CPG_MOD 137>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 145>, <&cpg 146>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
+		rsci9: serial@12803000 {
+			compatible = "renesas,r9a09g047-rscif";
+			reg = <0 0x12803000 0 0x400>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg CPG_MOD 138>, <&cpg CPG_MOD 139>,
+				 <&cpg CPG_MOD 140>, <&cpg CPG_MOD 141>,
+				 <&cpg CPG_MOD 142>;
+			clock-names = "bus", "tclk", "tclk_div64",
+				      "tclk_div16", "tclk_div4";
+			power-domains = <&cpg>;
+			resets = <&cpg 147>, <&cpg 148>;
+			reset-names = "presetn", "tresetn";
+			status = "disabled";
+		};
+
 		gpu: gpu@14850000 {
 			compatible = "renesas,r9a09g047-mali",
 				     "arm,mali-bifrost";
-- 
2.43.0

[PATCH 18/19] arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS

[Biju Das]

SMARC2 board dtsi is common for multiple SoCs. So Move aliases
to board DTS as SoC may have different IPs for a given alias.
eg: RZ/G3S does not have RSCI interface.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 6 ++++++
 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi    | 6 ------
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 08e814c03fa8..12cd488f5dfa 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -36,6 +36,12 @@ / {
 	compatible = "renesas,smarc2-evk", "renesas,rzg3e-smarcm",
 		     "renesas,r9a09g047e57", "renesas,r9a09g047";
 
+	aliases {
+		i2c0 = &i2c0;
+		serial3 = &scif0;
+		mmc1 = &sdhi1;
+	};
+
 	vqmmc_sd1_pvdd: regulator-vqmmc-sd1-pvdd {
 		compatible = "regulator-gpio";
 		regulator-name = "SD1_PVDD";
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index 58561da3007a..a296c2c1c7ab 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -37,12 +37,6 @@ chosen {
 		stdout-path = "serial3:115200n8";
 	};
 
-	aliases {
-		i2c0 = &i2c0;
-		serial3 = &scif0;
-		mmc1 = &sdhi1;
-	};
-
 	can_transceiver0: can-phy0 {
 		compatible = "ti,tcan1042";
 		#phy-cells = <0>;
-- 
2.43.0

[PATCH 19/19] arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes

[Biju Das]

Enable device rsci{2,4,9} nodes for the RZ SMARC Carrier-II Board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   | 40 +++++++++++++++++++
 .../boot/dts/renesas/renesas-smarc2.dtsi      | 12 ++++++
 2 files changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 12cd488f5dfa..301eb6d47861 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -38,6 +38,9 @@ / {
 
 	aliases {
 		i2c0 = &i2c0;
+		serial0 = &rsci4;
+		serial1 = &rsci9;
+		serial2 = &rsci2;
 		serial3 = &scif0;
 		mmc1 = &sdhi1;
 	};
@@ -141,6 +144,26 @@ nmi_pins: nmi {
 		input-schmitt-enable;
 	};
 
+	rsci2_pins: rsci2 {
+		pinmux = <RZG3E_PORT_PINMUX(1, 1, 1)>, /* SER2_TX */
+			 <RZG3E_PORT_PINMUX(1, 0, 1)>, /* SER2_RX */
+			 <RZG3E_PORT_PINMUX(1, 2, 6)>, /* SER2_CTS# */
+			 <RZG3E_PORT_PINMUX(1, 3, 1)>; /* SER2_RTS# */
+		bias-pull-up;
+	};
+
+	rsci4_pins: rsci4 {
+		pinmux = <RZG3E_PORT_PINMUX(7, 7, 5)>, /* SER0_TX */
+			 <RZG3E_PORT_PINMUX(7, 6, 5)>; /* SER0_RX */
+		bias-pull-up;
+	};
+
+	rsci9_pins: rsci9 {
+		pinmux = <RZG3E_PORT_PINMUX(8, 3, 5)>, /* SER1_TX */
+			 <RZG3E_PORT_PINMUX(8, 2, 5)>; /* SER1_RX */
+		bias-pull-up;
+	};
+
 	scif_pins: scif {
 		pins = "SCIF_TXD", "SCIF_RXD";
 		renesas,output-impedance = <1>;
@@ -172,6 +195,23 @@ sd1-data {
 	};
 };
 
+&rsci2 {
+	pinctrl-0 = <&rsci2_pins>;
+	pinctrl-names = "default";
+
+	uart-has-rtscts;
+};
+
+&rsci4 {
+	pinctrl-0 = <&rsci4_pins>;
+	pinctrl-names = "default";
+};
+
+&rsci9 {
+	pinctrl-0 = <&rsci9_pins>;
+	pinctrl-names = "default";
+};
+
 &scif0 {
 	pinctrl-0 = <&scif_pins>;
 	pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index a296c2c1c7ab..305215cdaeb3 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -89,6 +89,18 @@ &i2c0 {
 	clock-frequency = <400000>;
 };
 
+&rsci2 {
+	status = "okay";
+};
+
+&rsci4 {
+	status = "okay";
+};
+
+&rsci9 {
+	status = "okay";
+};
+
 &scif0 {
 	status = "okay";
 };
-- 
2.43.0

Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1081 bytes --]

On Mon, Oct 27, 2025 at 03:45:49PM +0000, Biju Das wrote:
> Drop "uart-has-rtscts: false" from binding as the IP support hardware
> flow control.

Why is it being removed, rather than only being required for the
existing devices? It's not clear to me that the comment about the IP
supporting flow control excludes the integration on these particular
devices from somehow having flow control disabled.

> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  Documentation/devicetree/bindings/serial/renesas,rsci.yaml | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> index f50d8e02f476..6b1f827a335b 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -54,8 +54,6 @@ properties:
>    power-domains:
>      maxItems: 1
>  
> -  uart-has-rtscts: false
> -
>  required:
>    - compatible
>    - reg
> -- 
> 2.43.0
> 

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Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Conor Dooley]

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On Mon, Oct 27, 2025 at 03:45:50PM +0000, Biju Das wrote:
> Add documentation for the serial communication interface (RSCI) found on
> the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is identical
> to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage FIFO compared
> to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode operation. RZ/G3E
> has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
>  .../bindings/serial/renesas,rsci.yaml         | 82 ++++++++++++++++---
>  1 file changed, 71 insertions(+), 11 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> index 6b1f827a335b..7cf6348e2b5b 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> @@ -10,17 +10,16 @@ maintainers:
>    - Geert Uytterhoeven <geert+renesas@glider.be>
>    - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>  
> -allOf:
> -  - $ref: serial.yaml#
> -
>  properties:
>    compatible:
>      oneOf:
> -      - items:
> -          - const: renesas,r9a09g087-rsci # RZ/N2H
> -          - const: renesas,r9a09g077-rsci # RZ/T2H
> +      - enum:
> +          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> +          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
> +          - renesas,r9a09g077-rsci # RZ/T2H
>  
>        - items:
> +          - const: renesas,r9a09g087-rsci # RZ/N2H
>            - const: renesas,r9a09g077-rsci # RZ/T2H
>  
>    reg:
> @@ -42,14 +41,40 @@ properties:
>  
>    clocks:
>      minItems: 2
> -    maxItems: 3
> +    maxItems: 6
>  
>    clock-names:
> -    minItems: 2
> +    oneOf:
> +      - items:
> +          - const: operation
> +          - const: bus
> +      - items:
> +          - const: operation
> +          - const: bus
> +          - const: sck # optional external clock input
> +      - items:
> +          - const: bus
> +          - const: tclk
> +          - const: tclk_div64
> +          - const: tclk_div16
> +          - const: tclk_div4
> +      - items:
> +          - const: bus
> +          - const: tclk
> +          - const: tclk_div64
> +          - const: tclk_div16
> +          - const: tclk_div4
> +          - const: sck # optional external clock input
> +
> +  resets:
> +    items:
> +      - description: Input for resetting the APB clock
> +      - description: Input for resetting TCLK
> +
> +  reset-names:
>      items:
> -      - const: operation
> -      - const: bus
> -      - const: sck # optional external clock input
> +      - const: presetn
> +      - const: tresetn
>  
>    power-domains:
>      maxItems: 1
> @@ -62,6 +87,41 @@ required:
>    - clock-names
>    - power-domains
>  
> +allOf:
> +  - $ref: serial.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g077-rsci
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 3
> +
> +        clock-names:
> +          maxItems: 3
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,r9a09g047-rsci
> +              - renesas,r9a09g047-rscif
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 5
> +
> +        clock-names:
> +          minItems: 5
> +
> +      required:
> +        - resets
> +        - reset-names

Does this need an "else: properties: resets: false"? Or do other devices
actually have resets too?

> +
>  unevaluatedProperties: false
>  
>  examples:
> -- 
> 2.43.0
> 

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RE: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Biju Das]

Hi Conor Dooley,

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 28 October 2025 19:28
> Subject: Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
> 
> On Mon, Oct 27, 2025 at 03:45:49PM +0000, Biju Das wrote:
> > Drop "uart-has-rtscts: false" from binding as the IP support hardware
> > flow control.
> 
> Why is it being removed, rather than only being required for the existing devices? It's not clear to
> me that the comment about the IP supporting flow control excludes the integration on these particular
> devices from somehow having flow control disabled.

It was a mistake previously as the driver does not implement hardware flow control and
is excluded in device tree.

Actually, the RSCI IP on all SoCs supports hardware flow control.
If a channel need flow control it can make use of the property uart-has-rtscts;
That is the reason for removing hardware flow control disabled property("uart-has-rtscts: false")


Cheers,
Biju



> 
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  Documentation/devicetree/bindings/serial/renesas,rsci.yaml | 2 --
> >  1 file changed, 2 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > index f50d8e02f476..6b1f827a335b 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > @@ -54,8 +54,6 @@ properties:
> >    power-domains:
> >      maxItems: 1
> >
> > -  uart-has-rtscts: false
> > -
> >  required:
> >    - compatible
> >    - reg
> > --
> > 2.43.0
> >

RE: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Biju Das]

Hi Conor Dooley,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 28 October 2025 19:31
> Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> 
> On Mon, Oct 27, 2025 at 03:45:50PM +0000, Biju Das wrote:
> > Add documentation for the serial communication interface (RSCI) found
> > on the Renesas RZ/G3E (R9A09G047) SoC. The RSCI IP on this SoC is
> > identical to that on the RZ/T2H (R9A09G077) SoC, but it has a 32-stage
> > FIFO compared to 16 on RZ/T2H. It supports both FIFO and non-FIFO mode
> > operation. RZ/G3E has 6 clocks compared to 3 on RZ/T2H, and it has multiple resets.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> >  .../bindings/serial/renesas,rsci.yaml         | 82 ++++++++++++++++---
> >  1 file changed, 71 insertions(+), 11 deletions(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > index 6b1f827a335b..7cf6348e2b5b 100644
> > --- a/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > +++ b/Documentation/devicetree/bindings/serial/renesas,rsci.yaml
> > @@ -10,17 +10,16 @@ maintainers:
> >    - Geert Uytterhoeven <geert+renesas@glider.be>
> >    - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > -allOf:
> > -  - $ref: serial.yaml#
> > -
> >  properties:
> >    compatible:
> >      oneOf:
> > -      - items:
> > -          - const: renesas,r9a09g087-rsci # RZ/N2H
> > -          - const: renesas,r9a09g077-rsci # RZ/T2H
> > +      - enum:
> > +          - renesas,r9a09g047-rsci # RZ/G3E non FIFO mode
> > +          - renesas,r9a09g047-rscif # RZ/G3E FIFO mode
> > +          - renesas,r9a09g077-rsci # RZ/T2H
> >
> >        - items:
> > +          - const: renesas,r9a09g087-rsci # RZ/N2H
> >            - const: renesas,r9a09g077-rsci # RZ/T2H
> >
> >    reg:
> > @@ -42,14 +41,40 @@ properties:
> >
> >    clocks:
> >      minItems: 2
> > -    maxItems: 3
> > +    maxItems: 6
> >
> >    clock-names:
> > -    minItems: 2
> > +    oneOf:
> > +      - items:
> > +          - const: operation
> > +          - const: bus
> > +      - items:
> > +          - const: operation
> > +          - const: bus
> > +          - const: sck # optional external clock input
> > +      - items:
> > +          - const: bus
> > +          - const: tclk
> > +          - const: tclk_div64
> > +          - const: tclk_div16
> > +          - const: tclk_div4
> > +      - items:
> > +          - const: bus
> > +          - const: tclk
> > +          - const: tclk_div64
> > +          - const: tclk_div16
> > +          - const: tclk_div4
> > +          - const: sck # optional external clock input
> > +
> > +  resets:
> > +    items:
> > +      - description: Input for resetting the APB clock
> > +      - description: Input for resetting TCLK
> > +
> > +  reset-names:
> >      items:
> > -      - const: operation
> > -      - const: bus
> > -      - const: sck # optional external clock input
> > +      - const: presetn
> > +      - const: tresetn
> >
> >    power-domains:
> >      maxItems: 1
> > @@ -62,6 +87,41 @@ required:
> >    - clock-names
> >    - power-domains
> >
> > +allOf:
> > +  - $ref: serial.yaml#
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a09g077-rsci
> > +    then:
> > +      properties:
> > +        clocks:
> > +          maxItems: 3
> > +
> > +        clock-names:
> > +          maxItems: 3
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - renesas,r9a09g047-rsci
> > +              - renesas,r9a09g047-rscif
> > +    then:
> > +      properties:
> > +        clocks:
> > +          minItems: 5
> > +
> > +        clock-names:
> > +          minItems: 5
> > +
> > +      required:
> > +        - resets
> > +        - reset-names
> 
> Does this need an "else: properties: resets: false"? Or do other devices actually have resets too?

It is not required as resets are optional for RZ/T2H and RZ/N2H. RZ/T2H and N2H does not have
Resets.

Cheers,
Biju

> 
> > +
> >  unevaluatedProperties: false
> >
> >  examples:
> > --
> > 2.43.0
> >

Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Conor Dooley]

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On Tue, Oct 28, 2025 at 07:39:41PM +0000, Biju Das wrote:
> Hi Conor Dooley,
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 28 October 2025 19:28
> > Subject: Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
> > 
> > On Mon, Oct 27, 2025 at 03:45:49PM +0000, Biju Das wrote:
> > > Drop "uart-has-rtscts: false" from binding as the IP support hardware
> > > flow control.
> > 
> > Why is it being removed, rather than only being required for the existing devices? It's not clear to
> > me that the comment about the IP supporting flow control excludes the integration on these particular
> > devices from somehow having flow control disabled.
> 
> It was a mistake previously as the driver does not implement hardware flow control and
> is excluded in device tree.
> 
> Actually, the RSCI IP on all SoCs supports hardware flow control.
> If a channel need flow control it can make use of the property uart-has-rtscts;
> That is the reason for removing hardware flow control disabled property("uart-has-rtscts: false")

Could you update the commit message to be clear that that's the case?
Just something like "as the IP supports hardware flow control on all
SoCs".

With that,
Acked-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

pw-bot: changes-requested

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Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Conor Dooley]

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On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote:
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            enum:
> > > +              - renesas,r9a09g047-rsci
> > > +              - renesas,r9a09g047-rscif
> > > +    then:
> > > +      properties:
> > > +        clocks:
> > > +          minItems: 5
> > > +
> > > +        clock-names:
> > > +          minItems: 5
> > > +
> > > +      required:
> > > +        - resets
> > > +        - reset-names
> > 
> > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too?
> 
> It is not required as resets are optional for RZ/T2H and RZ/N2H. RZ/T2H and N2H does not have
> Resets.

This is a contradiction. Either they are optional for these platforms or
the platforms do not have resets. Cannot be both!

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RE: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Biju Das]

Hi Conor Dooley,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 28 October 2025 19:52
> Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> 
> On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote:
> > > > +  - if:
> > > > +      properties:
> > > > +        compatible:
> > > > +          contains:
> > > > +            enum:
> > > > +              - renesas,r9a09g047-rsci
> > > > +              - renesas,r9a09g047-rscif
> > > > +    then:
> > > > +      properties:
> > > > +        clocks:
> > > > +          minItems: 5
> > > > +
> > > > +        clock-names:
> > > > +          minItems: 5
> > > > +
> > > > +      required:
> > > > +        - resets
> > > > +        - reset-names
> > >
> > > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too?
> >
> > It is not required as resets are optional for RZ/T2H and RZ/N2H.
> > RZ/T2H and N2H does not have Resets.
> 
> This is a contradiction. Either they are optional for these platforms or the platforms do not have
> resets. Cannot be both!

Some RSCI IP SoCs has resets and some does not have. From RSCI IP point of view
this property is optional.

I just try to avoid complex if else statements in dt schema by adding
Per SoC properties.

If you prefer else statements for resets, I can add that as well. Please let me know.

Cheers,
Biju

RE: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"

[Biju Das]

Hi Conor Dooley,

Thanks for the feedback.

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 28 October 2025 19:51
> Subject: Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
> 
> On Tue, Oct 28, 2025 at 07:39:41PM +0000, Biju Das wrote:
> > Hi Conor Dooley,
> >
> > > -----Original Message-----
> > > From: Conor Dooley <conor@kernel.org>
> > > Sent: 28 October 2025 19:28
> > > Subject: Re: [PATCH 02/19] dt-bindings: serial: rsci: Drop "uart-has-rtscts: false"
> > >
> > > On Mon, Oct 27, 2025 at 03:45:49PM +0000, Biju Das wrote:
> > > > Drop "uart-has-rtscts: false" from binding as the IP support
> > > > hardware flow control.
> > >
> > > Why is it being removed, rather than only being required for the
> > > existing devices? It's not clear to me that the comment about the IP
> > > supporting flow control excludes the integration on these particular devices from somehow having
> flow control disabled.
> >
> > It was a mistake previously as the driver does not implement hardware
> > flow control and is excluded in device tree.
> >
> > Actually, the RSCI IP on all SoCs supports hardware flow control.
> > If a channel need flow control it can make use of the property
> > uart-has-rtscts; That is the reason for removing hardware flow control
> > disabled property("uart-has-rtscts: false")
> 
> Could you update the commit message to be clear that that's the case?
> Just something like "as the IP supports hardware flow control on all SoCs".

Agreed, Should I add fixes tag as well?

Cheers,
Biju

> 
> With that,
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> 
> Cheers,
> Conor.
> 
> pw-bot: changes-requested

Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support

[Conor Dooley]

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On Tue, Oct 28, 2025 at 08:26:08PM +0000, Biju Das wrote:
> Hi Conor Dooley,
> 
> Thanks for the feedback.
> 
> > -----Original Message-----
> > From: Conor Dooley <conor@kernel.org>
> > Sent: 28 October 2025 19:52
> > Subject: Re: [PATCH 03/19] dt-bindings: serial: renesas,rsci: Document RZ/G3E support
> > 
> > On Tue, Oct 28, 2025 at 07:41:33PM +0000, Biju Das wrote:
> > > > > +  - if:
> > > > > +      properties:
> > > > > +        compatible:
> > > > > +          contains:
> > > > > +            enum:
> > > > > +              - renesas,r9a09g047-rsci
> > > > > +              - renesas,r9a09g047-rscif
> > > > > +    then:
> > > > > +      properties:
> > > > > +        clocks:
> > > > > +          minItems: 5
> > > > > +
> > > > > +        clock-names:
> > > > > +          minItems: 5
> > > > > +
> > > > > +      required:
> > > > > +        - resets
> > > > > +        - reset-names
> > > >
> > > > Does this need an "else: properties: resets: false"? Or do other devices actually have resets too?
> > >
> > > It is not required as resets are optional for RZ/T2H and RZ/N2H.
> > > RZ/T2H and N2H does not have Resets.
> > 
> > This is a contradiction. Either they are optional for these platforms or the platforms do not have
> > resets. Cannot be both!
> 
> Some RSCI IP SoCs has resets and some does not have. From RSCI IP point of view
> this property is optional.
> 
> I just try to avoid complex if else statements in dt schema by adding
> Per SoC properties.
> 
> If you prefer else statements for resets, I can add that as well. Please let me know.

I would prefer that you do that, yes.

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Re: [PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes

[Geert Uytterhoeven]

Hi Biju,

On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> @@ -823,6 +823,196 @@ i2c8: i2c@11c01000 {
>                         status = "disabled";
>                 };
>
> +               rsci0: serial@12800c00 {
> +                       compatible = "renesas,r9a09g047-rscif";

"renesas,r9a09g047-rsci", as per the updated DT bindings.

> +                       reg = <0 0x12800c00 0 0x400>;
> +                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> +                                    <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
> +                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "eri", "rxi", "txi", "tei";

Missing "aed" and "bfd" interrupts, as per to-be-updated DT bindings.

> +                       clocks = <&cpg CPG_MOD 93>, <&cpg CPG_MOD 94>,
> +                                <&cpg CPG_MOD 95>, <&cpg CPG_MOD 96>,
> +                                <&cpg CPG_MOD 97>;
> +                       clock-names = "bus", "tclk", "tclk_div64",
> +                                     "tclk_div16", "tclk_div4";

Third and fifth clock and clock name should be exchanged, as per the
updated DT bindings.

> +                       power-domains = <&cpg>;
> +                       resets = <&cpg 129>, <&cpg 130>;

Please use hexadecimal numbers for module clocks and resets, for
easier matching with the documentation.

> +                       reset-names = "presetn", "tresetn";
> +                       status = "disabled";
> +               };

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 18/19] arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS

[Geert Uytterhoeven]

Hi Biju,

On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> SMARC2 board dtsi is common for multiple SoCs. So Move aliases
> to board DTS as SoC may have different IPs for a given alias.
> eg: RZ/G3S does not have RSCI interface.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

Makes sense, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 19/19] arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes

[Geert Uytterhoeven]

Hi Biju,

On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Enable device rsci{2,4,9} nodes for the RZ SMARC Carrier-II Board.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> @@ -38,6 +38,9 @@ / {
>
>         aliases {
>                 i2c0 = &i2c0;
> +               serial0 = &rsci4;
> +               serial1 = &rsci9;
> +               serial2 = &rsci2;
>                 serial3 = &scif0;
>                 mmc1 = &sdhi1;
>         };
> @@ -141,6 +144,26 @@ nmi_pins: nmi {
>                 input-schmitt-enable;
>         };
>
> +       rsci2_pins: rsci2 {
> +               pinmux = <RZG3E_PORT_PINMUX(1, 1, 1)>, /* SER2_TX */
> +                        <RZG3E_PORT_PINMUX(1, 0, 1)>, /* SER2_RX */

Why not order by port number?

> +                        <RZG3E_PORT_PINMUX(1, 2, 6)>, /* SER2_CTS# */
> +                        <RZG3E_PORT_PINMUX(1, 3, 1)>; /* SER2_RTS# */

These comments reflect the board signals?  Usually we put the pin
functions ("TXD2", "RXD2", "CTS2N", "RTS2N") in the comments.

> +               bias-pull-up;
> +       };
> +
> +       rsci4_pins: rsci4 {
> +               pinmux = <RZG3E_PORT_PINMUX(7, 7, 5)>, /* SER0_TX */
> +                        <RZG3E_PORT_PINMUX(7, 6, 5)>; /* SER0_RX */

Why not order by port number?

Pin functions are "TXD4" and "RXD4".

CTS4N and RTS4N seem to be wired, too?

> +               bias-pull-up;
> +       };
> +
> +       rsci9_pins: rsci9 {
> +               pinmux = <RZG3E_PORT_PINMUX(8, 3, 5)>, /* SER1_TX */
> +                        <RZG3E_PORT_PINMUX(8, 2, 5)>; /* SER1_RX */

Why not order by port number?

Pin functions are "TXD9" and "RXD9".

> +               bias-pull-up;
> +       };
> +
>         scif_pins: scif {
>                 pins = "SCIF_TXD", "SCIF_RXD";
>                 renesas,output-impedance = <1>;
> @@ -172,6 +195,23 @@ sd1-data {
>         };
>  };
>
> +&rsci2 {
> +       pinctrl-0 = <&rsci2_pins>;
> +       pinctrl-names = "default";
> +
> +       uart-has-rtscts;
> +};

Shouldn't this be wrapped inside an #ifdef controlled by new defines
SW_SER2_EN and SW_SER0_PMOD?

> +
> +&rsci4 {
> +       pinctrl-0 = <&rsci4_pins>;
> +       pinctrl-names = "default";

uart-has-rtscts?

> +};

Shouldn't this be wrapped inside an #ifdef controlled by SW_LCD_EN?
The port seems to be available irrespective of the setting of
SW_SER0_PMOD, which merely controls routing to either the PMOD or the
M.2 connector.

> +
> +&rsci9 {
> +       pinctrl-0 = <&rsci9_pins>;
> +       pinctrl-names = "default";
> +};
> +
>  &scif0 {
>         pinctrl-0 = <&scif_pins>;
>         pinctrl-names = "default";
> diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> index a296c2c1c7ab..305215cdaeb3 100644
> --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> @@ -89,6 +89,18 @@ &i2c0 {
>         clock-frequency = <400000>;
>  };
>
> +&rsci2 {
> +       status = "okay";
> +};
> +
> +&rsci4 {
> +       status = "okay";
> +};
> +
> +&rsci9 {
> +       status = "okay";
> +};

Given "[PATCH 18/19] arm64: dts: renesas: renesas-smarc2: Move aliases
to board DTS" because RZ/G3S does not have RSCI interfaces, why are
these added here instead of to r9a09g047e57-smarc.dts?

> +
>  &scif0 {
>         status = "okay";
>  };

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 28 November 2025 13:05
> Subject: Re: [PATCH 17/19] arm64: dts: renesas: r9a09g047: Add RSCI nodes
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Add RSCI nodes to RZ/G3E ("R9A09G047") SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
> > @@ -823,6 +823,196 @@ i2c8: i2c@11c01000 {
> >                         status = "disabled";
> >                 };
> >
> > +               rsci0: serial@12800c00 {
> > +                       compatible = "renesas,r9a09g047-rscif";
> 
> "renesas,r9a09g047-rsci", as per the updated DT bindings.

OK.

> 
> > +                       reg = <0 0x12800c00 0 0x400>;
> > +                       interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> > +                                    <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
> > +                                    <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
> > +                       interrupt-names = "eri", "rxi", "txi", "tei";
> 
> Missing "aed" and "bfd" interrupts, as per to-be-updated DT bindings.

OK.

> 
> > +                       clocks = <&cpg CPG_MOD 93>, <&cpg CPG_MOD 94>,
> > +                                <&cpg CPG_MOD 95>, <&cpg CPG_MOD 96>,
> > +                                <&cpg CPG_MOD 97>;
> > +                       clock-names = "bus", "tclk", "tclk_div64",
> > +                                     "tclk_div16", "tclk_div4";
> 
> Third and fifth clock and clock name should be exchanged, as per the updated DT bindings.

OK.
> 
> > +                       power-domains = <&cpg>;
> > +                       resets = <&cpg 129>, <&cpg 130>;
> 
> Please use hexadecimal numbers for module clocks and resets, for easier matching with the
> documentation.

Agreed, Will fix this in next version.

Cheers,
Biju

RE: [PATCH 19/19] arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes

[Biju Das]

Hi Geert,

Thanks for the feedback

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 28 November 2025 13:41
> Subject: Re: [PATCH 19/19] arm64: dts: renesas: renesas-smarc2: Enable rsci{2,4,9} nodes
> 
> Hi Biju,
> 
> On Mon, 27 Oct 2025 at 16:47, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Enable device rsci{2,4,9} nodes for the RZ SMARC Carrier-II Board.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
> > @@ -38,6 +38,9 @@ / {
> >
> >         aliases {
> >                 i2c0 = &i2c0;
> > +               serial0 = &rsci4;
> > +               serial1 = &rsci9;
> > +               serial2 = &rsci2;
> >                 serial3 = &scif0;
> >                 mmc1 = &sdhi1;
> >         };
> > @@ -141,6 +144,26 @@ nmi_pins: nmi {
> >                 input-schmitt-enable;
> >         };
> >
> > +       rsci2_pins: rsci2 {
> > +               pinmux = <RZG3E_PORT_PINMUX(1, 1, 1)>, /* SER2_TX */
> > +                        <RZG3E_PORT_PINMUX(1, 0, 1)>, /* SER2_RX */
> 
> Why not order by port number?

It is mistake, will fix it.

> 
> > +                        <RZG3E_PORT_PINMUX(1, 2, 6)>, /* SER2_CTS# */
> > +                        <RZG3E_PORT_PINMUX(1, 3, 1)>; /* SER2_RTS# */
> 
> These comments reflect the board signals?  Usually we put the pin functions ("TXD2", "RXD2", "CTS2N",
> "RTS2N") in the comments.

OK.

> 
> > +               bias-pull-up;
> > +       };
> > +
> > +       rsci4_pins: rsci4 {
> > +               pinmux = <RZG3E_PORT_PINMUX(7, 7, 5)>, /* SER0_TX */
> > +                        <RZG3E_PORT_PINMUX(7, 6, 5)>; /* SER0_RX */
> 
> Why not order by port number?
> 
> Pin functions are "TXD4" and "RXD4".
> 

OK.

> CTS4N and RTS4N seem to be wired, too?

OK, Will add.

> 
> > +               bias-pull-up;
> > +       };
> > +
> > +       rsci9_pins: rsci9 {
> > +               pinmux = <RZG3E_PORT_PINMUX(8, 3, 5)>, /* SER1_TX */
> > +                        <RZG3E_PORT_PINMUX(8, 2, 5)>; /* SER1_RX */
> 
> Why not order by port number?
> 
> Pin functions are "TXD9" and "RXD9".

OK, will fix this.

> 
> > +               bias-pull-up;
> > +       };
> > +
> >         scif_pins: scif {
> >                 pins = "SCIF_TXD", "SCIF_RXD";
> >                 renesas,output-impedance = <1>; @@ -172,6 +195,23 @@
> > sd1-data {
> >         };
> >  };
> >
> > +&rsci2 {
> > +       pinctrl-0 = <&rsci2_pins>;
> > +       pinctrl-names = "default";
> > +
> > +       uart-has-rtscts;
> > +};
> 
> Shouldn't this be wrapped inside an #ifdef controlled by new defines SW_SER2_EN and SW_SER0_PMOD?

OK, Will add this macros.

SW_SER2_EN by default ON
SW_SER0_PMOD by default ON.

> 
> > +
> > +&rsci4 {
> > +       pinctrl-0 = <&rsci4_pins>;
> > +       pinctrl-names = "default";
> 
> uart-has-rtscts?

OK, Will add.

> 
> > +};
> 
> Shouldn't this be wrapped inside an #ifdef controlled by SW_LCD_EN?

Yes. We cannot use this signal if DPI turned on.

> The port seems to be available irrespective of the setting of SW_SER0_PMOD, which merely controls
> routing to either the PMOD or the
> M.2 connector.

I agree, SW_OPT_MUX.4 will be always on for that
(SMARC SER0 signals connect to PMOD, SMARC SER2 signals connect to M.2 Key-E)

> 
> > +
> > +&rsci9 {
> > +       pinctrl-0 = <&rsci9_pins>;
> > +       pinctrl-names = "default";
> > +};
> > +
> >  &scif0 {
> >         pinctrl-0 = <&scif_pins>;
> >         pinctrl-names = "default";
> > diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > index a296c2c1c7ab..305215cdaeb3 100644
> > --- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
> > @@ -89,6 +89,18 @@ &i2c0 {
> >         clock-frequency = <400000>;
> >  };
> >
> > +&rsci2 {
> > +       status = "okay";
> > +};
> > +
> > +&rsci4 {
> > +       status = "okay";
> > +};
> > +
> > +&rsci9 {
> > +       status = "okay";
> > +};
> 
> Given "[PATCH 18/19] arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS" because RZ/G3S
> does not have RSCI interfaces, why are these added here instead of to r9a09g047e57-smarc.dts?

Agreed.


Cheers,
Biju