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From: Conor Dooley <conor@kernel.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
	devicetree@vger.kernel.org,
	Valentina.FernandezAlanis@microchip.com
Subject: Re: [RFC v1 0/4] Microchip mpfs/pic64gx pinctrl part 2
Date: Thu, 20 Nov 2025 00:25:46 +0000	[thread overview]
Message-ID: <20251120-unguarded-stony-a58ea2401605@spud> (raw)
In-Reply-To: <CACRpkdZOak-+Aahj7fte9gk9m+76LOguEsO7bBbHTMTfLExWcA@mail.gmail.com>

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On Wed, Nov 19, 2025 at 10:31:47PM +0100, Linus Walleij wrote:
> On Wed, Nov 19, 2025 at 7:06 PM Conor Dooley <conor@kernel.org> wrote:
> > On Wed, Nov 19, 2025 at 01:16:16PM +0100, Linus Walleij wrote:
> > > On Wed, Nov 12, 2025 at 3:33 PM Conor Dooley <conor@kernel.org> wrote:
> 
> > > > and b) how the bank voltage
> > > > interacts with the schmitt trigger setting.
> > >
> > > Please check if "bank voltage" is somewhat analogous to
> > > this generic config:
> > >
> > > * @PIN_CONFIG_POWER_SOURCE: if the pin can select between different power
> > >  *      supplies, the argument to this parameter (on a custom format) tells
> > >  *      the driver which alternative power source to use.
> >
> > It's not pin based, the whole bank it is connected to has to be changed.
> 
> So there *is* such a thing as a group pin config setting for a
> whole group of pins. Groups are not just for functions...
> 
> And I don't know what is meant by a bank here, but it seems
> to be exactly a group of pins.

Yeah, it's a whole group of pins. There's two banks that the IOs this
driver controls are split between, they don't really neatly correspond
to a particular function (although the configurator doesn't permit a
function belong to two banks, but it is technically possible for them
to).
> 
> From arch/arm/boot/dts/gemini/gemini-sq201.dts:
> 
>  /* Set up drive strength on GMAC0 and GMAC1 to 16 mA */
> conf9 {
>     groups = "gmii_gmac0_grp", "gmii_gmac1_grp";
>     drive-strength = <16>;
> };
> 
> If you look in driver/pinctrl/pinctrl-gemini.c you find:
> gemini_pinconf_group_set()
> 
> static const struct pinconf_ops gemini_pinconf_ops = {
>         .pin_config_get = gemini_pinconf_get,
>         .pin_config_set = gemini_pinconf_set,
>         .pin_config_group_set = gemini_pinconf_group_set,
>         .is_generic = true,
> };
> 
> OTOMH it's actually *fine* to *just* use groups for pin config like this
> and *not* use it for muxing, i.e. have this group correspond to
> a bank and not use that group for anything else than to set this
> or any other per-bank property. But have a look!

I could just put it in as a per-pin thing, even if the control isn't
actually that granular. The bank lockdown has a per-pin bit, but is
actually a bank wide toggle in the configurator, it wouldn't be too
different.

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      reply	other threads:[~2025-11-20  0:25 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-12 14:31 [RFC v1 0/4] Microchip mpfs/pic64gx pinctrl part 2 Conor Dooley
2025-11-12 14:31 ` [RFC v1 1/4] dt-bindings: pinctrl: document polarfire soc mssio pin controller Conor Dooley
2025-11-19  9:13   ` Linus Walleij
2025-11-12 14:31 ` [RFC v1 2/4] pinctrl: add polarfire soc mssio pinctrl driver Conor Dooley
2025-11-19 12:08   ` Linus Walleij
2025-11-19 18:23     ` Conor Dooley
2025-11-19 21:48       ` Linus Walleij
2025-11-20  0:26         ` Conor Dooley
2025-11-20 23:13           ` Linus Walleij
2025-11-21 10:46             ` Conor Dooley
2025-11-21 11:21               ` Conor Dooley
2025-11-24 17:16                 ` Conor Dooley
2025-11-25  0:31                   ` Linus Walleij
2025-11-25  1:03                     ` Conor Dooley
2025-11-25 16:09                       ` Linus Walleij
2025-11-25  0:10                 ` Linus Walleij
2025-11-25  0:24                   ` Conor Dooley
2025-11-24 19:14     ` Conor Dooley
2025-11-25 13:24       ` Linus Walleij
2025-11-25 17:47         ` Conor Dooley
2025-11-25 19:28           ` Linus Walleij
2025-11-25 19:55             ` Conor Dooley
2025-11-25 19:59               ` Linus Walleij
2025-11-12 14:31 ` [RFC v1 3/4] MAINTAINERS: add Microchip mpfs mssio driver/bindings to entry Conor Dooley
2025-11-12 14:31 ` [RFC v1 4/4] riscv: dts: microchip: add pinctrl nodes for mpfs/icicle kit Conor Dooley
2025-11-19 12:16 ` [RFC v1 0/4] Microchip mpfs/pic64gx pinctrl part 2 Linus Walleij
2025-11-19 18:06   ` Conor Dooley
2025-11-19 21:31     ` Linus Walleij
2025-11-20  0:25       ` Conor Dooley [this message]

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