* [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
@ 2026-01-20 12:52 ` Biju
2026-01-20 17:34 ` Fabrizio Castro
` (2 more replies)
2026-01-20 12:52 ` [PATCH 02/12] dt-bindings: dma: rz-dmac: " Biju
` (8 subsequent siblings)
9 siblings, 3 replies; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, linux-kernel, linux-serial, devicetree,
linux-renesas-soc, Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add SCIF binding documentation for Renesas RZ/G3L SoC. SCIF block on the
RZ/G3L is identical to one found on the RZ/G3S SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
index a6ef02327be8..82f54446835e 100644
--- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
+++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
@@ -82,6 +82,7 @@ properties:
- renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five
- renesas,scif-r9a07g054 # RZ/V2L
- renesas,scif-r9a08g045 # RZ/G3S
+ - renesas,scif-r9a08g046 # RZ/G3L
- const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
- items:
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* RE: [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC
2026-01-20 12:52 ` [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC Biju
@ 2026-01-20 17:34 ` Fabrizio Castro
2026-01-20 19:49 ` Conor Dooley
2026-03-04 8:24 ` Geert Uytterhoeven
2 siblings, 0 replies; 27+ messages in thread
From: Fabrizio Castro @ 2026-01-20 17:34 UTC (permalink / raw)
To: biju.das.au, Greg Kroah-Hartman, Jiri Slaby, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Geert Uytterhoeven,
magnus.damm
Cc: Biju Das, linux-kernel@vger.kernel.org,
linux-serial@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad,
biju.das.au
> From: Biju <biju.das.au@gmail.com>
> Sent: 20 January 2026 12:52
> To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Jiri Slaby <jirislaby@kernel.org>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Geert
> Uytterhoeven <geert+renesas@glider.be>; magnus.damm <magnus.damm@gmail.com>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; linux-kernel@vger.kernel.org; linux-serial@vger.kernel.org;
> devicetree@vger.kernel.org; linux-renesas-soc@vger.kernel.org; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>; biju.das.au <biju.das.au@gmail.com>
> Subject: [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC
>
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add SCIF binding documentation for Renesas RZ/G3L SoC. SCIF block on the
> RZ/G3L is identical to one found on the RZ/G3S SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> Documentation/devicetree/bindings/serial/renesas,scif.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> index a6ef02327be8..82f54446835e 100644
> --- a/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> +++ b/Documentation/devicetree/bindings/serial/renesas,scif.yaml
> @@ -82,6 +82,7 @@ properties:
> - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five
> - renesas,scif-r9a07g054 # RZ/V2L
> - renesas,scif-r9a08g045 # RZ/G3S
> + - renesas,scif-r9a08g046 # RZ/G3L
> - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback
>
> - items:
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC
2026-01-20 12:52 ` [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC Biju
2026-01-20 17:34 ` Fabrizio Castro
@ 2026-01-20 19:49 ` Conor Dooley
2026-03-04 8:24 ` Geert Uytterhoeven
2 siblings, 0 replies; 27+ messages in thread
From: Conor Dooley @ 2026-01-20 19:49 UTC (permalink / raw)
To: Biju
Cc: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Biju Das,
linux-kernel, linux-serial, devicetree, linux-renesas-soc,
Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC
2026-01-20 12:52 ` [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC Biju
2026-01-20 17:34 ` Fabrizio Castro
2026-01-20 19:49 ` Conor Dooley
@ 2026-03-04 8:24 ` Geert Uytterhoeven
2 siblings, 0 replies; 27+ messages in thread
From: Geert Uytterhoeven @ 2026-03-04 8:24 UTC (permalink / raw)
To: Biju
Cc: Greg Kroah-Hartman, Jiri Slaby, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Biju Das, linux-kernel, linux-serial,
devicetree, linux-renesas-soc, Prabhakar Mahadev Lad
On Tue, 20 Jan 2026 at 13:52, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add SCIF binding documentation for Renesas RZ/G3L SoC. SCIF block on the
> RZ/G3L is identical to one found on the RZ/G3S SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 02/12] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
2026-01-20 12:52 ` [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC Biju
@ 2026-01-20 12:52 ` Biju
2026-01-20 17:35 ` Fabrizio Castro
2026-01-20 19:51 ` Conor Dooley
2026-01-20 12:52 ` [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants Biju
` (7 subsequent siblings)
9 siblings, 2 replies; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm
Cc: Biju Das, dmaengine, devicetree, linux-kernel, linux-renesas-soc,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document the Renesas RZ/G3L DMAC block. This is identical to the one found
on the RZ/G3S SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index d137b9cbaee9..e3311029eb2f 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -19,6 +19,7 @@ properties:
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
- renesas,r9a07g054-dmac # RZ/V2L
- renesas,r9a08g045-dmac # RZ/G3S
+ - renesas,r9a08g046-dmac # RZ/G3L
- const: renesas,rz-dmac
- items:
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* RE: [PATCH 02/12] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
2026-01-20 12:52 ` [PATCH 02/12] dt-bindings: dma: rz-dmac: " Biju
@ 2026-01-20 17:35 ` Fabrizio Castro
2026-01-20 19:51 ` Conor Dooley
1 sibling, 0 replies; 27+ messages in thread
From: Fabrizio Castro @ 2026-01-20 17:35 UTC (permalink / raw)
To: biju.das.au, Vinod Koul, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, magnus.damm
Cc: Biju Das, dmaengine@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Prabhakar Mahadev Lad, biju.das.au
> From: Biju <biju.das.au@gmail.com>
> Sent: 20 January 2026 12:52
> To: Vinod Koul <vkoul@kernel.org>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Geert Uytterhoeven <geert+renesas@glider.be>;
> magnus.damm <magnus.damm@gmail.com>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; dmaengine@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; linux-renesas-soc@vger.kernel.org; Prabhakar Mahadev Lad
> <prabhakar.mahadev-lad.rj@bp.renesas.com>; biju.das.au <biju.das.au@gmail.com>
> Subject: [PATCH 02/12] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
>
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document the Renesas RZ/G3L DMAC block. This is identical to the one found
> on the RZ/G3S SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> index d137b9cbaee9..e3311029eb2f 100644
> --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -19,6 +19,7 @@ properties:
> - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> - renesas,r9a07g054-dmac # RZ/V2L
> - renesas,r9a08g045-dmac # RZ/G3S
> + - renesas,r9a08g046-dmac # RZ/G3L
> - const: renesas,rz-dmac
>
> - items:
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [PATCH 02/12] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
2026-01-20 12:52 ` [PATCH 02/12] dt-bindings: dma: rz-dmac: " Biju
2026-01-20 17:35 ` Fabrizio Castro
@ 2026-01-20 19:51 ` Conor Dooley
1 sibling, 0 replies; 27+ messages in thread
From: Conor Dooley @ 2026-01-20 19:51 UTC (permalink / raw)
To: Biju
Cc: Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Biju Das, dmaengine, devicetree,
linux-kernel, linux-renesas-soc, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
2026-01-20 12:52 ` [PATCH 01/12] dt-bindings: serial: renesas,scif: Document RZ/G3L SoC Biju
2026-01-20 12:52 ` [PATCH 02/12] dt-bindings: dma: rz-dmac: " Biju
@ 2026-01-20 12:52 ` Biju
2026-01-20 17:41 ` Fabrizio Castro
2026-01-20 19:50 ` Conor Dooley
2026-01-20 12:52 ` [PATCH 04/12] dt-bindings: soc: renesas: Document RZ/G3L SMARC SoM and Carrier-II EVK Biju
` (6 subsequent siblings)
9 siblings, 2 replies; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document Renesas RZ/G3L (R9A08G046) SoC variants.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../devicetree/bindings/soc/renesas/renesas.yaml | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index f4947ac65460..be61a71c7305 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -548,6 +548,15 @@ properties:
- const: renesas,r9a08g045s33 # PCIe support
- const: renesas,r9a08g045
+ - description: RZ/G3L (R9A08G046)
+ items:
+ - enum:
+ - renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 (14mm LFBGA)
+ - renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 (17mm LFBGA)
+ - renesas,r9a08g046l46 # Quad Cortex-A55 + Cortex-M33 (14mm LFBGA)
+ - renesas,r9a08g046l48 # Quad Cortex-A55 + Cortex-M33 + GE3D/VCP (17mm LFBGA)
+ - const: renesas,r9a08g046
+
- description: RZ/V2M (R9A09G011)
items:
- enum:
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* RE: [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants
2026-01-20 12:52 ` [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants Biju
@ 2026-01-20 17:41 ` Fabrizio Castro
2026-01-20 17:48 ` Biju Das
2026-01-20 19:50 ` Conor Dooley
1 sibling, 1 reply; 27+ messages in thread
From: Fabrizio Castro @ 2026-01-20 17:41 UTC (permalink / raw)
To: biju.das.au, Geert Uytterhoeven, magnus.damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Prabhakar Mahadev Lad, biju.das.au
Hi Biju,
thanks for your patch.
> From: Biju <biju.das.au@gmail.com>
> Sent: 20 January 2026 12:52
> To: Geert Uytterhoeven <geert+renesas@glider.be>; magnus.damm <magnus.damm@gmail.com>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; biju.das.au <biju.das.au@gmail.com>
> Subject: [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants
>
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document Renesas RZ/G3L (R9A08G046) SoC variants.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../devicetree/bindings/soc/renesas/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> index f4947ac65460..be61a71c7305 100644
> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -548,6 +548,15 @@ properties:
> - const: renesas,r9a08g045s33 # PCIe support
> - const: renesas,r9a08g045
>
> + - description: RZ/G3L (R9A08G046)
> + items:
> + - enum:
> + - renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 (14mm LFBGA)
> + - renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 (17mm LFBGA)
> + - renesas,r9a08g046l46 # Quad Cortex-A55 + Cortex-M33 (14mm LFBGA)
> + - renesas,r9a08g046l48 # Quad Cortex-A55 + Cortex-M33 + GE3D/VCP (17mm LFBGA)
The document I am looking at seems to indicate that all of the above parts come
with GE3D/VCP, but we are only mentioning that for the last part number?
Cheers,
Fab
> + - const: renesas,r9a08g046
> +
> - description: RZ/V2M (R9A09G011)
> items:
> - enum:
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants
2026-01-20 17:41 ` Fabrizio Castro
@ 2026-01-20 17:48 ` Biju Das
0 siblings, 0 replies; 27+ messages in thread
From: Biju Das @ 2026-01-20 17:48 UTC (permalink / raw)
To: Fabrizio Castro, biju.das.au, Geert Uytterhoeven, magnus.damm,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad, biju.das.au
Hi Fabrizio,
Thanks for the feedback.
> -----Original Message-----
> From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Sent: 20 January 2026 17:42
> Subject: RE: [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants
>
> Hi Biju,
>
> thanks for your patch.
>
> > From: Biju <biju.das.au@gmail.com>
> > Sent: 20 January 2026 12:52
> > To: Geert Uytterhoeven <geert+renesas@glider.be>; magnus.damm
> > <magnus.damm@gmail.com>; Rob Herring <robh@kernel.org>; Krzysztof
> > Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>
> > Cc: Biju Das <biju.das.jz@bp.renesas.com>;
> > linux-renesas-soc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Prabhakar
> > Mahadev Lad <prabhakar.mahadev- lad.rj@bp.renesas.com>; biju.das.au
> > <biju.das.au@gmail.com>
> > Subject: [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas
> > RZ/G3L SoC variants
> >
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document Renesas RZ/G3L (R9A08G046) SoC variants.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > .../devicetree/bindings/soc/renesas/renesas.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > index f4947ac65460..be61a71c7305 100644
> > --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > @@ -548,6 +548,15 @@ properties:
> > - const: renesas,r9a08g045s33 # PCIe support
> > - const: renesas,r9a08g045
> >
> > + - description: RZ/G3L (R9A08G046)
> > + items:
> > + - enum:
> > + - renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 (14mm LFBGA)
> > + - renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 (17mm LFBGA)
> > + - renesas,r9a08g046l46 # Quad Cortex-A55 + Cortex-M33 (14mm LFBGA)
> > + - renesas,r9a08g046l48 # Quad Cortex-A55 + Cortex-M33 +
> > + GE3D/VCP (17mm LFBGA)
>
> The document I am looking at seems to indicate that all of the above parts come with GE3D/VCP, but we
> are only mentioning that for the last part number?
Good catch. When I looked it was on the first line. I did not thought it is for all the variants.
You are correct. I will fix it in next version.
Cheers,
Biju
>
> Cheers,
> Fab
>
> > + - const: renesas,r9a08g046
> > +
> > - description: RZ/V2M (R9A09G011)
> > items:
> > - enum:
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants
2026-01-20 12:52 ` [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants Biju
2026-01-20 17:41 ` Fabrizio Castro
@ 2026-01-20 19:50 ` Conor Dooley
2026-01-21 16:23 ` Biju Das
1 sibling, 1 reply; 27+ messages in thread
From: Conor Dooley @ 2026-01-20 19:50 UTC (permalink / raw)
To: Biju
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Biju Das, linux-renesas-soc, devicetree,
linux-kernel, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 1548 bytes --]
On Tue, Jan 20, 2026 at 12:52:14PM +0000, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document Renesas RZ/G3L (R9A08G046) SoC variants.
I don't get why this is a standalone commit, when you come along in the
next patch and add required items to the list. Think that should be a
single patch.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../devicetree/bindings/soc/renesas/renesas.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> index f4947ac65460..be61a71c7305 100644
> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -548,6 +548,15 @@ properties:
> - const: renesas,r9a08g045s33 # PCIe support
> - const: renesas,r9a08g045
>
> + - description: RZ/G3L (R9A08G046)
> + items:
> + - enum:
> + - renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 (14mm LFBGA)
> + - renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 (17mm LFBGA)
> + - renesas,r9a08g046l46 # Quad Cortex-A55 + Cortex-M33 (14mm LFBGA)
> + - renesas,r9a08g046l48 # Quad Cortex-A55 + Cortex-M33 + GE3D/VCP (17mm LFBGA)
> + - const: renesas,r9a08g046
> +
> - description: RZ/V2M (R9A09G011)
> items:
> - enum:
> --
> 2.43.0
>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* RE: [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants
2026-01-20 19:50 ` Conor Dooley
@ 2026-01-21 16:23 ` Biju Das
0 siblings, 0 replies; 27+ messages in thread
From: Biju Das @ 2026-01-21 16:23 UTC (permalink / raw)
To: Conor Dooley, biju.das.au
Cc: Geert Uytterhoeven, magnus.damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Prabhakar Mahadev Lad
Hi Conor,
Thanks for the feedback.
> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 20 January 2026 19:51
> Subject: Re: [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants
>
> On Tue, Jan 20, 2026 at 12:52:14PM +0000, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document Renesas RZ/G3L (R9A08G046) SoC variants.
>
> I don't get why this is a standalone commit, when you come along in the next patch and add required
> items to the list. Think that should be a single patch.
OK will squash both the patches.
Cheers,
Biju
>
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > .../devicetree/bindings/soc/renesas/renesas.yaml | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > index f4947ac65460..be61a71c7305 100644
> > --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> > @@ -548,6 +548,15 @@ properties:
> > - const: renesas,r9a08g045s33 # PCIe support
> > - const: renesas,r9a08g045
> >
> > + - description: RZ/G3L (R9A08G046)
> > + items:
> > + - enum:
> > + - renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 (14mm LFBGA)
> > + - renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 (17mm LFBGA)
> > + - renesas,r9a08g046l46 # Quad Cortex-A55 + Cortex-M33 (14mm LFBGA)
> > + - renesas,r9a08g046l48 # Quad Cortex-A55 + Cortex-M33 + GE3D/VCP (17mm LFBGA)
> > + - const: renesas,r9a08g046
> > +
> > - description: RZ/V2M (R9A09G011)
> > items:
> > - enum:
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 04/12] dt-bindings: soc: renesas: Document RZ/G3L SMARC SoM and Carrier-II EVK
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
` (2 preceding siblings ...)
2026-01-20 12:52 ` [PATCH 03/12] dt-bindings: soc: renesas: Document Renesas RZ/G3L SoC variants Biju
@ 2026-01-20 12:52 ` Biju
2026-01-20 17:42 ` Fabrizio Castro
2026-01-20 12:52 ` [PATCH 05/12] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC Biju
` (5 subsequent siblings)
9 siblings, 1 reply; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document the Renesas RZ/G3L SMARC Carrier-II EVK board which is based on
the Renesas RZ/G3L SMARC SoM. The RZ/G3L SMARC Carrier-II EVK consists of
an RZ/G3L SoM module and a SMARC Carrier-II carrier board. The SoM module
sits on top of the carrier board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index be61a71c7305..201d15dd30f2 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -550,6 +550,10 @@ properties:
- description: RZ/G3L (R9A08G046)
items:
+ - enum:
+ - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
+ - enum:
+ - renesas,rzg3l-smarcm # RZ/G3L SMARC Module (SoM)
- enum:
- renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 (14mm LFBGA)
- renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 (17mm LFBGA)
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* RE: [PATCH 04/12] dt-bindings: soc: renesas: Document RZ/G3L SMARC SoM and Carrier-II EVK
2026-01-20 12:52 ` [PATCH 04/12] dt-bindings: soc: renesas: Document RZ/G3L SMARC SoM and Carrier-II EVK Biju
@ 2026-01-20 17:42 ` Fabrizio Castro
0 siblings, 0 replies; 27+ messages in thread
From: Fabrizio Castro @ 2026-01-20 17:42 UTC (permalink / raw)
To: biju.das.au, Geert Uytterhoeven, magnus.damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Biju Das, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Prabhakar Mahadev Lad, biju.das.au
> From: Biju <biju.das.au@gmail.com>
> Sent: 20 January 2026 12:52
> To: Geert Uytterhoeven <geert+renesas@glider.be>; magnus.damm <magnus.damm@gmail.com>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>
> Cc: Biju Das <biju.das.jz@bp.renesas.com>; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>; biju.das.au <biju.das.au@gmail.com>
> Subject: [PATCH 04/12] dt-bindings: soc: renesas: Document RZ/G3L SMARC SoM and Carrier-II EVK
>
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document the Renesas RZ/G3L SMARC Carrier-II EVK board which is based on
> the Renesas RZ/G3L SMARC SoM. The RZ/G3L SMARC Carrier-II EVK consists of
> an RZ/G3L SoM module and a SMARC Carrier-II carrier board. The SoM module
> sits on top of the carrier board.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> ---
> Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> index be61a71c7305..201d15dd30f2 100644
> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> @@ -550,6 +550,10 @@ properties:
>
> - description: RZ/G3L (R9A08G046)
> items:
> + - enum:
> + - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
> + - enum:
> + - renesas,rzg3l-smarcm # RZ/G3L SMARC Module (SoM)
> - enum:
> - renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 (14mm LFBGA)
> - renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 (17mm LFBGA)
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 05/12] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
` (3 preceding siblings ...)
2026-01-20 12:52 ` [PATCH 04/12] dt-bindings: soc: renesas: Document RZ/G3L SMARC SoM and Carrier-II EVK Biju
@ 2026-01-20 12:52 ` Biju
2026-01-20 19:50 ` Conor Dooley
2026-01-20 12:52 ` [PATCH 07/12] dt-bindings: clock: " Biju
` (4 subsequent siblings)
9 siblings, 1 reply; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the
RZ/G3L SoC is similar to the one found on the RZ/G3S.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml
index 4386b2c3fa4d..94ae72eb8fb6 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml
@@ -24,6 +24,7 @@ properties:
- renesas,r9a07g044-sysc # RZ/G2{L,LC}
- renesas,r9a07g054-sysc # RZ/V2L
- renesas,r9a08g045-sysc # RZ/G3S
+ - renesas,r9a08g046-sysc # RZ/G3L
reg:
maxItems: 1
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 05/12] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC
2026-01-20 12:52 ` [PATCH 05/12] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC Biju
@ 2026-01-20 19:50 ` Conor Dooley
0 siblings, 0 replies; 27+ messages in thread
From: Conor Dooley @ 2026-01-20 19:50 UTC (permalink / raw)
To: Biju
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Biju Das, linux-renesas-soc, devicetree,
linux-kernel, Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 07/12] dt-bindings: clock: Document RZ/G3L SoC
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
` (4 preceding siblings ...)
2026-01-20 12:52 ` [PATCH 05/12] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC Biju
@ 2026-01-20 12:52 ` Biju
2026-01-20 19:51 ` Conor Dooley
2026-01-20 12:52 ` [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for " Biju
` (3 subsequent siblings)
9 siblings, 1 reply; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm
Cc: Biju Das, linux-renesas-soc, linux-clk, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse
Generator (CPG).
Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock, module
clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
Reset definitions referring to registers CPG_RST_* in Section 4.4.3
("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../bindings/clock/renesas,rzg2l-cpg.yaml | 1 +
include/dt-bindings/clock/r9a08g046-cpg.h | 339 ++++++++++++++++++
2 files changed, 340 insertions(+)
create mode 100644 include/dt-bindings/clock/r9a08g046-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index 8c18616e5c4d..318fb91e4f5e 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -28,6 +28,7 @@ properties:
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
- renesas,r9a07g054-cpg # RZ/V2L
- renesas,r9a08g045-cpg # RZ/G3S
+ - renesas,r9a08g046-cpg # RZ/G3L
- renesas,r9a09g011-cpg # RZ/V2M
reg:
diff --git a/include/dt-bindings/clock/r9a08g046-cpg.h b/include/dt-bindings/clock/r9a08g046-cpg.h
new file mode 100644
index 000000000000..d8304a73efdf
--- /dev/null
+++ b/include/dt-bindings/clock/r9a08g046-cpg.h
@@ -0,0 +1,339 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A08G046 CPG Core Clocks */
+#define R9A08G046_CLK_I 0
+#define R9A08G046_CLK_IC0 1
+#define R9A08G046_CLK_IC1 2
+#define R9A08G046_CLK_IC2 3
+#define R9A08G046_CLK_IC3 4
+#define R9A08G046_CLK_P0 5
+#define R9A08G046_CLK_P1 6
+#define R9A08G046_CLK_P2 7
+#define R9A08G046_CLK_P3 8
+#define R9A08G046_CLK_P4 9
+#define R9A08G046_CLK_P5 10
+#define R9A08G046_CLK_P6 11
+#define R9A08G046_CLK_P7 12
+#define R9A08G046_CLK_P8 13
+#define R9A08G046_CLK_P9 14
+#define R9A08G046_CLK_P10 15
+#define R9A08G046_CLK_P13 16
+#define R9A08G046_CLK_P14 17
+#define R9A08G046_CLK_P15 18
+#define R9A08G046_CLK_P16 19
+#define R9A08G046_CLK_P17 20
+#define R9A08G046_CLK_P18 21
+#define R9A08G046_CLK_P19 22
+#define R9A08G046_CLK_P20 23
+#define R9A08G046_CLK_M0 24
+#define R9A08G046_CLK_M1 25
+#define R9A08G046_CLK_M2 26
+#define R9A08G046_CLK_M3 27
+#define R9A08G046_CLK_M4 28
+#define R9A08G046_CLK_M5 29
+#define R9A08G046_CLK_M6 30
+#define R9A08G046_CLK_AT 31
+#define R9A08G046_CLK_B 32
+#define R9A08G046_CLK_ETHTX01 33
+#define R9A08G046_CLK_ETHTX02 34
+#define R9A08G046_CLK_ETHRX01 35
+#define R9A08G046_CLK_ETHRX02 36
+#define R9A08G046_CLK_ETHRM0 37
+#define R9A08G046_CLK_ETHTX11 38
+#define R9A08G046_CLK_ETHTX12 39
+#define R9A08G046_CLK_ETHRX11 40
+#define R9A08G046_CLK_ETHRX12 41
+#define R9A08G046_CLK_ETHRM1 42
+#define R9A08G046_CLK_G 43
+#define R9A08G046_CLK_HP 44
+#define R9A08G046_CLK_SD0 45
+#define R9A08G046_CLK_SD1 46
+#define R9A08G046_CLK_SD2 47
+#define R9A08G046_CLK_SPI0 48
+#define R9A08G046_CLK_SPI1 49
+#define R9A08G046_CLK_S0 50
+#define R9A08G046_CLK_SWD 51
+#define R9A08G046_OSCCLK 52
+#define R9A08G046_OSCCLK2 53
+#define R9A08G046_CLK_P4_DIV2 54
+
+/* R9A08G046 Module Clocks */
+#define R9A08G046_CA55_SCLK 0
+#define R9A08G046_CA55_PCLK 1
+#define R9A08G046_CA55_ATCLK 2
+#define R9A08G046_CA55_GICCLK 3
+#define R9A08G046_CA55_PERICLK 4
+#define R9A08G046_CA55_ACLK 5
+#define R9A08G046_CA55_TSCLK 6
+#define R9A08G046_CA55_CORECLK0 7
+#define R9A08G046_CA55_CORECLK1 8
+#define R9A08G046_CA55_CORECLK2 9
+#define R9A08G046_CA55_CORECLK3 10
+#define R9A08G046_SRAM_ACPU_ACLK0 11
+#define R9A08G046_SRAM_ACPU_ACLK1 12
+#define R9A08G046_SRAM_ACPU_ACLK2 13
+#define R9A08G046_GIC600_GICCLK 14
+#define R9A08G046_IA55_CLK 15
+#define R9A08G046_IA55_PCLK 16
+#define R9A08G046_MHU_PCLK 17
+#define R9A08G046_SYC_CNT_CLK 18
+#define R9A08G046_DMAC_ACLK 19
+#define R9A08G046_DMAC_PCLK 20
+#define R9A08G046_OSTM0_PCLK 21
+#define R9A08G046_OSTM1_PCLK 22
+#define R9A08G046_OSTM2_PCLK 23
+#define R9A08G046_MTU_X_MCK_MTU3 24
+#define R9A08G046_POE3_CLKM_POE 25
+#define R9A08G046_GPT_PCLK 26
+#define R9A08G046_POEG_A_CLKP 27
+#define R9A08G046_POEG_B_CLKP 28
+#define R9A08G046_POEG_C_CLKP 29
+#define R9A08G046_POEG_D_CLKP 30
+#define R9A08G046_WDT0_PCLK 31
+#define R9A08G046_WDT0_CLK 32
+#define R9A08G046_WDT1_PCLK 33
+#define R9A08G046_WDT1_CLK 34
+#define R9A08G046_WDT2_PCLK 35
+#define R9A08G046_WDT2_CLK 36
+#define R9A08G046_XSPI_HCLK 37
+#define R9A08G046_XSPI_ACLK 38
+#define R9A08G046_XSPI_CLK 39
+#define R9A08G046_XSPI_CLKX2 40
+#define R9A08G046_SDHI0_IMCLK 41
+#define R9A08G046_SDHI0_IMCLK2 42
+#define R9A08G046_SDHI0_CLK_HS 43
+#define R9A08G046_SDHI0_IACLKS 44
+#define R9A08G046_SDHI0_IACLKM 45
+#define R9A08G046_SDHI1_IMCLK 46
+#define R9A08G046_SDHI1_IMCLK2 47
+#define R9A08G046_SDHI1_CLK_HS 48
+#define R9A08G046_SDHI1_IACLKS 49
+#define R9A08G046_SDHI1_IACLKM 50
+#define R9A08G046_SDHI2_IMCLK 51
+#define R9A08G046_SDHI2_IMCLK2 52
+#define R9A08G046_SDHI2_CLK_HS 53
+#define R9A08G046_SDHI2_IACLKS 54
+#define R9A08G046_SDHI2_IACLKM 55
+#define R9A08G046_GE3D_CLK 56
+#define R9A08G046_GE3D_AXI_CLK 57
+#define R9A08G046_GE3D_ACE_CLK 58
+#define R9A08G046_ISU_ACLK 59
+#define R9A08G046_ISU_PCLK 60
+#define R9A08G046_H264_CLK_A 61
+#define R9A08G046_H264_CLK_P 62
+#define R9A08G046_CRU_SYSCLK 63
+#define R9A08G046_CRU_VCLK 64
+#define R9A08G046_CRU_PCLK 65
+#define R9A08G046_CRU_ACLK 66
+#define R9A08G046_MIPI_DSI_PLLCLK 67
+#define R9A08G046_MIPI_DSI_SYSCLK 68
+#define R9A08G046_MIPI_DSI_ACLK 69
+#define R9A08G046_MIPI_DSI_PCLK 70
+#define R9A08G046_MIPI_DSI_VCLK 71
+#define R9A08G046_MIPI_DSI_LPCLK 72
+#define R9A08G046_LVDS_PLLCLK 73
+#define R9A08G046_LVDS_CLK_DOT0 74
+#define R9A08G046_LVDS_PCLK 75
+#define R9A08G046_LCDC_CLK_A 76
+#define R9A08G046_LCDC_CLK_D 77
+#define R9A08G046_LCDC_CLK_P 78
+#define R9A08G046_SSI0_PCLK2 79
+#define R9A08G046_SSI0_PCLK_SFR 80
+#define R9A08G046_SSI1_PCLK2 81
+#define R9A08G046_SSI1_PCLK_SFR 82
+#define R9A08G046_SSI2_PCLK2 83
+#define R9A08G046_SSI2_PCLK_SFR 84
+#define R9A08G046_SSI3_PCLK2 85
+#define R9A08G046_SSI3_PCLK_SFR 86
+#define R9A08G046_USB_U2H0_HCLK 87
+#define R9A08G046_USB_U2H1_HCLK 88
+#define R9A08G046_USB_U2P0_EXR_CPUCLK 89
+#define R9A08G046_USB_U2P1_EXR_CPUCLK 90
+#define R9A08G046_USB_PCLK 91
+#define R9A08G046_USB_SCLK 92
+#define R9A08G046_ETH0_CLK_AXI 93
+#define R9A08G046_ETH0_CLK_CHI 94
+#define R9A08G046_ETH0_CLK_TX_I 95
+#define R9A08G046_ETH0_CLK_RX_I 96
+#define R9A08G046_ETH0_CLK_TX_180_I 97
+#define R9A08G046_ETH0_CLK_RX_180_I 98
+#define R9A08G046_ETH0_CLK_RMII_I 99
+#define R9A08G046_ETH0_CLK_PTP_REF_I 100
+#define R9A08G046_ETH1_CLK_AXI 101
+#define R9A08G046_ETH1_CLK_CHI 102
+#define R9A08G046_ETH1_CLK_TX_I 103
+#define R9A08G046_ETH1_CLK_RX_I 104
+#define R9A08G046_ETH1_CLK_TX_180_I 105
+#define R9A08G046_ETH1_CLK_RX_180_I 106
+#define R9A08G046_ETH1_CLK_RMII_I 107
+#define R9A08G046_ETH1_CLK_PTP_REF_I 108
+#define R9A08G046_I2C0_PCLK 109
+#define R9A08G046_I2C1_PCLK 110
+#define R9A08G046_I2C2_PCLK 111
+#define R9A08G046_I2C3_PCLK 112
+#define R9A08G046_SCIF0_CLK_PCK 113
+#define R9A08G046_SCIF1_CLK_PCK 114
+#define R9A08G046_SCIF2_CLK_PCK 115
+#define R9A08G046_SCIF3_CLK_PCK 116
+#define R9A08G046_SCIF4_CLK_PCK 117
+#define R9A08G046_SCIF5_CLK_PCK 118
+#define R9A08G046_RSCI0_PCLK 119
+#define R9A08G046_RSCI0_TCLK 120
+#define R9A08G046_RSCI1_PCLK 121
+#define R9A08G046_RSCI1_TCLK 122
+#define R9A08G046_RSCI2_PCLK 123
+#define R9A08G046_RSCI2_TCLK 124
+#define R9A08G046_RSCI3_PCLK 125
+#define R9A08G046_RSCI3_TCLK 126
+#define R9A08G046_RSPI0_PCLK 127
+#define R9A08G046_RSPI0_TCLK 128
+#define R9A08G046_RSPI1_PCLK 129
+#define R9A08G046_RSPI1_TCLK 130
+#define R9A08G046_RSPI2_PCLK 131
+#define R9A08G046_RSPI2_TCLK 132
+#define R9A08G046_CANFD_PCLK 133
+#define R9A08G046_CANFD_CLK_RAM 134
+#define R9A08G046_GPIO_HCLK 135
+#define R9A08G046_ADC0_ADCLK 136
+#define R9A08G046_ADC0_PCLK 137
+#define R9A08G046_ADC1_ADCLK 138
+#define R9A08G046_ADC1_PCLK 139
+#define R9A08G046_TSU_PCLK 140
+#define R9A08G046_PDM_PCLK 141
+#define R9A08G046_PDM_CCLK 142
+#define R9A08G046_PCI_ACLK 143
+#define R9A08G046_PCI_CLKL1PM 144
+#define R9A08G046_PCI_CLK_PMU 145
+#define R9A08G046_SPDIF_PCLK 146
+#define R9A08G046_I3C_TCLK 147
+#define R9A08G046_I3C_PCLK 148
+#define R9A08G046_VBAT_BCLK 149
+#define R9A08G046_BSC_X_BCK_BSC 150
+
+/* R9A08G046 Resets */
+#define R9A08G046_CA55_RST0_0 0
+#define R9A08G046_CA55_RST0_1 1
+#define R9A08G046_CA55_RST0_2 2
+#define R9A08G046_CA55_RST0_3 3
+#define R9A08G046_CA55_RST4_0 4
+#define R9A08G046_CA55_RST4_1 5
+#define R9A08G046_CA55_RST4_2 6
+#define R9A08G046_CA55_RST4_3 7
+#define R9A08G046_CA55_RST8 8
+#define R9A08G046_CA55_RST9 9
+#define R9A08G046_CA55_RST10 10
+#define R9A08G046_CA55_RST11 11
+#define R9A08G046_CA55_RST12 12
+#define R9A08G046_CA55_RST13 13
+#define R9A08G046_CA55_RST14 14
+#define R9A08G046_CA55_RST15 15
+#define R9A08G046_CA55_RST16 16
+#define R9A08G046_SRAM_ACPU_ARESETN0 17
+#define R9A08G046_SRAM_ACPU_ARESETN1 18
+#define R9A08G046_SRAM_ACPU_ARESETN2 19
+#define R9A08G046_GIC600_GICRESET_N 20
+#define R9A08G046_GIC600_DBG_GICRESET_N 21
+#define R9A08G046_IA55_RESETN 22
+#define R9A08G046_MHU_RESETN 23
+#define R9A08G046_SYC_RESETN 24
+#define R9A08G046_DMAC_ARESETN 25
+#define R9A08G046_DMAC_RST_ASYNC 26
+#define R9A08G046_GTM0_PRESETZ 27
+#define R9A08G046_GTM1_PRESETZ 28
+#define R9A08G046_GTM2_PRESETZ 29
+#define R9A08G046_MTU_X_PRESET_MTU3 30
+#define R9A08G046_POE3_RST_M_REG 31
+#define R9A08G046_GPT_RST_C 32
+#define R9A08G046_POEG_A_RST 33
+#define R9A08G046_POEG_B_RST 34
+#define R9A08G046_POEG_C_RST 35
+#define R9A08G046_POEG_D_RST 36
+#define R9A08G046_WDT0_PRESETN 37
+#define R9A08G046_WDT1_PRESETN 38
+#define R9A08G046_WDT2_PRESETN 39
+#define R9A08G046_XSPI_HRESETN 40
+#define R9A08G046_XSPI_ARESETN 41
+#define R9A08G046_SDHI0_IXRST 42
+#define R9A08G046_SDHI1_IXRST 43
+#define R9A08G046_SDHI2_IXRST 44
+#define R9A08G046_SDHI0_IXRSTAXIM 45
+#define R9A08G046_SDHI0_IXRSTAXIS 46
+#define R9A08G046_SDHI1_IXRSTAXIM 47
+#define R9A08G046_SDHI1_IXRSTAXIS 48
+#define R9A08G046_SDHI2_IXRSTAXIM 49
+#define R9A08G046_SDHI2_IXRSTAXIS 50
+#define R9A08G046_GE3D_RESETN 51
+#define R9A08G046_GE3D_AXI_RESETN 52
+#define R9A08G046_GE3D_ACE_RESETN 53
+#define R9A08G046_ISU_ARESETN 54
+#define R9A08G046_ISU_PRESETN 55
+#define R9A08G046_H264_X_RESET_VCP 56
+#define R9A08G046_H264_CP_PRESET_P 57
+#define R9A08G046_CRU_CMN_RSTB 58
+#define R9A08G046_CRU_PRESETN 59
+#define R9A08G046_CRU_ARESETN 60
+#define R9A08G046_MIPI_DSI_CMN_RSTB 61
+#define R9A08G046_MIPI_DSI_ARESET_N 62
+#define R9A08G046_MIPI_DSI_PRESET_N 63
+#define R9A08G046_LCDC_RESET_N 64
+#define R9A08G046_SSI0_RST_M2_REG 65
+#define R9A08G046_SSI1_RST_M2_REG 66
+#define R9A08G046_SSI2_RST_M2_REG 67
+#define R9A08G046_SSI3_RST_M2_REG 68
+#define R9A08G046_USB_U2H0_HRESETN 69
+#define R9A08G046_USB_U2H1_HRESETN 70
+#define R9A08G046_USB_U2P0_EXL_SYSRST 71
+#define R9A08G046_USB_PRESETN 72
+#define R9A08G046_USB_U2P1_EXL_SYSRST 73
+#define R9A08G046_ETH0_ARESET_N 74
+#define R9A08G046_ETH1_ARESET_N 75
+#define R9A08G046_I2C0_MRST 76
+#define R9A08G046_I2C1_MRST 77
+#define R9A08G046_I2C2_MRST 78
+#define R9A08G046_I2C3_MRST 79
+#define R9A08G046_SCIF0_RST_SYSTEM_N 80
+#define R9A08G046_SCIF1_RST_SYSTEM_N 81
+#define R9A08G046_SCIF2_RST_SYSTEM_N 82
+#define R9A08G046_SCIF3_RST_SYSTEM_N 83
+#define R9A08G046_SCIF4_RST_SYSTEM_N 84
+#define R9A08G046_SCIF5_RST_SYSTEM_N 85
+#define R9A08G046_RSPI0_PRESETN 86
+#define R9A08G046_RSPI1_PRESETN 87
+#define R9A08G046_RSPI2_PRESETN 88
+#define R9A08G046_RSPI0_TRESETN 89
+#define R9A08G046_RSPI1_TRESETN 90
+#define R9A08G046_RSPI2_TRESETN 91
+#define R9A08G046_CANFD_RSTP_N 92
+#define R9A08G046_CANFD_RSTC_N 93
+#define R9A08G046_GPIO_RSTN 94
+#define R9A08G046_GPIO_PORT_RESETN 95
+#define R9A08G046_GPIO_SPARE_RESETN 96
+#define R9A08G046_ADC0_PRESETN 97
+#define R9A08G046_ADC0_ADRST_N 98
+#define R9A08G046_ADC1_PRESETN 99
+#define R9A08G046_ADC1_ADRST_N 100
+#define R9A08G046_TSU_PRESETN 101
+#define R9A08G046_PDM_PRESETN 102
+#define R9A08G046_PCI_ARESETN 103
+#define R9A08G046_SPDIF_RST 104
+#define R9A08G046_I3C_TRESETN 105
+#define R9A08G046_I3C_PRESETN 106
+#define R9A08G046_VBAT_BRESETN 107
+#define R9A08G046_RSCI0_PRESETN 108
+#define R9A08G046_RSCI1_PRESETN 109
+#define R9A08G046_RSCI2_PRESETN 110
+#define R9A08G046_RSCI3_PRESETN 111
+#define R9A08G046_RSCI0_TRESETN 112
+#define R9A08G046_RSCI1_TRESETN 113
+#define R9A08G046_RSCI2_TRESETN 114
+#define R9A08G046_RSCI3_TRESETN 115
+#define R9A08G046_LVDS_RESET_N 116
+
+#endif /* __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__ */
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 07/12] dt-bindings: clock: Document RZ/G3L SoC
2026-01-20 12:52 ` [PATCH 07/12] dt-bindings: clock: " Biju
@ 2026-01-20 19:51 ` Conor Dooley
0 siblings, 0 replies; 27+ messages in thread
From: Conor Dooley @ 2026-01-20 19:51 UTC (permalink / raw)
To: Biju
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Magnus Damm, Biju Das,
linux-renesas-soc, linux-clk, devicetree, linux-kernel,
Prabhakar Mahadev Lad
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
` (5 preceding siblings ...)
2026-01-20 12:52 ` [PATCH 07/12] dt-bindings: clock: " Biju
@ 2026-01-20 12:52 ` Biju
2026-01-21 13:05 ` Geert Uytterhoeven
2026-01-20 12:52 ` [PATCH 10/12] arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM Biju
` (2 subsequent siblings)
9 siblings, 1 reply; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add the initial DTSI for the RZ/G3L SoC.
The files in this commit have the following meaning:
- r9a08g046.dtsi: RZ/G3L family SoC common parts
- r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
Added place holders to reuse the code for Renesas SMARC II carrier
board.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 219 ++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi | 13 ++
2 files changed, 232 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
new file mode 100644
index 000000000000..0619c296a8d0
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -0,0 +1,219 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3L SoC
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r9a08g046-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "renesas,r9a08g046";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ audio_clk1: audio-clk1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it. */
+ clock-frequency = <0>;
+ };
+
+ audio_clk2: audio-clk2 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it. */
+ clock-frequency = <0>;
+ };
+
+ can_clk: can-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by boards that provide it. */
+ clock-frequency = <0>;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ reg = <0>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@100 {
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@200 {
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@300 {
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ device_type = "cpu";
+ next-level-cache = <&L3_CA55>;
+ enable-method = "psci";
+ };
+
+ L3_CA55: cache-controller-0 {
+ compatible = "cache";
+ cache-unified;
+ cache-size = <0x80000>;
+ cache-level = <3>;
+ };
+ };
+
+ extal_clk: extal-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ soc: soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ scif0: serial@100ac000 {
+ compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
+ reg = <0 0x100ac000 0 0x400>;
+ interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "eri", "rxi", "txi",
+ "bri", "dri", "tei";
+ clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
+ clock-names = "fck";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@100ae000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x100AE000 0 0x400>;
+ /* placeholder */
+ };
+
+ canfd: can@100c0000 {
+ reg = <0 0x100c0000 0 0x20000>;
+ /* placeholder */
+ };
+
+ cpg: clock-controller@11010000 {
+ compatible = "renesas,r9a08g046-cpg";
+ reg = <0 0x11010000 0 0x10000>;
+ clocks = <&extal_clk>;
+ clock-names = "extal";
+ #clock-cells = <2>;
+ #reset-cells = <1>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@11020000 {
+ compatible = "renesas,r9a08g046-sysc";
+ reg = <0 0x11020000 0 0x10000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "lpm_int", "ca55stbydone_int",
+ "cm33stbyr_int", "ca55_deny";
+ };
+
+ pinctrl: pinctrl@11030000 {
+ reg = <0 0x11030000 0 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a08g046-dmac", "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A08G046_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A08G046_DMAC_PCLK>;
+ clock-names = "main", "register";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G046_DMAC_ARESETN>,
+ <&cpg R9A08G046_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
+ sdhi1: mmc@11c10000 {
+ reg = <0x0 0x11c10000 0 0x10000>;
+ /* placeholder */
+ };
+
+ gic: interrupt-controller@12400000 {
+ compatible = "arm,gic-v3";
+ reg = <0x0 0x12400000 0 0x20000>,
+ <0x0 0x12440000 0 0x80000>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+ };
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
new file mode 100644
index 000000000000..f6f673abc01b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A08G046L48 SoC specific parts
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a08g046.dtsi"
+
+/ {
+ compatible = "renesas,r9a08g046l48", "renesas,r9a08g046";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
2026-01-20 12:52 ` [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for " Biju
@ 2026-01-21 13:05 ` Geert Uytterhoeven
2026-01-21 13:15 ` Biju Das
0 siblings, 1 reply; 27+ messages in thread
From: Geert Uytterhoeven @ 2026-01-21 13:05 UTC (permalink / raw)
To: Biju
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad
Hi Biju,
On Tue, 20 Jan 2026 at 13:52, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add the initial DTSI for the RZ/G3L SoC.
> The files in this commit have the following meaning:
> - r9a08g046.dtsi: RZ/G3L family SoC common parts
> - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
>
> Added place holders to reuse the code for Renesas SMARC II carrier
> board.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -0,0 +1,219 @@
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + scif0: serial@100ac000 {
> + compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
> + reg = <0 0x100ac000 0 0x400>;
> + interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "eri", "rxi", "txi",
> + "bri", "dri", "tei";
> + clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
> + clock-names = "fck";
> + power-domains = <&cpg>;
> + resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
> + status = "disabled";
> + };
> +
> + i2c0: i2c@100ae000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x100AE000 0 0x400>;
> + /* placeholder */
> + };
> +
> + canfd: can@100c0000 {
> + reg = <0 0x100c0000 0 0x20000>;
> + /* placeholder */
> + };
> +
Early feedback: depending on when this goes upstream, we may
need a few more:
+ ohci0: usb@11e10000 {
+ /* placeholder */
+ };
+
+ ohci1: usb@11e90000 {
+ /* placeholder */
+ };
+
+ ehci0: usb@11e10100 {
+ /* placeholder */
+ };
+
+ ehci1: usb@11e90100 {
+ /* placeholder */
+ };
+
+ hsusb: usb@11e30000 {
+ /* placeholder */
+ };
+
+ pcie: pcie@11e40000 {
+ /* placeholder */
+ };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 27+ messages in thread* RE: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
2026-01-21 13:05 ` Geert Uytterhoeven
@ 2026-01-21 13:15 ` Biju Das
0 siblings, 0 replies; 27+ messages in thread
From: Biju Das @ 2026-01-21 13:15 UTC (permalink / raw)
To: geert, biju.das.au
Cc: magnus.damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 21 January 2026 13:05
> Subject: Re: [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
>
> Hi Biju,
>
> On Tue, 20 Jan 2026 at 13:52, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add the initial DTSI for the RZ/G3L SoC.
> > The files in this commit have the following meaning:
> > - r9a08g046.dtsi: RZ/G3L family SoC common parts
> > - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
> >
> > Added place holders to reuse the code for Renesas SMARC II carrier
> > board.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > @@ -0,0 +1,219 @@
>
> > + soc: soc {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + scif0: serial@100ac000 {
> > + compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
> > + reg = <0 0x100ac000 0 0x400>;
> > + interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "eri", "rxi", "txi",
> > + "bri", "dri", "tei";
> > + clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
> > + clock-names = "fck";
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
> > + status = "disabled";
> > + };
> > +
> > + i2c0: i2c@100ae000 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0 0x100AE000 0 0x400>;
> > + /* placeholder */
> > + };
> > +
> > + canfd: can@100c0000 {
> > + reg = <0 0x100c0000 0 0x20000>;
> > + /* placeholder */
> > + };
> > +
>
> Early feedback: depending on when this goes upstream, we may need a few more:
>
> + ohci0: usb@11e10000 {
> + /* placeholder */
> + };
> +
> + ohci1: usb@11e90000 {
> + /* placeholder */
> + };
> +
> + ehci0: usb@11e10100 {
> + /* placeholder */
> + };
> +
> + ehci1: usb@11e90100 {
> + /* placeholder */
> + };
> +
> + hsusb: usb@11e30000 {
> + /* placeholder */
> + };
> +
> + pcie: pcie@11e40000 {
> + /* placeholder */
> + };
OK, I will keep an eye on these patch series.
Cheers,
Biju
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 10/12] arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
` (6 preceding siblings ...)
2026-01-20 12:52 ` [PATCH 09/12] arm64: dts: renesas: Add initial DTSI for " Biju
@ 2026-01-20 12:52 ` Biju
2026-01-21 12:25 ` Biju Das
2026-01-20 12:52 ` [PATCH 11/12] arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS Biju
2026-01-20 12:52 ` [PATCH 12/12] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board Biju
9 siblings, 1 reply; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add initial support for the RZ/G3L SMARC SoM with 2GB memory and
extal clk.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
.../boot/dts/renesas/rzg3l-smarc-som.dtsi | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
new file mode 100644
index 000000000000..7a3a2d4ab037
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for R9A08G046L48 SMARC SoM board.
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046";
+
+ memory@48000000 {
+ device_type = "memory";
+ /* First 128MB is reserved for secure area. */
+ reg = <0x0 0x48000000 0x0 0x78000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <24000000>;
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* RE: [PATCH 10/12] arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
2026-01-20 12:52 ` [PATCH 10/12] arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM Biju
@ 2026-01-21 12:25 ` Biju Das
0 siblings, 0 replies; 27+ messages in thread
From: Biju Das @ 2026-01-21 12:25 UTC (permalink / raw)
To: biju.das.au, Geert Uytterhoeven, magnus.damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad, biju.das.au
Hi All,
> -----Original Message-----
> From: Biju <biju.das.au@gmail.com>
> Sent: 20 January 2026 12:52
> Subject: [PATCH 10/12] arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
>
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add initial support for the RZ/G3L SMARC SoM with 2GB memory and extal clk.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 22 +++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
>
> diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-
> smarc-som.dtsi
> new file mode 100644
> index 000000000000..7a3a2d4ab037
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for R9A08G046L48 SMARC SoM board.
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
Will drop this header file in v2.
Cheers,
Biju
> +
> +/ {
> + compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48",
> +"renesas,r9a08g046";
> +
> + memory@48000000 {
> + device_type = "memory";
> + /* First 128MB is reserved for secure area. */
> + reg = <0x0 0x48000000 0x0 0x78000000>;
> + };
> +};
> +
> +&extal_clk {
> + clock-frequency = <24000000>;
> +};
> --
> 2.43.0
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 11/12] arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
` (7 preceding siblings ...)
2026-01-20 12:52 ` [PATCH 10/12] arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM Biju
@ 2026-01-20 12:52 ` Biju
2026-01-20 12:52 ` [PATCH 12/12] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board Biju
9 siblings, 0 replies; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
SMARC2 board dtsi is common for multiple SoCs. So move usb3 nodes
to board DTS as some SOCs (eg: RZ/G3{S,L}) does not support USB3.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 6 ++++++
arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi | 8 --------
2 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 696903dc7a63..cc75f6fdf7f5 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -248,7 +248,13 @@ &sdhi1 {
vqmmc-supply = <&vqmmc_sd1_pvdd>;
};
+&usb3_phy {
+ status = "okay";
+};
+
&xhci {
pinctrl-0 = <&usb3_pins>;
pinctrl-names = "default";
+
+ status = "okay";
};
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index b607b5d6c259..69c0101ff7f5 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -107,11 +107,3 @@ &sdhi1 {
status = "okay";
};
-
-&usb3_phy {
- status = "okay";
-};
-
-&xhci {
- status = "okay";
-};
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH 12/12] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board
2026-01-20 12:52 [PATCH 00/12] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform Biju
` (8 preceding siblings ...)
2026-01-20 12:52 ` [PATCH 11/12] arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS Biju
@ 2026-01-20 12:52 ` Biju
2026-01-26 20:48 ` Biju Das
9 siblings, 1 reply; 27+ messages in thread
From: Biju @ 2026-01-20 12:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Biju Das, linux-renesas-soc, devicetree, linux-kernel,
Prabhakar Mahadev Lad, Biju Das
From: Biju Das <biju.das.jz@bp.renesas.com>
Add the initial device tree for the Renesas RZ/G3L SMARC EVK board.
Added placeholders to avoid compilation error with the common code in
renesas-smarc2.dtsi.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/Makefile | 2 +
.../boot/dts/renesas/r9a08g046l48-smarc.dts | 41 +++++++++++++++++++
2 files changed, 43 insertions(+)
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 1fab1b50f20e..0153e772c231 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -179,6 +179,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo
r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo
dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
+dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc.dtb
+
dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
new file mode 100644
index 000000000000..988b1f96228f
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3L SMARC EVK board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/* Add place holder to avoid compilation error with renesas-smarc2.dtsi */
+#define KEY_1_GPIO 1
+#define KEY_2_GPIO 2
+#define KEY_3_GPIO 3
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "r9a08g046l48.dtsi"
+#include "rzg3l-smarc-som.dtsi"
+#include "renesas-smarc2.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK version 2 based on r9a08g046l48";
+ compatible = "renesas,smarc2-evk", "renesas,rzg3l-smarcm",
+ "renesas,r9a08g046l48", "renesas,r9a08g046";
+
+ aliases {
+ serial3 = &scif0;
+ };
+};
+
+&keys {
+ status = "disabled";
+
+ /delete-node/ key-1;
+ /delete-node/ key-2;
+ /delete-node/ key-3;
+};
+
+&scif0 {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related [flat|nested] 27+ messages in thread* RE: [PATCH 12/12] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board
2026-01-20 12:52 ` [PATCH 12/12] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board Biju
@ 2026-01-26 20:48 ` Biju Das
0 siblings, 0 replies; 27+ messages in thread
From: Biju Das @ 2026-01-26 20:48 UTC (permalink / raw)
To: biju.das.au, Geert Uytterhoeven, magnus.damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad, biju.das.au
Hi All,
> -----Original Message-----
> From: Biju <biju.das.au@gmail.com>
> Sent: 20 January 2026 12:52
> Subject: [PATCH 12/12] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board
>
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add the initial device tree for the Renesas RZ/G3L SMARC EVK board.
>
> Added placeholders to avoid compilation error with the common code in renesas-smarc2.dtsi.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> arch/arm64/boot/dts/renesas/Makefile | 2 +
> .../boot/dts/renesas/r9a08g046l48-smarc.dts | 41 +++++++++++++++++++
> 2 files changed, 43 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
>
> diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
> index 1fab1b50f20e..0153e772c231 100644
> --- a/arch/arm64/boot/dts/renesas/Makefile
> +++ b/arch/arm64/boot/dts/renesas/Makefile
> @@ -179,6 +179,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo
> r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo
> dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
>
> +dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc.dtb
> +
> dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
>
> dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb diff --git
> a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-
> smarc.dts
> new file mode 100644
> index 000000000000..988b1f96228f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
> @@ -0,0 +1,41 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/G3L SMARC EVK board
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +/dts-v1/;
> +
> +/* Add place holder to avoid compilation error with renesas-smarc2.dtsi */
> +#define KEY_1_GPIO 1
> +#define KEY_2_GPIO 2
> +#define KEY_3_GPIO 3
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "r9a08g046l48.dtsi"
> +#include "rzg3l-smarc-som.dtsi"
> +#include "renesas-smarc2.dtsi"
> +
> +/ {
> + model = "Renesas SMARC EVK version 2 based on r9a08g046l48";
> + compatible = "renesas,smarc2-evk", "renesas,rzg3l-smarcm",
> + "renesas,r9a08g046l48", "renesas,r9a08g046";
> +
> + aliases {
> + serial3 = &scif0;
> + };
> +};
> +
> +&keys {
> + status = "disabled";
> +
> + /delete-node/ key-1;
> + /delete-node/ key-2;
> + /delete-node/ key-3;
> +};
> +
> +&scif0 {
> + status = "okay";
> +};
I will drop this node in next version as it is enabled in renesas-smarc.dtsi
Cheers,
Biju
> --
> 2.43.0
^ permalink raw reply [flat|nested] 27+ messages in thread