[PATCH v3 00/10] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform

[PATCH v3 00/10] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Hi all,

This patch series adds initial support for the Renesas RZ/G3L SoC and
RZ/G3L SMARC EVK platform. The RZ/G3L device is a general-purpose
microprocessor with a quad-core CA-55, single core CM-33, Mali-G31
3-D Graphics and other peripherals.

Support for the below list of blocks is added in the SoC DTSI (r9a08g046.dtsi):

 - EXT CLK
 - 4X CA55
 - SCIF
 - CPG
 - GIC
 - ARMv8 Timer

This series also adds SCIF support for the RZ/G3L SMARC EVK board (r9a08g046l48-smarc.dts).

v2->v3:
 * Added macros R9A08G046_ETH{0,1}_CLK_{TX,RX}_I_RMII in r9a08g046-cpg.h.
 * Keep the tag from Conor as it is trivial change for just adding macros.
v1->v2:
 * Dropped scif bindings patch as it is accepted.
 * Collected tags.
 * Squashed the patch#3 and #4
 * Documented GE3D/VCP for all SoC variants
 * Documented external ethernet clocks as it is a clock source for MUX
   inside CPG
 * Updated commit description for bindings.
 * Keep the tag from Conor as it is trivial change for adding more
   clks.
 * Added CLK_ETH{0,1}_TXC_TX_CLK_IN and CLK_ETH{0,1}_RXC_RX_CLK_IN clocks
   in clk table.
 * Dropped R9A08G046_IA55_PCLK from critical clock list.
 * Added external clocks eth{0,1}_txc_tx_clk and eth{0,1}_rxc_rx_clk
   in soc dtsi as it needed for cpg as it is a clock source for mux.
 * Updated cpg node.
 * Dropped gpio.h header from SoM dtsi.
 * Dropped scif node as it is already included in common platform
   file.

Test logs:
/ # uname -r
6.19.0-rc8-next-20260202-g61054f67d824
/ # cat /proc/cpuinfo
processor       : 0
BogoMIPS        : 48.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 1
BogoMIPS        : 48.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 2
BogoMIPS        : 48.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

processor       : 3
BogoMIPS        : 48.00
Features        : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant     : 0x2
CPU part        : 0xd05
CPU revision    : 0

/ # cat /proc/interrupts
           CPU0       CPU1       CPU2       CPU3
 11:        271        105        273         62    GICv3  27 Level     arch_timer
 14:          0          0          0          0    GICv3 185 Edge      error
 15:          0          0          0          0    GICv3 186 Edge      11820000.dma-controller:0
 16:          0          0          0          0    GICv3 187 Edge      11820000.dma-controller:1
 17:          0          0          0          0    GICv3 188 Edge      11820000.dma-controller:2
 18:          0          0          0          0    GICv3 189 Edge      11820000.dma-controller:3
 19:          0          0          0          0    GICv3 190 Edge      11820000.dma-controller:4
 20:          0          0          0          0    GICv3 191 Edge      11820000.dma-controller:5
 21:          0          0          0          0    GICv3 192 Edge      11820000.dma-controller:6
 22:          0          0          0          0    GICv3 193 Edge      11820000.dma-controller:7
 23:          0          0          0          0    GICv3 194 Edge      11820000.dma-controller:8
 24:          0          0          0          0    GICv3 195 Edge      11820000.dma-controller:9
 25:          0          0          0          0    GICv3 196 Edge      11820000.dma-controller:10
 26:          0          0          0          0    GICv3 197 Edge      11820000.dma-controller:11
 27:          0          0          0          0    GICv3 198 Edge      11820000.dma-controller:12
 28:          0          0          0          0    GICv3 199 Edge      11820000.dma-controller:13
 29:          0          0          0          0    GICv3 200 Edge      11820000.dma-controller:14
 30:          0          0          0          0    GICv3 201 Edge      11820000.dma-controller:15
 31:          0          0          0          0    GICv3 418 Level     100ac000.serial:rx err
 32:          4          0          0          0    GICv3 420 Level     100ac000.serial:rx full
 33:        222          0          0          0    GICv3 421 Level     100ac000.serial:tx empty
 34:          0          0          0          0    GICv3 419 Level     100ac000.serial:break
 35:         13          0          0          0    GICv3 422 Level     100ac000.serial:rx ready
IPI0:        20          9         37         20       Rescheduling interrupts
IPI1:       238        226        223        248       Function call interrupts
IPI2:         0          0          0          0       CPU stop interrupts
IPI3:         0          0          0          0       CPU stop NMIs
IPI4:         0          0          0          0       Timer broadcast interrupts
IPI5:         0          0          0          0       IRQ work interrupts
IPI6:         0          0          0          0       CPU backtrace interrupts
IPI7:         0          0          0          0       KGDB roundup interrupts
Err:          0
/ # cat /proc/meminfo
MemTotal:        1887812 kB
MemFree:         1848236 kB
MemAvailable:    1815628 kB
/ # cat /sys/devices/soc0/family
RZ/G3L
/ # cat /sys/devices/soc0/machine
Renesas SMARC EVK version 2 based on r9a08g046l48
/ # cat /sys/devices/soc0/soc_id
r9a08g046
/ # cat /sys/devices/soc0/revision
0
/ # dmesg | grep r9a
[    0.000000] Machine model: Renesas SMARC EVK version 2 based on r9a08g046l48
[    0.039307] renesas-rz-sysc 11020000.system-controller: Detected Renesas RZ/G3L r9a08g046 Rev 0

Biju Das (10):
  dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
  dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and
    Carrier-II EVK
  dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC
  soc: renesas: rz-sysc: Add SoC identification for RZ/G3L SoC
  dt-bindings: clock: Document RZ/G3L SoC
  clk: renesas: Add support for RZ/G3L SoC
  arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
  arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM
  arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
  arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK
    board

 .../bindings/clock/renesas,rzg2l-cpg.yaml     |  40 +-
 .../bindings/dma/renesas,rz-dmac.yaml         |   1 +
 .../soc/renesas/renesas,rzg2l-sysc.yaml       |   1 +
 .../bindings/soc/renesas/renesas.yaml         |  13 +
 arch/arm64/boot/dts/renesas/Makefile          |   2 +
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 251 +++++++++++++
 .../boot/dts/renesas/r9a08g046l48-smarc.dts   |  37 ++
 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi |  13 +
 .../boot/dts/renesas/r9a09g047e57-smarc.dts   |   6 +
 .../boot/dts/renesas/renesas-smarc2.dtsi      |   8 -
 .../boot/dts/renesas/rzg3l-smarc-som.dtsi     |  20 +
 drivers/clk/renesas/Kconfig                   |   7 +-
 drivers/clk/renesas/Makefile                  |   1 +
 drivers/clk/renesas/r9a08g046-cpg.c           | 144 ++++++++
 drivers/clk/renesas/rzg2l-cpg.c               |   6 +
 drivers/clk/renesas/rzg2l-cpg.h               |   1 +
 drivers/soc/renesas/Kconfig                   |  12 +
 drivers/soc/renesas/Makefile                  |   1 +
 drivers/soc/renesas/r9a08g046-sysc.c          |  91 +++++
 drivers/soc/renesas/rz-sysc.c                 |   3 +
 drivers/soc/renesas/rz-sysc.h                 |   1 +
 include/dt-bindings/clock/r9a08g046-cpg.h     | 343 ++++++++++++++++++
 22 files changed, 988 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
 create mode 100644 drivers/clk/renesas/r9a08g046-cpg.c
 create mode 100644 drivers/soc/renesas/r9a08g046-sysc.c
 create mode 100644 include/dt-bindings/clock/r9a08g046-cpg.h

-- 
2.43.0

[PATCH v3 01/10] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document the Renesas RZ/G3L DMAC block. This is identical to the one found
on the RZ/G3S SoC.

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Collected tags.
---
 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index d137b9cbaee9..e3311029eb2f 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -19,6 +19,7 @@ properties:
               - renesas,r9a07g044-dmac # RZ/G2{L,LC}
               - renesas,r9a07g054-dmac # RZ/V2L
               - renesas,r9a08g045-dmac # RZ/G3S
+              - renesas,r9a08g046-dmac # RZ/G3L
           - const: renesas,rz-dmac
 
       - items:
-- 
2.43.0

[PATCH v3 02/10] dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and Carrier-II EVK

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document Renesas RZ/G3L (R9A08G046) SoC variants and the Renesas RZ/G3L
SMARC Carrier-II EVK board which is based on the Renesas RZ/G3L SMARC SoM.
The RZ/G3L SMARC Carrier-II EVK consists of an RZ/G3L SoM module and a
SMARC Carrier-II carrier board. The SoM module sits on top of the carrier
board.

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Squashed the patch#3 and #4
 * Documented GE3D/VCP for all SoC variants
 * Collected tag
---
 .../devicetree/bindings/soc/renesas/renesas.yaml    | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index f4947ac65460..5c22c51b1533 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -548,6 +548,19 @@ properties:
           - const: renesas,r9a08g045s33 # PCIe support
           - const: renesas,r9a08g045
 
+      - description: RZ/G3L (R9A08G046)
+        items:
+          - enum:
+              - renesas,smarc2-evk # RZ SMARC Carrier-II EVK
+          - enum:
+              - renesas,rzg3l-smarcm # RZ/G3L SMARC Module (SoM)
+          - enum:
+              - renesas,r9a08g046l26 # Dual Cortex-A55 + Cortex-M33 + GE3D/VCP (14mm LFBGA)
+              - renesas,r9a08g046l28 # Dual Cortex-A55 + Cortex-M33 + GE3D/VCP (17mm LFBGA)
+              - renesas,r9a08g046l46 # Quad Cortex-A55 + Cortex-M33 + GE3D/VCP (14mm LFBGA)
+              - renesas,r9a08g046l48 # Quad Cortex-A55 + Cortex-M33 + GE3D/VCP (17mm LFBGA)
+          - const: renesas,r9a08g046
+
       - description: RZ/V2M (R9A09G011)
         items:
           - enum:
-- 
2.43.0

[PATCH v3 03/10] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the
RZ/G3L SoC is similar to the one found on the RZ/G3S.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Collected tag.
---
 .../devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml      | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml
index 4386b2c3fa4d..94ae72eb8fb6 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzg2l-sysc.yaml
@@ -24,6 +24,7 @@ properties:
       - renesas,r9a07g044-sysc # RZ/G2{L,LC}
       - renesas,r9a07g054-sysc # RZ/V2L
       - renesas,r9a08g045-sysc # RZ/G3S
+      - renesas,r9a08g046-sysc # RZ/G3L
 
   reg:
     maxItems: 1
-- 
2.43.0

[PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse
Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5 clocks
compared to 1 clock on other SoCs.

Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock, module
clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
Reset definitions referring to registers CPG_RST_* in Section 4.4.3
("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * Added macros R9A08G046_ETH{0,1}_CLK_{TX,RX}_I_RMII.
 * Keep the tag from Conor as it is trivial change for just adding macros.
v1->v2:
 * Documented external ethernet clocks as it is a clock source for MUX
   inside CPG
 * Updated commit description.
 * Keep the tag from Conor as it is trivial change for adding more
   clks.
---
 .../bindings/clock/renesas,rzg2l-cpg.yaml     |  40 +-
 include/dt-bindings/clock/r9a08g046-cpg.h     | 343 ++++++++++++++++++
 2 files changed, 378 insertions(+), 5 deletions(-)
 create mode 100644 include/dt-bindings/clock/r9a08g046-cpg.h

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
index 8c18616e5c4d..c0ce687d83ee 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
@@ -28,19 +28,30 @@ properties:
       - renesas,r9a07g044-cpg # RZ/G2{L,LC}
       - renesas,r9a07g054-cpg # RZ/V2L
       - renesas,r9a08g045-cpg # RZ/G3S
+      - renesas,r9a08g046-cpg # RZ/G3L
       - renesas,r9a09g011-cpg # RZ/V2M
 
   reg:
     maxItems: 1
 
   clocks:
-    maxItems: 1
+    minItems: 1
+    items:
+      - description: Clock source to CPG can be either from external clock
+                     input (EXCLK) or crystal oscillator (XIN/XOUT).
+      - description: ETH0 TXC clock input
+      - description: ETH0 RXC clock input
+      - description: ETH1 TXC clock input
+      - description: ETH1 RXC clock input
 
   clock-names:
-    description:
-      Clock source to CPG can be either from external clock input (EXCLK) or
-      crystal oscillator (XIN/XOUT).
-    const: extal
+    minItems: 1
+    items:
+      - const: extal
+      - const: eth0_txc_tx_clk
+      - const: eth0_rxc_rx_clk
+      - const: eth1_txc_tx_clk
+      - const: eth1_rxc_rx_clk
 
   '#clock-cells':
     description: |
@@ -74,6 +85,25 @@ required:
   - '#power-domain-cells'
   - '#reset-cells'
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g046-cpg
+    then:
+      properties:
+        clocks:
+          minItems: 5
+        clock-names:
+          minItems: 5
+    else:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names:
+          maxItems: 1
+
 additionalProperties: false
 
 examples:
diff --git a/include/dt-bindings/clock/r9a08g046-cpg.h b/include/dt-bindings/clock/r9a08g046-cpg.h
new file mode 100644
index 000000000000..ca484e065bbe
--- /dev/null
+++ b/include/dt-bindings/clock/r9a08g046-cpg.h
@@ -0,0 +1,343 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
+#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* R9A08G046 CPG Core Clocks */
+#define R9A08G046_CLK_I			0
+#define R9A08G046_CLK_IC0		1
+#define R9A08G046_CLK_IC1		2
+#define R9A08G046_CLK_IC2		3
+#define R9A08G046_CLK_IC3		4
+#define R9A08G046_CLK_P0		5
+#define R9A08G046_CLK_P1		6
+#define R9A08G046_CLK_P2		7
+#define R9A08G046_CLK_P3		8
+#define R9A08G046_CLK_P4		9
+#define R9A08G046_CLK_P5		10
+#define R9A08G046_CLK_P6		11
+#define R9A08G046_CLK_P7		12
+#define R9A08G046_CLK_P8		13
+#define R9A08G046_CLK_P9		14
+#define R9A08G046_CLK_P10		15
+#define R9A08G046_CLK_P13		16
+#define R9A08G046_CLK_P14		17
+#define R9A08G046_CLK_P15		18
+#define R9A08G046_CLK_P16		19
+#define R9A08G046_CLK_P17		20
+#define R9A08G046_CLK_P18		21
+#define R9A08G046_CLK_P19		22
+#define R9A08G046_CLK_P20		23
+#define R9A08G046_CLK_M0		24
+#define R9A08G046_CLK_M1		25
+#define R9A08G046_CLK_M2		26
+#define R9A08G046_CLK_M3		27
+#define R9A08G046_CLK_M4		28
+#define R9A08G046_CLK_M5		29
+#define R9A08G046_CLK_M6		30
+#define R9A08G046_CLK_AT		31
+#define R9A08G046_CLK_B			32
+#define R9A08G046_CLK_ETHTX01		33
+#define R9A08G046_CLK_ETHTX02		34
+#define R9A08G046_CLK_ETHRX01		35
+#define R9A08G046_CLK_ETHRX02		36
+#define R9A08G046_CLK_ETHRM0		37
+#define R9A08G046_CLK_ETHTX11		38
+#define R9A08G046_CLK_ETHTX12		39
+#define R9A08G046_CLK_ETHRX11		40
+#define R9A08G046_CLK_ETHRX12		41
+#define R9A08G046_CLK_ETHRM1		42
+#define R9A08G046_CLK_G			43
+#define R9A08G046_CLK_HP		44
+#define R9A08G046_CLK_SD0		45
+#define R9A08G046_CLK_SD1		46
+#define R9A08G046_CLK_SD2		47
+#define R9A08G046_CLK_SPI0		48
+#define R9A08G046_CLK_SPI1		49
+#define R9A08G046_CLK_S0		50
+#define R9A08G046_CLK_SWD		51
+#define R9A08G046_OSCCLK		52
+#define R9A08G046_OSCCLK2		53
+#define R9A08G046_CLK_P4_DIV2		54
+
+/* R9A08G046 Module Clocks */
+#define R9A08G046_CA55_SCLK		0
+#define R9A08G046_CA55_PCLK		1
+#define R9A08G046_CA55_ATCLK		2
+#define R9A08G046_CA55_GICCLK		3
+#define R9A08G046_CA55_PERICLK		4
+#define R9A08G046_CA55_ACLK		5
+#define R9A08G046_CA55_TSCLK		6
+#define R9A08G046_CA55_CORECLK0		7
+#define R9A08G046_CA55_CORECLK1		8
+#define R9A08G046_CA55_CORECLK2		9
+#define R9A08G046_CA55_CORECLK3		10
+#define R9A08G046_SRAM_ACPU_ACLK0	11
+#define R9A08G046_SRAM_ACPU_ACLK1	12
+#define R9A08G046_SRAM_ACPU_ACLK2	13
+#define R9A08G046_GIC600_GICCLK		14
+#define R9A08G046_IA55_CLK		15
+#define R9A08G046_IA55_PCLK		16
+#define R9A08G046_MHU_PCLK		17
+#define R9A08G046_SYC_CNT_CLK		18
+#define R9A08G046_DMAC_ACLK		19
+#define R9A08G046_DMAC_PCLK		20
+#define R9A08G046_OSTM0_PCLK		21
+#define R9A08G046_OSTM1_PCLK		22
+#define R9A08G046_OSTM2_PCLK		23
+#define R9A08G046_MTU_X_MCK_MTU3	24
+#define R9A08G046_POE3_CLKM_POE		25
+#define R9A08G046_GPT_PCLK		26
+#define R9A08G046_POEG_A_CLKP		27
+#define R9A08G046_POEG_B_CLKP		28
+#define R9A08G046_POEG_C_CLKP		29
+#define R9A08G046_POEG_D_CLKP		30
+#define R9A08G046_WDT0_PCLK		31
+#define R9A08G046_WDT0_CLK		32
+#define R9A08G046_WDT1_PCLK		33
+#define R9A08G046_WDT1_CLK		34
+#define R9A08G046_WDT2_PCLK		35
+#define R9A08G046_WDT2_CLK		36
+#define R9A08G046_XSPI_HCLK		37
+#define R9A08G046_XSPI_ACLK		38
+#define R9A08G046_XSPI_CLK		39
+#define R9A08G046_XSPI_CLKX2		40
+#define R9A08G046_SDHI0_IMCLK		41
+#define R9A08G046_SDHI0_IMCLK2		42
+#define R9A08G046_SDHI0_CLK_HS		43
+#define R9A08G046_SDHI0_IACLKS		44
+#define R9A08G046_SDHI0_IACLKM		45
+#define R9A08G046_SDHI1_IMCLK		46
+#define R9A08G046_SDHI1_IMCLK2		47
+#define R9A08G046_SDHI1_CLK_HS		48
+#define R9A08G046_SDHI1_IACLKS		49
+#define R9A08G046_SDHI1_IACLKM		50
+#define R9A08G046_SDHI2_IMCLK		51
+#define R9A08G046_SDHI2_IMCLK2		52
+#define R9A08G046_SDHI2_CLK_HS		53
+#define R9A08G046_SDHI2_IACLKS		54
+#define R9A08G046_SDHI2_IACLKM		55
+#define R9A08G046_GE3D_CLK		56
+#define R9A08G046_GE3D_AXI_CLK		57
+#define R9A08G046_GE3D_ACE_CLK		58
+#define R9A08G046_ISU_ACLK		59
+#define R9A08G046_ISU_PCLK		60
+#define R9A08G046_H264_CLK_A		61
+#define R9A08G046_H264_CLK_P		62
+#define R9A08G046_CRU_SYSCLK		63
+#define R9A08G046_CRU_VCLK		64
+#define R9A08G046_CRU_PCLK		65
+#define R9A08G046_CRU_ACLK		66
+#define R9A08G046_MIPI_DSI_PLLCLK	67
+#define R9A08G046_MIPI_DSI_SYSCLK	68
+#define R9A08G046_MIPI_DSI_ACLK		69
+#define R9A08G046_MIPI_DSI_PCLK		70
+#define R9A08G046_MIPI_DSI_VCLK		71
+#define R9A08G046_MIPI_DSI_LPCLK	72
+#define R9A08G046_LVDS_PLLCLK		73
+#define R9A08G046_LVDS_CLK_DOT0		74
+#define R9A08G046_LVDS_PCLK		75
+#define R9A08G046_LCDC_CLK_A		76
+#define R9A08G046_LCDC_CLK_D		77
+#define R9A08G046_LCDC_CLK_P		78
+#define R9A08G046_SSI0_PCLK2		79
+#define R9A08G046_SSI0_PCLK_SFR		80
+#define R9A08G046_SSI1_PCLK2		81
+#define R9A08G046_SSI1_PCLK_SFR		82
+#define R9A08G046_SSI2_PCLK2		83
+#define R9A08G046_SSI2_PCLK_SFR		84
+#define R9A08G046_SSI3_PCLK2		85
+#define R9A08G046_SSI3_PCLK_SFR		86
+#define R9A08G046_USB_U2H0_HCLK		87
+#define R9A08G046_USB_U2H1_HCLK		88
+#define R9A08G046_USB_U2P0_EXR_CPUCLK	89
+#define R9A08G046_USB_U2P1_EXR_CPUCLK	90
+#define R9A08G046_USB_PCLK		91
+#define R9A08G046_USB_SCLK		92
+#define R9A08G046_ETH0_CLK_AXI		93
+#define R9A08G046_ETH0_CLK_CHI		94
+#define R9A08G046_ETH0_CLK_TX_I		95
+#define R9A08G046_ETH0_CLK_RX_I		96
+#define R9A08G046_ETH0_CLK_TX_180_I	97
+#define R9A08G046_ETH0_CLK_RX_180_I	98
+#define R9A08G046_ETH0_CLK_RMII_I	99
+#define R9A08G046_ETH0_CLK_PTP_REF_I	100
+#define R9A08G046_ETH0_CLK_TX_I_RMII	101
+#define R9A08G046_ETH0_CLK_RX_I_RMII	102
+#define R9A08G046_ETH1_CLK_AXI		103
+#define R9A08G046_ETH1_CLK_CHI		104
+#define R9A08G046_ETH1_CLK_TX_I		105
+#define R9A08G046_ETH1_CLK_RX_I		106
+#define R9A08G046_ETH1_CLK_TX_180_I	107
+#define R9A08G046_ETH1_CLK_RX_180_I	108
+#define R9A08G046_ETH1_CLK_RMII_I	109
+#define R9A08G046_ETH1_CLK_PTP_REF_I	110
+#define R9A08G046_ETH1_CLK_TX_I_RMII	111
+#define R9A08G046_ETH1_CLK_RX_I_RMII	112
+#define R9A08G046_I2C0_PCLK		113
+#define R9A08G046_I2C1_PCLK		114
+#define R9A08G046_I2C2_PCLK		115
+#define R9A08G046_I2C3_PCLK		116
+#define R9A08G046_SCIF0_CLK_PCK		117
+#define R9A08G046_SCIF1_CLK_PCK		118
+#define R9A08G046_SCIF2_CLK_PCK		119
+#define R9A08G046_SCIF3_CLK_PCK		120
+#define R9A08G046_SCIF4_CLK_PCK		121
+#define R9A08G046_SCIF5_CLK_PCK		122
+#define R9A08G046_RSCI0_PCLK		123
+#define R9A08G046_RSCI0_TCLK		124
+#define R9A08G046_RSCI1_PCLK		125
+#define R9A08G046_RSCI1_TCLK		126
+#define R9A08G046_RSCI2_PCLK		127
+#define R9A08G046_RSCI2_TCLK		128
+#define R9A08G046_RSCI3_PCLK		129
+#define R9A08G046_RSCI3_TCLK		130
+#define R9A08G046_RSPI0_PCLK		131
+#define R9A08G046_RSPI0_TCLK		132
+#define R9A08G046_RSPI1_PCLK		133
+#define R9A08G046_RSPI1_TCLK		134
+#define R9A08G046_RSPI2_PCLK		135
+#define R9A08G046_RSPI2_TCLK		136
+#define R9A08G046_CANFD_PCLK		137
+#define R9A08G046_CANFD_CLK_RAM		138
+#define R9A08G046_GPIO_HCLK		139
+#define R9A08G046_ADC0_ADCLK		140
+#define R9A08G046_ADC0_PCLK		141
+#define R9A08G046_ADC1_ADCLK		142
+#define R9A08G046_ADC1_PCLK		143
+#define R9A08G046_TSU_PCLK		144
+#define R9A08G046_PDM_PCLK		145
+#define R9A08G046_PDM_CCLK		146
+#define R9A08G046_PCI_ACLK		147
+#define R9A08G046_PCI_CLKL1PM		148
+#define R9A08G046_PCI_CLK_PMU		149
+#define R9A08G046_SPDIF_PCLK		150
+#define R9A08G046_I3C_TCLK		151
+#define R9A08G046_I3C_PCLK		152
+#define R9A08G046_VBAT_BCLK		153
+#define R9A08G046_BSC_X_BCK_BSC		154
+
+/* R9A08G046 Resets */
+#define R9A08G046_CA55_RST0_0		0
+#define R9A08G046_CA55_RST0_1		1
+#define R9A08G046_CA55_RST0_2		2
+#define R9A08G046_CA55_RST0_3		3
+#define R9A08G046_CA55_RST4_0		4
+#define R9A08G046_CA55_RST4_1		5
+#define R9A08G046_CA55_RST4_2		6
+#define R9A08G046_CA55_RST4_3		7
+#define R9A08G046_CA55_RST8		8
+#define R9A08G046_CA55_RST9		9
+#define R9A08G046_CA55_RST10		10
+#define R9A08G046_CA55_RST11		11
+#define R9A08G046_CA55_RST12		12
+#define R9A08G046_CA55_RST13		13
+#define R9A08G046_CA55_RST14		14
+#define R9A08G046_CA55_RST15		15
+#define R9A08G046_CA55_RST16		16
+#define R9A08G046_SRAM_ACPU_ARESETN0	17
+#define R9A08G046_SRAM_ACPU_ARESETN1	18
+#define R9A08G046_SRAM_ACPU_ARESETN2	19
+#define R9A08G046_GIC600_GICRESET_N	20
+#define R9A08G046_GIC600_DBG_GICRESET_N	21
+#define R9A08G046_IA55_RESETN		22
+#define R9A08G046_MHU_RESETN		23
+#define R9A08G046_SYC_RESETN		24
+#define R9A08G046_DMAC_ARESETN		25
+#define R9A08G046_DMAC_RST_ASYNC	26
+#define R9A08G046_GTM0_PRESETZ		27
+#define R9A08G046_GTM1_PRESETZ		28
+#define R9A08G046_GTM2_PRESETZ		29
+#define R9A08G046_MTU_X_PRESET_MTU3	30
+#define R9A08G046_POE3_RST_M_REG	31
+#define R9A08G046_GPT_RST_C		32
+#define R9A08G046_POEG_A_RST		33
+#define R9A08G046_POEG_B_RST		34
+#define R9A08G046_POEG_C_RST		35
+#define R9A08G046_POEG_D_RST		36
+#define R9A08G046_WDT0_PRESETN		37
+#define R9A08G046_WDT1_PRESETN		38
+#define R9A08G046_WDT2_PRESETN		39
+#define R9A08G046_XSPI_HRESETN		40
+#define R9A08G046_XSPI_ARESETN		41
+#define R9A08G046_SDHI0_IXRST		42
+#define R9A08G046_SDHI1_IXRST		43
+#define R9A08G046_SDHI2_IXRST		44
+#define R9A08G046_SDHI0_IXRSTAXIM	45
+#define R9A08G046_SDHI0_IXRSTAXIS	46
+#define R9A08G046_SDHI1_IXRSTAXIM	47
+#define R9A08G046_SDHI1_IXRSTAXIS	48
+#define R9A08G046_SDHI2_IXRSTAXIM	49
+#define R9A08G046_SDHI2_IXRSTAXIS	50
+#define R9A08G046_GE3D_RESETN		51
+#define R9A08G046_GE3D_AXI_RESETN	52
+#define R9A08G046_GE3D_ACE_RESETN	53
+#define R9A08G046_ISU_ARESETN		54
+#define R9A08G046_ISU_PRESETN		55
+#define R9A08G046_H264_X_RESET_VCP	56
+#define R9A08G046_H264_CP_PRESET_P	57
+#define R9A08G046_CRU_CMN_RSTB		58
+#define R9A08G046_CRU_PRESETN		59
+#define R9A08G046_CRU_ARESETN		60
+#define R9A08G046_MIPI_DSI_CMN_RSTB	61
+#define R9A08G046_MIPI_DSI_ARESET_N	62
+#define R9A08G046_MIPI_DSI_PRESET_N	63
+#define R9A08G046_LCDC_RESET_N		64
+#define R9A08G046_SSI0_RST_M2_REG	65
+#define R9A08G046_SSI1_RST_M2_REG	66
+#define R9A08G046_SSI2_RST_M2_REG	67
+#define R9A08G046_SSI3_RST_M2_REG	68
+#define R9A08G046_USB_U2H0_HRESETN	69
+#define R9A08G046_USB_U2H1_HRESETN	70
+#define R9A08G046_USB_U2P0_EXL_SYSRST	71
+#define R9A08G046_USB_PRESETN		72
+#define R9A08G046_USB_U2P1_EXL_SYSRST	73
+#define R9A08G046_ETH0_ARESET_N		74
+#define R9A08G046_ETH1_ARESET_N		75
+#define R9A08G046_I2C0_MRST		76
+#define R9A08G046_I2C1_MRST		77
+#define R9A08G046_I2C2_MRST		78
+#define R9A08G046_I2C3_MRST		79
+#define R9A08G046_SCIF0_RST_SYSTEM_N	80
+#define R9A08G046_SCIF1_RST_SYSTEM_N	81
+#define R9A08G046_SCIF2_RST_SYSTEM_N	82
+#define R9A08G046_SCIF3_RST_SYSTEM_N	83
+#define R9A08G046_SCIF4_RST_SYSTEM_N	84
+#define R9A08G046_SCIF5_RST_SYSTEM_N	85
+#define R9A08G046_RSPI0_PRESETN		86
+#define R9A08G046_RSPI1_PRESETN		87
+#define R9A08G046_RSPI2_PRESETN		88
+#define R9A08G046_RSPI0_TRESETN		89
+#define R9A08G046_RSPI1_TRESETN		90
+#define R9A08G046_RSPI2_TRESETN		91
+#define R9A08G046_CANFD_RSTP_N		92
+#define R9A08G046_CANFD_RSTC_N		93
+#define R9A08G046_GPIO_RSTN		94
+#define R9A08G046_GPIO_PORT_RESETN	95
+#define R9A08G046_GPIO_SPARE_RESETN	96
+#define R9A08G046_ADC0_PRESETN		97
+#define R9A08G046_ADC0_ADRST_N		98
+#define R9A08G046_ADC1_PRESETN		99
+#define R9A08G046_ADC1_ADRST_N		100
+#define R9A08G046_TSU_PRESETN		101
+#define R9A08G046_PDM_PRESETN		102
+#define R9A08G046_PCI_ARESETN		103
+#define R9A08G046_SPDIF_RST		104
+#define R9A08G046_I3C_TRESETN		105
+#define R9A08G046_I3C_PRESETN		106
+#define R9A08G046_VBAT_BRESETN		107
+#define R9A08G046_RSCI0_PRESETN		108
+#define R9A08G046_RSCI1_PRESETN		109
+#define R9A08G046_RSCI2_PRESETN		110
+#define R9A08G046_RSCI3_PRESETN		111
+#define R9A08G046_RSCI0_TRESETN		112
+#define R9A08G046_RSCI1_TRESETN		113
+#define R9A08G046_RSCI2_TRESETN		114
+#define R9A08G046_RSCI3_TRESETN		115
+#define R9A08G046_LVDS_RESET_N		116
+
+#endif /* __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__ */
-- 
2.43.0

[PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add the initial DTSI for the RZ/G3L SoC.
The files in this commit have the following meaning:
  - r9a08g046.dtsi:    RZ/G3L family SoC common parts
  - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts

Added place holders to reuse the code for Renesas SMARC II carrier
board.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Added external clocks eth{0,1}_txc_tx_clk and eth{0,1}_rxc_rx_clk
   as it needed for cpg as it is a clock source for mux.
 * Updated cpg node
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi    | 251 ++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi |  13 +
 2 files changed, 264 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046.dtsi
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
new file mode 100644
index 000000000000..0922ad642c67
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3L SoC
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+#include <dt-bindings/clock/r9a08g046-cpg.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a08g046";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&gic>;
+
+	audio_clk1: audio-clk1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it. */
+		clock-frequency = <0>;
+	};
+
+	audio_clk2: audio-clk2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it. */
+		clock-frequency = <0>;
+	};
+
+	can_clk: can-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by boards that provide it. */
+		clock-frequency = <0>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@100 {
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@200 {
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@300 {
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+			device_type = "cpu";
+			next-level-cache = <&L3_CA55>;
+			enable-method = "psci";
+		};
+
+		L3_CA55: cache-controller-0 {
+			compatible = "cache";
+			cache-unified;
+			cache-size = <0x80000>;
+			cache-level = <3>;
+		};
+	};
+
+	eth0_txc_tx_clk: eth0-txc-tx-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	eth0_rxc_rx_clk: eth0-rxc-rx-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	eth1_txc_tx_clk: eth1-txc-tx-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	eth1_rxc_rx_clk: eth1-rxc-rx-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board */
+		clock-frequency = <0>;
+	};
+
+	extal_clk: extal-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		/* This value must be overridden by the board. */
+		clock-frequency = <0>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0", "arm,psci-0.2";
+		method = "smc";
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		scif0: serial@100ac000 {
+			compatible = "renesas,scif-r9a08g046", "renesas,scif-r9a07g044";
+			reg = <0 0x100ac000 0 0x400>;
+			interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "eri", "rxi", "txi",
+					  "bri", "dri", "tei";
+			clocks = <&cpg CPG_MOD R9A08G046_SCIF0_CLK_PCK>;
+			clock-names = "fck";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G046_SCIF0_RST_SYSTEM_N>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@100ae000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x100AE000 0 0x400>;
+			/* placeholder */
+		};
+
+		canfd: can@100c0000 {
+			reg = <0 0x100c0000 0 0x20000>;
+			/* placeholder */
+		};
+
+		cpg: clock-controller@11010000 {
+			compatible = "renesas,r9a08g046-cpg";
+			reg = <0 0x11010000 0 0x10000>;
+			clocks = <&extal_clk>,
+				 <&eth0_txc_tx_clk>, <&eth0_rxc_rx_clk>,
+				 <&eth1_txc_tx_clk>, <&eth1_rxc_rx_clk>;
+			clock-names = "extal",
+				      "eth0_txc_tx_clk", "eth0_rxc_rx_clk",
+				      "eth1_txc_tx_clk", "eth1_rxc_rx_clk";
+			#clock-cells = <2>;
+			#reset-cells = <1>;
+			#power-domain-cells = <0>;
+		};
+
+		sysc: system-controller@11020000 {
+			compatible = "renesas,r9a08g046-sysc";
+			reg = <0 0x11020000 0 0x10000>;
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "lpm_int", "ca55stbydone_int",
+					  "cm33stbyr_int", "ca55_deny";
+		};
+
+		pinctrl: pinctrl@11030000 {
+			reg = <0 0x11030000 0 0x10000>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		dmac: dma-controller@11820000 {
+			compatible = "renesas,r9a08g046-dmac", "renesas,rz-dmac";
+			reg = <0 0x11820000 0 0x10000>,
+			      <0 0x11830000 0 0x10000>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 161 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "error",
+					  "ch0", "ch1", "ch2", "ch3",
+					  "ch4", "ch5", "ch6", "ch7",
+					  "ch8", "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15";
+			clocks = <&cpg CPG_MOD R9A08G046_DMAC_ACLK>,
+				 <&cpg CPG_MOD R9A08G046_DMAC_PCLK>;
+			clock-names = "main", "register";
+			power-domains = <&cpg>;
+			resets = <&cpg R9A08G046_DMAC_ARESETN>,
+				 <&cpg R9A08G046_DMAC_RST_ASYNC>;
+			reset-names = "arst", "rst_async";
+			#dma-cells = <1>;
+			dma-channels = <16>;
+		};
+
+		sdhi1: mmc@11c10000 {
+			reg = <0x0 0x11c10000 0 0x10000>;
+			/* placeholder */
+		};
+
+		gic: interrupt-controller@12400000 {
+			compatible = "arm,gic-v3";
+			reg = <0x0 0x12400000 0 0x20000>,
+			      <0x0 0x12440000 0 0x80000>;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+			interrupt-controller;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
+	};
+};
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
new file mode 100644
index 000000000000..f6f673abc01b
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3E R9A08G046L48 SoC specific parts
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r9a08g046.dtsi"
+
+/ {
+	compatible = "renesas,r9a08g046l48", "renesas,r9a08g046";
+};
-- 
2.43.0

[PATCH v3 08/10] arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add initial support for the RZ/G3L SMARC SoM with 2GB memory and
extal clk.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Dropped gpio.h header file.
---
 .../boot/dts/renesas/rzg3l-smarc-som.dtsi     | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi

diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
new file mode 100644
index 000000000000..7c21afaee9bc
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for R9A08G046L48 SMARC SoM board.
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/ {
+	compatible = "renesas,rzg3l-smarcm", "renesas,r9a08g046l48", "renesas,r9a08g046";
+
+	memory@48000000 {
+		device_type = "memory";
+		/* First 128MB is reserved for secure area. */
+		reg = <0x0 0x48000000 0x0 0x78000000>;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <24000000>;
+};
-- 
2.43.0

[PATCH v3 09/10] arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

SMARC2 board dtsi is common for multiple SoCs. So move usb3 nodes
to board DTS as some SOCs (eg: RZ/G3{S,L}) does not support USB3.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change
v1->v2:
 * No change
---
 arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts | 6 ++++++
 arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi    | 8 --------
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
index 696903dc7a63..cc75f6fdf7f5 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g047e57-smarc.dts
@@ -248,7 +248,13 @@ &sdhi1 {
 	vqmmc-supply = <&vqmmc_sd1_pvdd>;
 };
 
+&usb3_phy {
+	status = "okay";
+};
+
 &xhci {
 	pinctrl-0 = <&usb3_pins>;
 	pinctrl-names = "default";
+
+	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
index b607b5d6c259..69c0101ff7f5 100644
--- a/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
+++ b/arch/arm64/boot/dts/renesas/renesas-smarc2.dtsi
@@ -107,11 +107,3 @@ &sdhi1 {
 
 	status = "okay";
 };
-
-&usb3_phy {
-	status = "okay";
-};
-
-&xhci {
-	status = "okay";
-};
-- 
2.43.0

[PATCH v3 10/10] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add the initial device tree for the Renesas RZ/G3L SMARC EVK board.

Added placeholders to avoid compilation error with the common code in
renesas-smarc2.dtsi.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v2->v3:
 * No change.
v1->v2:
 * Dropped scif node as it is already included in common platform
   file.
---
 arch/arm64/boot/dts/renesas/Makefile          |  2 +
 .../boot/dts/renesas/r9a08g046l48-smarc.dts   | 37 +++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 1fab1b50f20e..0153e772c231 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -179,6 +179,8 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtbo
 r9a08g045s33-smarc-pmod1-type-3a-dtbs := r9a08g045s33-smarc.dtb r9a08g045s33-smarc-pmod1-type-3a.dtbo
 dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc-pmod1-type-3a.dtb
 
+dtb-$(CONFIG_ARCH_R9A08G046) += r9a08g046l48-smarc.dtb
+
 dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb
 
 dtb-$(CONFIG_ARCH_R9A09G047) += r9a09g047e57-smarc.dtb
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
new file mode 100644
index 000000000000..86db86335d5e
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/G3L SMARC EVK board
+ *
+ * Copyright (C) 2026 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/* Add place holder to avoid compilation error with renesas-smarc2.dtsi */
+#define KEY_1_GPIO		1
+#define KEY_2_GPIO		2
+#define KEY_3_GPIO		3
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "r9a08g046l48.dtsi"
+#include "rzg3l-smarc-som.dtsi"
+#include "renesas-smarc2.dtsi"
+
+/ {
+	model = "Renesas SMARC EVK version 2 based on r9a08g046l48";
+	compatible = "renesas,smarc2-evk", "renesas,rzg3l-smarcm",
+		     "renesas,r9a08g046l48", "renesas,r9a08g046";
+
+	aliases {
+		serial3 = &scif0;
+	};
+};
+
+&keys {
+	status = "disabled";
+
+	/delete-node/ key-1;
+	/delete-node/ key-2;
+	/delete-node/ key-3;
+};
-- 
2.43.0

Re: [PATCH v3 02/10] dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and Carrier-II EVK

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 75 bytes --]

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

RE: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Biju Das]

Hi all,

> -----Original Message-----
> From: Biju <biju.das.au@gmail.com>
> Sent: 03 February 2026 10:30
> Subject: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC
> 
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse Generator (CPG). RZ/G3L CPG
> is similar to RZ/G2L CPG but has 5 clocks compared to 1 clock on other SoCs.
> 
> Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock, module clock outputs, as listed in
> section 4.4.2 ("Clock List r1.00") and add Reset definitions referring to registers CPG_RST_* in
> Section 4.4.3
> ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v2->v3:
>  * Added macros R9A08G046_ETH{0,1}_CLK_{TX,RX}_I_RMII.
>  * Keep the tag from Conor as it is trivial change for just adding macros.
> v1->v2:
>  * Documented external ethernet clocks as it is a clock source for MUX
>    inside CPG
>  * Updated commit description.
>  * Keep the tag from Conor as it is trivial change for adding more
>    clks.
> ---
>  .../bindings/clock/renesas,rzg2l-cpg.yaml     |  40 +-
>  include/dt-bindings/clock/r9a08g046-cpg.h     | 343 ++++++++++++++++++
>  2 files changed, 378 insertions(+), 5 deletions(-)  create mode 100644 include/dt-
> bindings/clock/r9a08g046-cpg.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> index 8c18616e5c4d..c0ce687d83ee 100644
> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -28,19 +28,30 @@ properties:
>        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
>        - renesas,r9a07g054-cpg # RZ/V2L
>        - renesas,r9a08g045-cpg # RZ/G3S
> +      - renesas,r9a08g046-cpg # RZ/G3L
>        - renesas,r9a09g011-cpg # RZ/V2M
> 
>    reg:
>      maxItems: 1
> 
>    clocks:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: Clock source to CPG can be either from external clock
> +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> +      - description: ETH0 TXC clock input
> +      - description: ETH0 RXC clock input
> +      - description: ETH1 TXC clock input
> +      - description: ETH1 RXC clock input
> 
>    clock-names:
> -    description:
> -      Clock source to CPG can be either from external clock input (EXCLK) or
> -      crystal oscillator (XIN/XOUT).
> -    const: extal
> +    minItems: 1
> +    items:
> +      - const: extal
> +      - const: eth0_txc_tx_clk
> +      - const: eth0_rxc_rx_clk
> +      - const: eth1_txc_tx_clk
> +      - const: eth1_rxc_rx_clk
> 
>    '#clock-cells':
>      description: |
> @@ -74,6 +85,25 @@ required:
>    - '#power-domain-cells'
>    - '#reset-cells'
> 
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a08g046-cpg
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 5
> +        clock-names:
> +          minItems: 5
> +    else:
> +      properties:
> +        clocks:
> +          maxItems: 1
> +        clock-names:
> +          maxItems: 1
> +
>  additionalProperties: false
> 
>  examples:
> diff --git a/include/dt-bindings/clock/r9a08g046-cpg.h b/include/dt-bindings/clock/r9a08g046-cpg.h
> new file mode 100644
> index 000000000000..ca484e065bbe
> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a08g046-cpg.h
> @@ -0,0 +1,343 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A08G046 CPG Core Clocks */
> +#define R9A08G046_CLK_I			0
> +#define R9A08G046_CLK_IC0		1
> +#define R9A08G046_CLK_IC1		2
> +#define R9A08G046_CLK_IC2		3
> +#define R9A08G046_CLK_IC3		4
> +#define R9A08G046_CLK_P0		5
> +#define R9A08G046_CLK_P1		6
> +#define R9A08G046_CLK_P2		7
> +#define R9A08G046_CLK_P3		8
> +#define R9A08G046_CLK_P4		9
> +#define R9A08G046_CLK_P5		10
> +#define R9A08G046_CLK_P6		11
> +#define R9A08G046_CLK_P7		12
> +#define R9A08G046_CLK_P8		13
> +#define R9A08G046_CLK_P9		14
> +#define R9A08G046_CLK_P10		15
> +#define R9A08G046_CLK_P13		16
> +#define R9A08G046_CLK_P14		17
> +#define R9A08G046_CLK_P15		18
> +#define R9A08G046_CLK_P16		19
> +#define R9A08G046_CLK_P17		20
> +#define R9A08G046_CLK_P18		21
> +#define R9A08G046_CLK_P19		22
> +#define R9A08G046_CLK_P20		23
> +#define R9A08G046_CLK_M0		24
> +#define R9A08G046_CLK_M1		25
> +#define R9A08G046_CLK_M2		26
> +#define R9A08G046_CLK_M3		27
> +#define R9A08G046_CLK_M4		28
> +#define R9A08G046_CLK_M5		29
> +#define R9A08G046_CLK_M6		30
> +#define R9A08G046_CLK_AT		31
> +#define R9A08G046_CLK_B			32
> +#define R9A08G046_CLK_ETHTX01		33
> +#define R9A08G046_CLK_ETHTX02		34
> +#define R9A08G046_CLK_ETHRX01		35
> +#define R9A08G046_CLK_ETHRX02		36
> +#define R9A08G046_CLK_ETHRM0		37
> +#define R9A08G046_CLK_ETHTX11		38
> +#define R9A08G046_CLK_ETHTX12		39
> +#define R9A08G046_CLK_ETHRX11		40
> +#define R9A08G046_CLK_ETHRX12		41
> +#define R9A08G046_CLK_ETHRM1		42
> +#define R9A08G046_CLK_G			43
> +#define R9A08G046_CLK_HP		44
> +#define R9A08G046_CLK_SD0		45
> +#define R9A08G046_CLK_SD1		46
> +#define R9A08G046_CLK_SD2		47
> +#define R9A08G046_CLK_SPI0		48
> +#define R9A08G046_CLK_SPI1		49
> +#define R9A08G046_CLK_S0		50
> +#define R9A08G046_CLK_SWD		51
> +#define R9A08G046_OSCCLK		52
> +#define R9A08G046_OSCCLK2		53
> +#define R9A08G046_CLK_P4_DIV2		54
> +
> +/* R9A08G046 Module Clocks */
> +#define R9A08G046_CA55_SCLK		0
> +#define R9A08G046_CA55_PCLK		1
> +#define R9A08G046_CA55_ATCLK		2
> +#define R9A08G046_CA55_GICCLK		3
> +#define R9A08G046_CA55_PERICLK		4
> +#define R9A08G046_CA55_ACLK		5
> +#define R9A08G046_CA55_TSCLK		6
> +#define R9A08G046_CA55_CORECLK0		7
> +#define R9A08G046_CA55_CORECLK1		8
> +#define R9A08G046_CA55_CORECLK2		9
> +#define R9A08G046_CA55_CORECLK3		10
> +#define R9A08G046_SRAM_ACPU_ACLK0	11
> +#define R9A08G046_SRAM_ACPU_ACLK1	12
> +#define R9A08G046_SRAM_ACPU_ACLK2	13
> +#define R9A08G046_GIC600_GICCLK		14
> +#define R9A08G046_IA55_CLK		15
> +#define R9A08G046_IA55_PCLK		16
> +#define R9A08G046_MHU_PCLK		17
> +#define R9A08G046_SYC_CNT_CLK		18
> +#define R9A08G046_DMAC_ACLK		19
> +#define R9A08G046_DMAC_PCLK		20
> +#define R9A08G046_OSTM0_PCLK		21
> +#define R9A08G046_OSTM1_PCLK		22
> +#define R9A08G046_OSTM2_PCLK		23
> +#define R9A08G046_MTU_X_MCK_MTU3	24
> +#define R9A08G046_POE3_CLKM_POE		25
> +#define R9A08G046_GPT_PCLK		26
> +#define R9A08G046_POEG_A_CLKP		27
> +#define R9A08G046_POEG_B_CLKP		28
> +#define R9A08G046_POEG_C_CLKP		29
> +#define R9A08G046_POEG_D_CLKP		30
> +#define R9A08G046_WDT0_PCLK		31
> +#define R9A08G046_WDT0_CLK		32
> +#define R9A08G046_WDT1_PCLK		33
> +#define R9A08G046_WDT1_CLK		34
> +#define R9A08G046_WDT2_PCLK		35
> +#define R9A08G046_WDT2_CLK		36
> +#define R9A08G046_XSPI_HCLK		37
> +#define R9A08G046_XSPI_ACLK		38
> +#define R9A08G046_XSPI_CLK		39
> +#define R9A08G046_XSPI_CLKX2		40
> +#define R9A08G046_SDHI0_IMCLK		41
> +#define R9A08G046_SDHI0_IMCLK2		42
> +#define R9A08G046_SDHI0_CLK_HS		43
> +#define R9A08G046_SDHI0_IACLKS		44
> +#define R9A08G046_SDHI0_IACLKM		45
> +#define R9A08G046_SDHI1_IMCLK		46
> +#define R9A08G046_SDHI1_IMCLK2		47
> +#define R9A08G046_SDHI1_CLK_HS		48
> +#define R9A08G046_SDHI1_IACLKS		49
> +#define R9A08G046_SDHI1_IACLKM		50
> +#define R9A08G046_SDHI2_IMCLK		51
> +#define R9A08G046_SDHI2_IMCLK2		52
> +#define R9A08G046_SDHI2_CLK_HS		53
> +#define R9A08G046_SDHI2_IACLKS		54
> +#define R9A08G046_SDHI2_IACLKM		55
> +#define R9A08G046_GE3D_CLK		56
> +#define R9A08G046_GE3D_AXI_CLK		57
> +#define R9A08G046_GE3D_ACE_CLK		58
> +#define R9A08G046_ISU_ACLK		59
> +#define R9A08G046_ISU_PCLK		60
> +#define R9A08G046_H264_CLK_A		61
> +#define R9A08G046_H264_CLK_P		62
> +#define R9A08G046_CRU_SYSCLK		63
> +#define R9A08G046_CRU_VCLK		64
> +#define R9A08G046_CRU_PCLK		65
> +#define R9A08G046_CRU_ACLK		66
> +#define R9A08G046_MIPI_DSI_PLLCLK	67

As per hardware manual this clock cannot be gated,
Looks this to be moved to core clk??
(4.4.6.4 Procedure for Activating the Modules Related to PLL7)

Cheers,
Biju

Re: (subset) [PATCH v3 00/10] Add support for Renesas RZ/G3L SoC and SMARC-EVK platform

[Vinod Koul]

On Tue, 03 Feb 2026 10:30:08 +0000, Biju wrote:
> This patch series adds initial support for the Renesas RZ/G3L SoC and
> RZ/G3L SMARC EVK platform. The RZ/G3L device is a general-purpose
> microprocessor with a quad-core CA-55, single core CM-33, Mali-G31
> 3-D Graphics and other peripherals.
> 
> Support for the below list of blocks is added in the SoC DTSI (r9a08g046.dtsi):
> 
> [...]

Applied, thanks!

[01/10] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
        commit: e45cf0c7d9b960f1aae4ee56c3c3d46549ccde86

Best regards,
-- 
~Vinod

Re: [PATCH v3 01/10] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document the Renesas RZ/G3L DMAC block. This is identical to the one found
> on the RZ/G3S SoC.
>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch, which is now commit e45cf0c7d9b960f1
("dt-bindings: dma: rz-dmac: Document RZ/G3L SoC") in dmaengine/next.

> --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -19,6 +19,7 @@ properties:
>                - renesas,r9a07g044-dmac # RZ/G2{L,LC}
>                - renesas,r9a07g054-dmac # RZ/V2L
>                - renesas,r9a08g045-dmac # RZ/G3S
> +              - renesas,r9a08g046-dmac # RZ/G3L
>            - const: renesas,rz-dmac
>
>        - items:

This part is good, but you forgot to update the conditional section
below, restricting various property ranges.

                    - renesas,r9a07g044-dmac
                    - renesas,r9a07g054-dmac
                    - renesas,r9a08g045-dmac
    +               - renesas,r9a08g045-dmac
          then:
            properties:
              reg:

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 02/10] dt-bindings: soc: renesas: Document RZ/G3L SoC variants, SMARC SoM and Carrier-II EVK

[Geert Uytterhoeven]

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document Renesas RZ/G3L (R9A08G046) SoC variants and the Renesas RZ/G3L
> SMARC Carrier-II EVK board which is based on the Renesas RZ/G3L SMARC SoM.
> The RZ/G3L SMARC Carrier-II EVK consists of an RZ/G3L SoM module and a
> SMARC Carrier-II carrier board. The SoM module sits on top of the carrier
> board.
>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 03/10] dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/G3L SoC

[Geert Uytterhoeven]

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document RZ/G3L (R9A08G046) SYSC bindings. The SYSC block found on the
> RZ/G3L SoC is similar to the one found on the RZ/G3S.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 01/10] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 04 March 2026 08:22
> Subject: Re: [PATCH v3 01/10] dt-bindings: dma: rz-dmac: Document RZ/G3L SoC
> 
> Hi Biju,
> 
> On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document the Renesas RZ/G3L DMAC block. This is identical to the one
> > found on the RZ/G3S SoC.
> >
> > Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch, which is now commit e45cf0c7d9b960f1
> ("dt-bindings: dma: rz-dmac: Document RZ/G3L SoC") in dmaengine/next.
> 
> > --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > @@ -19,6 +19,7 @@ properties:
> >                - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> >                - renesas,r9a07g054-dmac # RZ/V2L
> >                - renesas,r9a08g045-dmac # RZ/G3S
> > +              - renesas,r9a08g046-dmac # RZ/G3L
> >            - const: renesas,rz-dmac
> >
> >        - items:
> 
> This part is good, but you forgot to update the conditional section below, restricting various
> property ranges.

Oops, I will send a patch for handling this.

Cheers,
Biju

Re: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

Thanks for your patch!

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Document the device tree bindings for the Renesas RZ/G3L SoC Clock Pulse
> Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5 clocks
> compared to 1 clock on other SoCs.
>
> Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock, module

Core Clocks, as listed in section 4.4.1 ("Block Diagram of the Clock System")

> clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
> Reset definitions referring to registers CPG_RST_* in Section 4.4.3
> ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> @@ -28,19 +28,30 @@ properties:
>        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
>        - renesas,r9a07g054-cpg # RZ/V2L
>        - renesas,r9a08g045-cpg # RZ/G3S
> +      - renesas,r9a08g046-cpg # RZ/G3L
>        - renesas,r9a09g011-cpg # RZ/V2M
>
>    reg:
>      maxItems: 1
>
>    clocks:
> -    maxItems: 1
> +    minItems: 1
> +    items:
> +      - description: Clock source to CPG can be either from external clock
> +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> +      - description: ETH0 TXC clock input
> +      - description: ETH0 RXC clock input
> +      - description: ETH1 TXC clock input
> +      - description: ETH1 RXC clock input
>
>    clock-names:
> -    description:
> -      Clock source to CPG can be either from external clock input (EXCLK) or
> -      crystal oscillator (XIN/XOUT).
> -    const: extal
> +    minItems: 1
> +    items:
> +      - const: extal
> +      - const: eth0_txc_tx_clk
> +      - const: eth0_rxc_rx_clk
> +      - const: eth1_txc_tx_clk
> +      - const: eth1_rxc_rx_clk

Are you sure about these four clocks? On which pins are they input?

>
>    '#clock-cells':
>      description: |

> --- /dev/null
> +++ b/include/dt-bindings/clock/r9a08g046-cpg.h
> @@ -0,0 +1,343 @@
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> +
> +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> +
> +/* R9A08G046 CPG Core Clocks */

[...]

> +#define R9A08G046_OSCCLK               52
> +#define R9A08G046_OSCCLK2              53
> +#define R9A08G046_CLK_P4_DIV2          54

CLK_P4_DIV2 looks like a purely internal clock to me.


> +
> +/* R9A08G046 Module Clocks */

[...]

> +#define R9A08G046_CRU_PCLK             65
> +#define R9A08G046_CRU_ACLK             66
> +#define R9A08G046_MIPI_DSI_PLLCLK      67

MIPI_DSI_PLLCLK is indeed not a gateable clock, so it should be a core
clock.

> +#define R9A08G046_MIPI_DSI_SYSCLK      68
> +#define R9A08G046_MIPI_DSI_ACLK                69
> +#define R9A08G046_MIPI_DSI_PCLK                70
> +#define R9A08G046_MIPI_DSI_VCLK                71
> +#define R9A08G046_MIPI_DSI_LPCLK       72
> +#define R9A08G046_LVDS_PLLCLK          73
> +#define R9A08G046_LVDS_CLK_DOT0                74
> +#define R9A08G046_LVDS_PCLK            75

LVDS_PCLK does not seem to exist, there is only a single reference to it
(but I can see where its gate bit used to be ;-)

> +#define R9A08G046_LCDC_CLK_A           76
> +#define R9A08G046_LCDC_CLK_D           77
> +#define R9A08G046_LCDC_CLK_P           78
> +#define R9A08G046_SSI0_PCLK2           79
> +#define R9A08G046_SSI0_PCLK_SFR                80
> +#define R9A08G046_SSI1_PCLK2           81
> +#define R9A08G046_SSI1_PCLK_SFR                82
> +#define R9A08G046_SSI2_PCLK2           83
> +#define R9A08G046_SSI2_PCLK_SFR                84
> +#define R9A08G046_SSI3_PCLK2           85
> +#define R9A08G046_SSI3_PCLK_SFR                86
> +#define R9A08G046_USB_U2H0_HCLK                87
> +#define R9A08G046_USB_U2H1_HCLK                88
> +#define R9A08G046_USB_U2P0_EXR_CPUCLK  89
> +#define R9A08G046_USB_U2P1_EXR_CPUCLK  90
> +#define R9A08G046_USB_PCLK             91
> +#define R9A08G046_USB_SCLK             92

USB_SCLK is not gateable, so it should be a core clock.

[...]

> +/* R9A08G046 Resets */

[...]

> +#define R9A08G046_RSCI2_TRESETN                114
> +#define R9A08G046_RSCI3_TRESETN                115
> +#define R9A08G046_LVDS_RESET_N         116

Missing BSC_X_PRESET_BSC?
It could be added later, but you do list the corresponding module clock.

> +
> +#endif /* __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__ */


The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add the initial DTSI for the RZ/G3L SoC.
> The files in this commit have the following meaning:
>   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
>   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
>
> Added place holders to reuse the code for Renesas SMARC II carrier
> board.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> @@ -0,0 +1,251 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/G3L SoC
> + *
> + * Copyright (C) 2026 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/clock/r9a08g046-cpg.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +       compatible = "renesas,r9a08g046";
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +       interrupt-parent = <&gic>;
> +
> +       audio_clk1: audio-clk1 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by boards that provide it. */
> +               clock-frequency = <0>;
> +       };
> +
> +       audio_clk2: audio-clk2 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by boards that provide it. */
> +               clock-frequency = <0>;
> +       };
> +
> +       can_clk: can-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by boards that provide it. */
> +               clock-frequency = <0>;
> +       };

These three are unused, so please drop them.

[...]

> +       eth0_txc_tx_clk: eth0-txc-tx-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };
> +
> +       eth0_rxc_rx_clk: eth0-rxc-rx-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };
> +
> +       eth1_txc_tx_clk: eth1-txc-tx-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };
> +
> +       eth1_rxc_rx_clk: eth1-rxc-rx-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board */
> +               clock-frequency = <0>;
> +       };

TBD...

> +
> +       extal_clk: extal-clk {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               /* This value must be overridden by the board. */
> +               clock-frequency = <0>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0", "arm,psci-0.2";
> +               method = "smc";
> +       };
> +
> +       soc: soc {

> +               i2c0: i2c@100ae000 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;

Please move these two below "reg".

> +                       reg = <0 0x100AE000 0 0x400>;

Please use lower-case hexadecimal.

> +                       /* placeholder */
> +               };

> +               pinctrl: pinctrl@11030000 {
> +                       reg = <0 0x11030000 0 0x10000>;
> +                       gpio-controller;
> +                       #gpio-cells = <2>;

/* placeholder */

> +               };
> +
> +               dmac: dma-controller@11820000 {

Unused. Surely you can wire up scif0?

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Thu, 5 Mar 2026 at 15:54, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add the initial DTSI for the RZ/G3L SoC.
> > The files in this commit have the following meaning:
> >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> >   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts

r9a08g046l48.dtsi does not apply to R0A08G046L46, as it uses the
wrong compatible value?

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 08/10] arm64: dts: renesas: Add initial support for RZ/G3L SMARC SoM

[Geert Uytterhoeven]

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add initial support for the RZ/G3L SMARC SoM with 2GB memory and
> extal clk.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 09/10] arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS

[Geert Uytterhoeven]

Hi Biju,

Thanks for your patch!

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:

> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> SMARC2 board dtsi is common for multiple SoCs. So move usb3 nodes
> to board DTS as some SOCs (eg: RZ/G3{S,L}) does not support USB3.

s/does/do/

>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 10/10] arm64: dts: renesas: Add initial device tree for RZ/G3L SMARC EVK board

[Geert Uytterhoeven]

On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> Add the initial device tree for the Renesas RZ/G3L SMARC EVK board.
>
> Added placeholders to avoid compilation error with the common code in
> renesas-smarc2.dtsi.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 05 March 2026 14:21
> Subject: Re: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Document the device tree bindings for the Renesas RZ/G3L SoC Clock
> > Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5
> > clocks compared to 1 clock on other SoCs.
> >
> > Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock,
> > module
> 
> Core Clocks, as listed in section 4.4.1 ("Block Diagram of the Clock System")

OK, will update.

> 
> > clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
> > Reset definitions referring to registers CPG_RST_* in Section 4.4.3
> > ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
> >
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> > --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > @@ -28,19 +28,30 @@ properties:
> >        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
> >        - renesas,r9a07g054-cpg # RZ/V2L
> >        - renesas,r9a08g045-cpg # RZ/G3S
> > +      - renesas,r9a08g046-cpg # RZ/G3L
> >        - renesas,r9a09g011-cpg # RZ/V2M
> >
> >    reg:
> >      maxItems: 1
> >
> >    clocks:
> > -    maxItems: 1
> > +    minItems: 1
> > +    items:
> > +      - description: Clock source to CPG can be either from external clock
> > +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> > +      - description: ETH0 TXC clock input
> > +      - description: ETH0 RXC clock input
> > +      - description: ETH1 TXC clock input
> > +      - description: ETH1 RXC clock input
> >
> >    clock-names:
> > -    description:
> > -      Clock source to CPG can be either from external clock input (EXCLK) or
> > -      crystal oscillator (XIN/XOUT).
> > -    const: extal
> > +    minItems: 1
> > +    items:
> > +      - const: extal
> > +      - const: eth0_txc_tx_clk
> > +      - const: eth0_rxc_rx_clk
> > +      - const: eth1_txc_tx_clk
> > +      - const: eth1_rxc_rx_clk
> 
> Are you sure about these four clocks? On which pins are they input?

From Figure 4.4-5 Block Diagram of the Deformed Clock System (4), page 789

These clks are external source clks connected to CPG_ETH_SSEL mux for
selecting rx/tx clks.

In RGMII case, currently on RZ/G3L SMARC EVK:

For Tx: we select DIV_ETH0_TR (SEL_ETH0A_SET)
For Rx: we select ETH0_RXC_RX_CLK_IN (SEL_ETH0B_SET)

> 
> >
> >    '#clock-cells':
> >      description: |
> 
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a08g046-cpg.h
> > @@ -0,0 +1,343 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2026 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* R9A08G046 CPG Core Clocks */
> 
> [...]
> 
> > +#define R9A08G046_OSCCLK               52
> > +#define R9A08G046_OSCCLK2              53
> > +#define R9A08G046_CLK_P4_DIV2          54
> 
> CLK_P4_DIV2 looks like a purely internal clock to me.

Page 3918 Figure 7.9-1 Block Diagram of CAN-FD

Peripheral clk,
RAM clk,
CAN external clk

Then, CANFD clk which is DIV2 clk of Peripheral clk, so thought of
modelling this as Core clk. I may be wrong here??

Maybe I will drop this now and revisit later when we add support for CANFD??

> 
> 
> > +
> > +/* R9A08G046 Module Clocks */
> 
> [...]
> 
> > +#define R9A08G046_CRU_PCLK             65
> > +#define R9A08G046_CRU_ACLK             66
> > +#define R9A08G046_MIPI_DSI_PLLCLK      67
> 
> MIPI_DSI_PLLCLK is indeed not a gateable clock, so it should be a core clock.

Agreed.

> 
> > +#define R9A08G046_MIPI_DSI_SYSCLK      68
> > +#define R9A08G046_MIPI_DSI_ACLK                69
> > +#define R9A08G046_MIPI_DSI_PCLK                70
> > +#define R9A08G046_MIPI_DSI_VCLK                71
> > +#define R9A08G046_MIPI_DSI_LPCLK       72
> > +#define R9A08G046_LVDS_PLLCLK          73
> > +#define R9A08G046_LVDS_CLK_DOT0                74
> > +#define R9A08G046_LVDS_PCLK            75
> 
> LVDS_PCLK does not seem to exist, there is only a single reference to it (but I can see where its gate
> bit used to be ;-)

OK, will drop this clk as there is no control bits in the HW manual.

> 
> > +#define R9A08G046_LCDC_CLK_A           76
> > +#define R9A08G046_LCDC_CLK_D           77
> > +#define R9A08G046_LCDC_CLK_P           78
> > +#define R9A08G046_SSI0_PCLK2           79
> > +#define R9A08G046_SSI0_PCLK_SFR                80
> > +#define R9A08G046_SSI1_PCLK2           81
> > +#define R9A08G046_SSI1_PCLK_SFR                82
> > +#define R9A08G046_SSI2_PCLK2           83
> > +#define R9A08G046_SSI2_PCLK_SFR                84
> > +#define R9A08G046_SSI3_PCLK2           85
> > +#define R9A08G046_SSI3_PCLK_SFR                86
> > +#define R9A08G046_USB_U2H0_HCLK                87
> > +#define R9A08G046_USB_U2H1_HCLK                88
> > +#define R9A08G046_USB_U2P0_EXR_CPUCLK  89 #define
> > +R9A08G046_USB_U2P1_EXR_CPUCLK  90
> > +#define R9A08G046_USB_PCLK             91
> > +#define R9A08G046_USB_SCLK             92
> 
> USB_SCLK is not gateable, so it should be a core clock.

OK, will add this as core clock.

> 
> [...]
> 
> > +/* R9A08G046 Resets */
> 
> [...]
> 
> > +#define R9A08G046_RSCI2_TRESETN                114
> > +#define R9A08G046_RSCI3_TRESETN                115
> > +#define R9A08G046_LVDS_RESET_N         116
> 
> Missing BSC_X_PRESET_BSC?
> It could be added later, but you do list the corresponding module clock.

I missed it. Will add it in next version. 

Cheers,
Biju

RE: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 05 March 2026 14:57
> Subject: Re: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
> 
> Hi Biju,
> 
> On Thu, 5 Mar 2026 at 15:54, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > Add the initial DTSI for the RZ/G3L SoC.
> > > The files in this commit have the following meaning:
> > >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> > >   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
> 
> r9a08g046l48.dtsi does not apply to R0A08G046L46, as it uses the wrong compatible value?

OK, I will update commit description dropping R0A08G046L46

Cheers,
Biju

RE: [PATCH v3 09/10] arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 05 March 2026 15:00
> Subject: Re: [PATCH v3 09/10] arm64: dts: renesas: renesas-smarc2: Move usb3 nodes to board DTS
> 
> Hi Biju,
> 
> Thanks for your patch!
> 
> On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> 
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > SMARC2 board dtsi is common for multiple SoCs. So move usb3 nodes to
> > board DTS as some SOCs (eg: RZ/G3{S,L}) does not support USB3.
> 
> s/does/do/

Will fix it in next version.

Cheers,
Biju

RE: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 05 March 2026 14:54
> Subject: Re: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
> 
> Hi Biju,
> 
> On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add the initial DTSI for the RZ/G3L SoC.
> > The files in this commit have the following meaning:
> >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> >   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
> >
> > Added place holders to reuse the code for Renesas SMARC II carrier
> > board.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > @@ -0,0 +1,251 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +/*
> > + * Device Tree Source for the RZ/G3L SoC
> > + *
> > + * Copyright (C) 2026 Renesas Electronics Corp.
> > + */
> > +
> > +#include <dt-bindings/clock/r9a08g046-cpg.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +/ {
> > +       compatible = "renesas,r9a08g046";
> > +       #address-cells = <2>;
> > +       #size-cells = <2>;
> > +       interrupt-parent = <&gic>;
> > +
> > +       audio_clk1: audio-clk1 {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by boards that provide it. */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       audio_clk2: audio-clk2 {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by boards that provide it. */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       can_clk: can-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by boards that provide it. */
> > +               clock-frequency = <0>;
> > +       };
> 
> These three are unused, so please drop them.

Agreed.

> 
> [...]
> 
> > +       eth0_txc_tx_clk: eth0-txc-tx-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       eth0_rxc_rx_clk: eth0-rxc-rx-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       eth1_txc_tx_clk: eth1-txc-tx-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       eth1_rxc_rx_clk: eth1-rxc-rx-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board */
> > +               clock-frequency = <0>;
> > +       };
> 
> TBD...
OK.

> 
> > +
> > +       extal_clk: extal-clk {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               /* This value must be overridden by the board. */
> > +               clock-frequency = <0>;
> > +       };
> > +
> > +       psci {
> > +               compatible = "arm,psci-1.0", "arm,psci-0.2";
> > +               method = "smc";
> > +       };
> > +
> > +       soc: soc {
> 
> > +               i2c0: i2c@100ae000 {
> > +                       #address-cells = <1>;
> > +                       #size-cells = <0>;
> 
> Please move these two below "reg".

OK.

> 
> > +                       reg = <0 0x100AE000 0 0x400>;
> 
> Please use lower-case hexadecimal.

OK.

> 
> > +                       /* placeholder */
> > +               };
> 
> > +               pinctrl: pinctrl@11030000 {
> > +                       reg = <0 0x11030000 0 0x10000>;
> > +                       gpio-controller;
> > +                       #gpio-cells = <2>;
> 
> /* placeholder */

OK.

> 
> > +               };
> > +
> > +               dmac: dma-controller@11820000 {
> 
> Unused. Surely you can wire up scif0?

Yes, but I don't get login prompt, as SCIF0 interrupts have dependency on
DMA reset/clocks to route the interrupts to CPU.

Cheers,
Biju

Re: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Thu, 5 Mar 2026 at 17:58, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > > Add the initial DTSI for the RZ/G3L SoC.
> > > The files in this commit have the following meaning:
> > >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> > >   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
> > >
> > > Added place holders to reuse the code for Renesas SMARC II carrier
> > > board.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
=
> > > +               dmac: dma-controller@11820000 {
> >
> > Unused. Surely you can wire up scif0?
>
> Yes, but I don't get login prompt, as SCIF0 interrupts have dependency on
> DMA reset/clocks to route the interrupts to CPU.

Aha ;-)

So you need to enable the DMA clock and deassert the DMA reset in the
clock/reset driver, and mark them critical.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 06 March 2026 08:51
> Subject: Re: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
> 
> Hi Biju,
> 
> On Thu, 5 Mar 2026 at 17:58, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, 3 Feb 2026
> > > at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > > > Add the initial DTSI for the RZ/G3L SoC.
> > > > The files in this commit have the following meaning:
> > > >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> > > >   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
> > > >
> > > > Added place holders to reuse the code for Renesas SMARC II carrier
> > > > board.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> =
> > > > +               dmac: dma-controller@11820000 {
> > >
> > > Unused. Surely you can wire up scif0?
> >
> > Yes, but I don't get login prompt, as SCIF0 interrupts have dependency
> > on DMA reset/clocks to route the interrupts to CPU.
> 
> Aha ;-)
> 
> So you need to enable the DMA clock and deassert the DMA reset in the clock/reset driver, and mark
> them critical.

For CLK, already framework is providing critical clock support, which turns on the clk at the start.
But for reset there is no support for critical reset in the reset framework.

you mean handle this in SoC specific driver for DMA deassert like[1]
DEF_RST_INIT_DEASSERTED during boot??

Or

Create a critical reset table in the SoC specific driver like clk
and explicitly deassert the resets in CPG core driver during probe??


Note:
For Suspend to RAM, marking critical clock/critical reset won't solve the issue
as we need to explicitly turn on DMA CLK/dessert reset for routing SCIF0 irq to CPU.

[1]
https://lore.kernel.org/linux-renesas-soc/20260210113041.138430-4-john.madieu.xa@bp.renesas.com/


Cheers,
Biju

Re: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Fri, 6 Mar 2026 at 10:10, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Thu, 5 Mar 2026 at 17:58, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, 3 Feb 2026
> > > > at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > > > > Add the initial DTSI for the RZ/G3L SoC.
> > > > > The files in this commit have the following meaning:
> > > > >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> > > > >   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific parts
> > > > >
> > > > > Added place holders to reuse the code for Renesas SMARC II carrier
> > > > > board.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > > > > --- /dev/null
> > > > > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > =
> > > > > +               dmac: dma-controller@11820000 {
> > > >
> > > > Unused. Surely you can wire up scif0?
> > >
> > > Yes, but I don't get login prompt, as SCIF0 interrupts have dependency
> > > on DMA reset/clocks to route the interrupts to CPU.
> >
> > Aha ;-)
> >
> > So you need to enable the DMA clock and deassert the DMA reset in the clock/reset driver, and mark
> > them critical.
>
> For CLK, already framework is providing critical clock support, which turns on the clk at the start.
> But for reset there is no support for critical reset in the reset framework.
>
> you mean handle this in SoC specific driver for DMA deassert like[1]
> DEF_RST_INIT_DEASSERTED during boot??
>
> Or
>
> Create a critical reset table in the SoC specific driver like clk
> and explicitly deassert the resets in CPG core driver during probe??

The latter sounds simpler to me...

You also have to avoid the DMAC is reset is ever being asserted again.

> Note:
> For Suspend to RAM, marking critical clock/critical reset won't solve the issue
> as we need to explicitly turn on DMA CLK/dessert reset for routing SCIF0 irq to CPU.

So you need to add suspendresume support to the clock driver,
to enable the clock and deassert the reset during resume?

> [1]
> https://lore.kernel.org/linux-renesas-soc/20260210113041.138430-4-john.madieu.xa@bp.renesas.com/

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC

[Biju Das]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 06 March 2026 09:25
> Subject: Re: [PATCH v3 07/10] arm64: dts: renesas: Add initial DTSI for RZ/G3L SoC
> 
> Hi Biju,
> 
> On Fri, 6 Mar 2026 at 10:10, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Thu, 5 Mar 2026
> > > at 17:58, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, 3 Feb
> > > > > 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > > > > > Add the initial DTSI for the RZ/G3L SoC.
> > > > > > The files in this commit have the following meaning:
> > > > > >   - r9a08g046.dtsi:    RZ/G3L family SoC common parts
> > > > > >   - r9a08g046l48.dtsi: RZ/G3L R0A08G046L{46,48} SoC specific
> > > > > > parts
> > > > > >
> > > > > > Added place holders to reuse the code for Renesas SMARC II
> > > > > > carrier board.
> > > > > >
> > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > > > > --- /dev/null
> > > > > > +++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
> > > =
> > > > > > +               dmac: dma-controller@11820000 {
> > > > >
> > > > > Unused. Surely you can wire up scif0?
> > > >
> > > > Yes, but I don't get login prompt, as SCIF0 interrupts have
> > > > dependency on DMA reset/clocks to route the interrupts to CPU.
> > >
> > > Aha ;-)
> > >
> > > So you need to enable the DMA clock and deassert the DMA reset in
> > > the clock/reset driver, and mark them critical.
> >
> > For CLK, already framework is providing critical clock support, which turns on the clk at the start.
> > But for reset there is no support for critical reset in the reset framework.
> >
> > you mean handle this in SoC specific driver for DMA deassert like[1]
> > DEF_RST_INIT_DEASSERTED during boot??
> >
> > Or
> >
> > Create a critical reset table in the SoC specific driver like clk and
> > explicitly deassert the resets in CPG core driver during probe??
> 
> The latter sounds simpler to me...

OK.

> 
> You also have to avoid the DMAC is reset is ever being asserted again.

Agreed.


> 
> > Note:
> > For Suspend to RAM, marking critical clock/critical reset won't solve
> > the issue as we need to explicitly turn on DMA CLK/dessert reset for routing SCIF0 irq to CPU.
> 
> So you need to add suspendresume support to the clock driver, to enable the clock and deassert the
> reset during resume?

Will send patches for supporting critical reset and enabling critical clks for RZ/G2L
Family.

Cheers,
Biju

Re: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Thu, 5 Mar 2026 at 16:18, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Tue, 3 Feb 2026 at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > Document the device tree bindings for the Renesas RZ/G3L SoC Clock
> > > Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has 5
> > > clocks compared to 1 clock on other SoCs.
> > >
> > > Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock,
> > > module
> > > clock outputs, as listed in section 4.4.2 ("Clock List r1.00") and add
> > > Reset definitions referring to registers CPG_RST_* in Section 4.4.3
> > > ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
> > >
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > > --- a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > @@ -28,19 +28,30 @@ properties:
> > >        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
> > >        - renesas,r9a07g054-cpg # RZ/V2L
> > >        - renesas,r9a08g045-cpg # RZ/G3S
> > > +      - renesas,r9a08g046-cpg # RZ/G3L
> > >        - renesas,r9a09g011-cpg # RZ/V2M
> > >
> > >    reg:
> > >      maxItems: 1
> > >
> > >    clocks:
> > > -    maxItems: 1
> > > +    minItems: 1
> > > +    items:
> > > +      - description: Clock source to CPG can be either from external clock
> > > +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> > > +      - description: ETH0 TXC clock input
> > > +      - description: ETH0 RXC clock input
> > > +      - description: ETH1 TXC clock input
> > > +      - description: ETH1 RXC clock input
> > >
> > >    clock-names:
> > > -    description:
> > > -      Clock source to CPG can be either from external clock input (EXCLK) or
> > > -      crystal oscillator (XIN/XOUT).
> > > -    const: extal
> > > +    minItems: 1
> > > +    items:
> > > +      - const: extal
> > > +      - const: eth0_txc_tx_clk
> > > +      - const: eth0_rxc_rx_clk
> > > +      - const: eth1_txc_tx_clk
> > > +      - const: eth1_rxc_rx_clk
> >
> > Are you sure about these four clocks? On which pins are they input?
>
> From Figure 4.4-5 Block Diagram of the Deformed Clock System (4), page 789
>
> These clks are external source clks connected to CPG_ETH_SSEL mux for
> selecting rx/tx clks.
>
> In RGMII case, currently on RZ/G3L SMARC EVK:
>
> For Tx: we select DIV_ETH0_TR (SEL_ETH0A_SET)
> For Rx: we select ETH0_RXC_RX_CLK_IN (SEL_ETH0B_SET)

Sure, these clocks are indeed shown in that Figure, and referenced in
the CPG_ETH_SSEL register documentation, but where do they originate
from? On which pins are they supplied?

> > > --- /dev/null
> > > +++ b/include/dt-bindings/clock/r9a08g046-cpg.h
> > > @@ -0,0 +1,343 @@
> > > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > + *
> > > + * Copyright (C) 2026 Renesas Electronics Corp.
> > > + */
> > > +#ifndef __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> > > +#define __DT_BINDINGS_CLOCK_R9A08G046_CPG_H__
> > > +
> > > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > > +
> > > +/* R9A08G046 CPG Core Clocks */
> >
> > [...]
> >
> > > +#define R9A08G046_OSCCLK               52
> > > +#define R9A08G046_OSCCLK2              53
> > > +#define R9A08G046_CLK_P4_DIV2          54
> >
> > CLK_P4_DIV2 looks like a purely internal clock to me.
>
> Page 3918 Figure 7.9-1 Block Diagram of CAN-FD
>
> Peripheral clk,
> RAM clk,
> CAN external clk
>
> Then, CANFD clk which is DIV2 clk of Peripheral clk, so thought of
> modelling this as Core clk. I may be wrong here??
>
> Maybe I will drop this now and revisit later when we add support for CANFD??

That may be the better option.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 13 March 2026 14:06
> Subject: Re: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC
> 
> Hi Biju,
> 
> On Thu, 5 Mar 2026 at 16:18, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, 3 Feb 2026
> > > at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > >
> > > > Document the device tree bindings for the Renesas RZ/G3L SoC Clock
> > > > Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has
> > > > 5 clocks compared to 1 clock on other SoCs.
> > > >
> > > > Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock,
> > > > module clock outputs, as listed in section 4.4.2 ("Clock List
> > > > r1.00") and add Reset definitions referring to registers CPG_RST_*
> > > > in Section 4.4.3
> > > > ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
> > > >
> > > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > >
> > > > ---
> > > > a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.ya
> > > > +++ ml
> > > > @@ -28,19 +28,30 @@ properties:
> > > >        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
> > > >        - renesas,r9a07g054-cpg # RZ/V2L
> > > >        - renesas,r9a08g045-cpg # RZ/G3S
> > > > +      - renesas,r9a08g046-cpg # RZ/G3L
> > > >        - renesas,r9a09g011-cpg # RZ/V2M
> > > >
> > > >    reg:
> > > >      maxItems: 1
> > > >
> > > >    clocks:
> > > > -    maxItems: 1
> > > > +    minItems: 1
> > > > +    items:
> > > > +      - description: Clock source to CPG can be either from external clock
> > > > +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> > > > +      - description: ETH0 TXC clock input
> > > > +      - description: ETH0 RXC clock input
> > > > +      - description: ETH1 TXC clock input
> > > > +      - description: ETH1 RXC clock input
> > > >
> > > >    clock-names:
> > > > -    description:
> > > > -      Clock source to CPG can be either from external clock input (EXCLK) or
> > > > -      crystal oscillator (XIN/XOUT).
> > > > -    const: extal
> > > > +    minItems: 1
> > > > +    items:
> > > > +      - const: extal
> > > > +      - const: eth0_txc_tx_clk
> > > > +      - const: eth0_rxc_rx_clk
> > > > +      - const: eth1_txc_tx_clk
> > > > +      - const: eth1_rxc_rx_clk
> > >
> > > Are you sure about these four clocks? On which pins are they input?
> >
> > From Figure 4.4-5 Block Diagram of the Deformed Clock System (4), page
> > 789
> >
> > These clks are external source clks connected to CPG_ETH_SSEL mux for
> > selecting rx/tx clks.
> >
> > In RGMII case, currently on RZ/G3L SMARC EVK:
> >
> > For Tx: we select DIV_ETH0_TR (SEL_ETH0A_SET) For Rx: we select
> > ETH0_RXC_RX_CLK_IN (SEL_ETH0B_SET)
> 
> Sure, these clocks are indeed shown in that Figure, and referenced in the CPG_ETH_SSEL register
> documentation, but where do they originate from? On which pins are they supplied?

Figure 6.3-1 Block Diagram of the Ethernet Interface 

and

1.3.3 Clock Pin Specifications
Table 1.3-3 List of Pin Functions (1/2)

For Rx this clock is supplied by PHY on the RZ/G3L SMARC SoM Module.
RZ_ETH0_RXC is the pin.
 
For Tx this clock is supplied by the SoC(RZ_ETH0_TXC)

Cheers,
Biju

Re: [PATCH v3 05/10] dt-bindings: clock: Document RZ/G3L SoC

[Geert Uytterhoeven]

Hi Biju,

On Fri, 13 Mar 2026 at 15:35, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > On Thu, 5 Mar 2026 at 16:18, Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > From: Geert Uytterhoeven <geert@linux-m68k.org> On Tue, 3 Feb 2026
> > > > at 11:30, Biju <biju.das.au@gmail.com> wrote:
> > > > > From: Biju Das <biju.das.jz@bp.renesas.com>
> > > > >
> > > > > Document the device tree bindings for the Renesas RZ/G3L SoC Clock
> > > > > Pulse Generator (CPG). RZ/G3L CPG is similar to RZ/G2L CPG but has
> > > > > 5 clocks compared to 1 clock on other SoCs.
> > > > >
> > > > > Also define RZ/G3L (R9A08G046) Clock Pulse Generator Core Clock,
> > > > > module clock outputs, as listed in section 4.4.2 ("Clock List
> > > > > r1.00") and add Reset definitions referring to registers CPG_RST_*
> > > > > in Section 4.4.3
> > > > > ("Register") of the RZ/G3L Hardware User's Manual (Rev.1.00 Oct, 2025).
> > > > >
> > > > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > >
> > > > > ---
> > > > > a/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
> > > > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.ya
> > > > > +++ ml
> > > > > @@ -28,19 +28,30 @@ properties:
> > > > >        - renesas,r9a07g044-cpg # RZ/G2{L,LC}
> > > > >        - renesas,r9a07g054-cpg # RZ/V2L
> > > > >        - renesas,r9a08g045-cpg # RZ/G3S
> > > > > +      - renesas,r9a08g046-cpg # RZ/G3L
> > > > >        - renesas,r9a09g011-cpg # RZ/V2M
> > > > >
> > > > >    reg:
> > > > >      maxItems: 1
> > > > >
> > > > >    clocks:
> > > > > -    maxItems: 1
> > > > > +    minItems: 1
> > > > > +    items:
> > > > > +      - description: Clock source to CPG can be either from external clock
> > > > > +                     input (EXCLK) or crystal oscillator (XIN/XOUT).
> > > > > +      - description: ETH0 TXC clock input
> > > > > +      - description: ETH0 RXC clock input
> > > > > +      - description: ETH1 TXC clock input
> > > > > +      - description: ETH1 RXC clock input
> > > > >
> > > > >    clock-names:
> > > > > -    description:
> > > > > -      Clock source to CPG can be either from external clock input (EXCLK) or
> > > > > -      crystal oscillator (XIN/XOUT).
> > > > > -    const: extal
> > > > > +    minItems: 1
> > > > > +    items:
> > > > > +      - const: extal
> > > > > +      - const: eth0_txc_tx_clk
> > > > > +      - const: eth0_rxc_rx_clk
> > > > > +      - const: eth1_txc_tx_clk
> > > > > +      - const: eth1_rxc_rx_clk
> > > >
> > > > Are you sure about these four clocks? On which pins are they input?
> > >
> > > From Figure 4.4-5 Block Diagram of the Deformed Clock System (4), page
> > > 789
> > >
> > > These clks are external source clks connected to CPG_ETH_SSEL mux for
> > > selecting rx/tx clks.
> > >
> > > In RGMII case, currently on RZ/G3L SMARC EVK:
> > >
> > > For Tx: we select DIV_ETH0_TR (SEL_ETH0A_SET) For Rx: we select
> > > ETH0_RXC_RX_CLK_IN (SEL_ETH0B_SET)
> >
> > Sure, these clocks are indeed shown in that Figure, and referenced in the CPG_ETH_SSEL register
> > documentation, but where do they originate from? On which pins are they supplied?
>
> Figure 6.3-1 Block Diagram of the Ethernet Interface
>
> and
>
> 1.3.3 Clock Pin Specifications
> Table 1.3-3 List of Pin Functions (1/2)
>
> For Rx this clock is supplied by PHY on the RZ/G3L SMARC SoM Module.
> RZ_ETH0_RXC is the pin.
>
> For Tx this clock is supplied by the SoC(RZ_ETH0_TXC)

OK, thanks! So these are fine.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds