[PATCH 0/5] pinctrl: sunxi: fix A523 GPIO IRQ blunder

[PATCH 0/5] pinctrl: sunxi: fix A523 GPIO IRQ blunder

[Andre Przywara]

When playing around with an Allwinner A527 board, I noticed that the
GPIO IRQ operation was broken, evident by not working SD card detect
functionality. The GPIO line reflected the CD pin correctly (as shown in
/sys/kernel/debug/gpio), but the core code just wouldn't react to those
changes.
This is admittedly mostly my fault, due to misunderstanding the IRQ
assocication in the original A523 DT submission.

Digging a bit deeper I found three bugs around this whole operation:
1) The A523 was marked as needing the "irq_read_needs_mux" workaround,
   even though this is not true. This itself wouldn't be too critical, if
   not:
2) The irq_read_needs_mux workaround routine assumes that the IRQ mux is
   always using value 0x6, which is not true for newer SoCs (D1, A523).
3) The association between GPIO IRQ banks and their interrupts is
   off-by-one for the A523. Interrupts are triggered, but the wrong ones.

This series fixes all those issues. Due to dependencies between DT and
code this is a bit involved:
- Patch 2/5 drops the irq_read_needs_mux workaround for the non-affected
  SoCs, which fixes one part of the problem by masking bug #2 above.
- Patch 4/5 adds the missing IRQ line for the (non-implemented!) PortA
  GPIO bank to the DT, which corrects the IRQ association.

Those two patches alone are fixing the immediate issue. If people agree,
these should be taken ASAP, I added Fixes: lines for the backports.

However there is more:
- The DT binding only describes 10 IRQs for the A523, so patch 3/5
  corrects that value, to make the new DT pass DT validation.
- The pinctrl code would only expect 10 IRQs, so would now be missing
  the one for the last bank (PortK). Patch 5/5 fixes that number, but
  is more elaborate since it needs now to cater for old DTs carrying
  just 10 interrupts. Not too happy or convinced about that workaround,
  eager to hear about better solutions here. Please note that no board
  so far uses PortK interrupts, so this isn't too criticial right now.
- For good measure, patch 1/5 fixes the workaround to cope with IRQ mux
  values other than 0x6. This is now more robust, not requiring to know
  the IRQ mux value at all, also saving one MMIO read and fixing a
  potential race with other pinctrl mux code.

This applies on top of v7.0-rc5 (really the .get_direction callback
fix[1] merged into v7.0-rc3), plus the two patches from Michal's series[2],
which I assume would be applied shortly.

Please have a look and test, especially on A523/A527/T527 boards!

Cheers,
Andre

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit?id=01e10d0272b9
[2] https://lore.kernel.org/linux-sunxi/20260320-rc2-boot-hang-v6-0-74dca70dd60e@mmpsystems.pl

Andre Przywara (5):
  pinctrl: sunxi: Rework IRQ remuxing to avoid fixed mux value
  pinctrl: sunxi: Remove unneeded IRQ remuxing for some SoCs
  dt-bindings: pinctrl: sun55i-a523: increase IRQ bank number
  arm64: dts: allwinner: a523: Add missing GPIO interrupt
  pinctrl: sunxi: a523: add missing IRQ bank (plus old DT workaround)

 .../allwinner,sun55i-a523-pinctrl.yaml        |  8 ++--
 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi |  3 +-
 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c     |  2 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c     |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c   |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c   |  3 +-
 drivers/pinctrl/sunxi/pinctrl-sunxi.c         | 45 ++++++++++++-------
 drivers/pinctrl/sunxi/pinctrl-sunxi.h         |  1 -
 9 files changed, 37 insertions(+), 28 deletions(-)


base-commit: c369299895a591d96745d6492d4888259b004a9e
prerequisite-patch-id: dcb1e8190ce649778193c3b391f759d4bcba9a28
prerequisite-patch-id: e003cee1830cf260b932fd6503a62270a1930310
-- 
2.43.0

[PATCH 1/5] pinctrl: sunxi: Rework IRQ remuxing to avoid fixed mux value

[Andre Przywara]

Some Allwinner SoCs cannot read the state of a GPIO line when the pin is
muxed to the IRQ function. To access that state anyway, we temporarily
mux that pin back to GPIO input, then return it to the IRQ mux
afterwards. This code assumes that the IRQ mux value is 0x6, even though
newer SoCs (D1/T113/A523/...) encode the IRQ mux with 0xe.

Avoid hardcoding the different IRQ mux values by saving the programmed
value before switching to GPIO input, then restoring the saved value
afterwards. This makes the code robust against future changes of the IRQ
mux value. This also avoids calling the sunxi_pmx_set() function twice,
each of which does a read/modify/write operation, fenced in by the pctl
lock. The new code takes the lock around the whole operation, which is
also safer since it avoids (probably theoretical) races against other
code touching the mux register meanwhile.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/pinctrl/sunxi/pinctrl-sunxi.c | 23 ++++++++++++++++-------
 drivers/pinctrl/sunxi/pinctrl-sunxi.h |  1 -
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index d3042e0c9712..6a86b7989b25 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -997,18 +997,27 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
 	struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
 	bool set_mux = pctl->desc->irq_read_needs_mux &&
 		gpiochip_line_is_irq(chip, offset);
-	u32 pin = offset + chip->base;
+	u32 mreg, mshift, mmask, mval;
 	u32 reg, shift, mask, val;
+	unsigned long flags;
 
 	sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
+	if (!set_mux)
+		return (readl(pctl->membase + reg) & mask) >> shift;
 
-	if (set_mux)
-		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
-
+	/*
+	 * Some SoCs don't read the GPIO value registers correctly
+	 * when the pinmux is not set to GPIO_INPUT. Temporarily switch
+	 * to that mux, to read the correct value.
+	 */
+	sunxi_mux_reg(pctl, offset, &mreg, &mshift, &mmask);
+	raw_spin_lock_irqsave(&pctl->lock, flags);
+	mval = readl(pctl->membase + mreg);
+	writel((mval & ~mmask) | SUN4I_FUNC_INPUT << mshift,
+	       pctl->membase + mreg);
 	val = (readl(pctl->membase + reg) & mask) >> shift;
-
-	if (set_mux)
-		sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
+	writel(mval, pctl->membase + mreg);
+	raw_spin_unlock_irqrestore(&pctl->lock, flags);
 
 	return val;
 }
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
index 0daf7600e2fb..ec7c977655b5 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h
@@ -85,7 +85,6 @@
 #define IO_BIAS_MASK		GENMASK(3, 0)
 
 #define SUN4I_FUNC_INPUT	0
-#define SUN4I_FUNC_IRQ		6
 #define SUN4I_FUNC_DISABLED_OLD 7
 #define SUN4I_FUNC_DISABLED_NEW 15
 
-- 
2.43.0

Re: [PATCH 1/5] pinctrl: sunxi: Rework IRQ remuxing to avoid fixed mux value

[Chen-Yu Tsai]

On Mon, Mar 23, 2026 at 7:02 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> Some Allwinner SoCs cannot read the state of a GPIO line when the pin is
> muxed to the IRQ function. To access that state anyway, we temporarily
> mux that pin back to GPIO input, then return it to the IRQ mux
> afterwards. This code assumes that the IRQ mux value is 0x6, even though
> newer SoCs (D1/T113/A523/...) encode the IRQ mux with 0xe.
>
> Avoid hardcoding the different IRQ mux values by saving the programmed
> value before switching to GPIO input, then restoring the saved value
> afterwards. This makes the code robust against future changes of the IRQ
> mux value. This also avoids calling the sunxi_pmx_set() function twice,
> each of which does a read/modify/write operation, fenced in by the pctl
> lock. The new code takes the lock around the whole operation, which is
> also safer since it avoids (probably theoretical) races against other
> code touching the mux register meanwhile.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>

[PATCH 2/5] pinctrl: sunxi: Remove unneeded IRQ remuxing for some SoCs

[Andre Przywara]

The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when
that line is muxed for IRQ triggering (muxval 6), but only if it's
explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this
behaviour, so we added a optional workaround, triggered by a quirk bit,
which triggers remuxing the pin when it's configured for IRQ, while we
need to read its value.

For some reasons this quirk flag was copied over to newer SoCs, even
though they don't show this behaviour, and the GPIO data register
reflects the true GPIO state even with a pin configured to muxval 6
(IRQ). The workaround is just more costly, but doesn't break otherwise,
so this was probably never noticed by anyone.
Experiments confirm that the H5, H6, H616 and A523 do not need this
workaround, they show the GPIO line value with both muxval 0 and 6.

Remove the unneeded quirk from those SoC's pinctrl driver description.
This should have no obvious effect on the H5, H6, H616 (other than
being more efficient), but the workaround is broken for the A523, so
it fixes (one part of the) interrupt operation there.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GPIO ports")
---
 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c     | 2 --
 drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c     | 1 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c   | 1 -
 drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 1 -
 drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c   | 1 -
 5 files changed, 6 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
index 669793c6578e..56ce0f78d4ba 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
@@ -533,7 +533,6 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
 	.pins = sun50i_h5_pins,
 	.npins = ARRAY_SIZE(sun50i_h5_pins),
 	.irq_banks = 2,
-	.irq_read_needs_mux = true,
 	.disable_strict_mode = true,
 };
 
@@ -541,7 +540,6 @@ static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
 	.pins = sun50i_h5_pins,
 	.npins = ARRAY_SIZE(sun50i_h5_pins),
 	.irq_banks = 3,
-	.irq_read_needs_mux = true,
 	.disable_strict_mode = true,
 };
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
index 517118341316..22f3d3875316 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
@@ -589,7 +589,6 @@ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
 	.npins = ARRAY_SIZE(h6_pins),
 	.irq_banks = 4,
 	.irq_bank_map = h6_irq_bank_map,
-	.irq_read_needs_mux = true,
 	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
 };
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
index ecf6d2438e21..48cf114505e0 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
@@ -875,7 +875,6 @@ static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
 	.npins = ARRAY_SIZE(h616_pins),
 	.irq_banks = ARRAY_SIZE(h616_irq_bank_map),
 	.irq_bank_map = h616_irq_bank_map,
-	.irq_read_needs_mux = true,
 	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
 };
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c
index 69cd2b4ebd7d..462aa1c4a5fa 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c
@@ -26,7 +26,6 @@ static const u8 a523_r_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
 static struct sunxi_pinctrl_desc a523_r_pinctrl_data = {
 	.irq_banks = ARRAY_SIZE(a523_r_irq_bank_map),
 	.irq_bank_map = a523_r_irq_bank_map,
-	.irq_read_needs_mux = true,
 	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
 	.pin_base = PL_BASE,
 };
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
index 7d2308c37d29..b6f78f1f30ac 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
@@ -26,7 +26,6 @@ static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
 static struct sunxi_pinctrl_desc a523_pinctrl_data = {
 	.irq_banks = ARRAY_SIZE(a523_irq_bank_map),
 	.irq_bank_map = a523_irq_bank_map,
-	.irq_read_needs_mux = true,
 	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
 };
 
-- 
2.43.0

Re: [PATCH 2/5] pinctrl: sunxi: Remove unneeded IRQ remuxing for some SoCs

[Chen-Yu Tsai]

On Mon, Mar 23, 2026 at 7:02 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The Allwinner A10 and H3 SoCs cannot read the state of a GPIO line when
> that line is muxed for IRQ triggering (muxval 6), but only if it's
> explicitly muxed for GPIO input (muxval 0). Other SoCs do not show this
> behaviour, so we added a optional workaround, triggered by a quirk bit,
> which triggers remuxing the pin when it's configured for IRQ, while we
> need to read its value.
>
> For some reasons this quirk flag was copied over to newer SoCs, even
> though they don't show this behaviour, and the GPIO data register
> reflects the true GPIO state even with a pin configured to muxval 6
> (IRQ). The workaround is just more costly, but doesn't break otherwise,
> so this was probably never noticed by anyone.
> Experiments confirm that the H5, H6, H616 and A523 do not need this
> workaround, they show the GPIO line value with both muxval 0 and 6.
>
> Remove the unneeded quirk from those SoC's pinctrl driver description.
> This should have no obvious effect on the H5, H6, H616 (other than
> being more efficient), but the workaround is broken for the A523, so
> it fixes (one part of the) interrupt operation there.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Fixes: b8a51e95b376 ("pinctrl: sunxi: Add support for the secondary A523 GPIO ports")

Acked-by: Chen-Yu Tsai <wens@kernel.org>

[PATCH 3/5] dt-bindings: pinctrl: sun55i-a523: increase IRQ bank number

[Andre Przywara]

The Allwinner A523 SoC implements 10 GPIO banks in the first pinctrl
instance, but it skips the first bank (PortA), so their index goes from
1 to 10. The same is actually true for the IRQ banks: there are registers
for 11 banks, though the first bank is not implemented (RAZ/WI).
In contrast to previous SoCs, the count of the IRQ banks starts with this
first unimplemented bank, so we need to provide an interrupt for it.
And indeed the A523 user manual lists an interrupt number for PortA, so we
need to increase the maximum number of interrupts per pin controller to 11,
to be able to assign the correct interrupt number for each bank.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 .../bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml   | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml
index 154e03da8ce9..f87b8274cc37 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml
@@ -34,7 +34,7 @@ properties:
 
   interrupts:
     minItems: 2
-    maxItems: 10
+    maxItems: 11
     description:
       One interrupt per external interrupt bank supported on the
       controller, sorted by bank number ascending order.
@@ -61,7 +61,7 @@ properties:
       bank found in the controller
     $ref: /schemas/types.yaml#/definitions/uint32-array
     minItems: 2
-    maxItems: 10
+    maxItems: 11
 
 patternProperties:
   # It's pretty scary, but the basic idea is that:
@@ -130,8 +130,8 @@ allOf:
     then:
       properties:
         interrupts:
-          minItems: 10
-          maxItems: 10
+          minItems: 11
+          maxItems: 11
 
   - if:
       properties:
-- 
2.43.0

Re: [PATCH 3/5] dt-bindings: pinctrl: sun55i-a523: increase IRQ bank number

[Chen-Yu Tsai]

On Mon, Mar 23, 2026 at 7:02 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The Allwinner A523 SoC implements 10 GPIO banks in the first pinctrl
> instance, but it skips the first bank (PortA), so their index goes from
> 1 to 10. The same is actually true for the IRQ banks: there are registers
> for 11 banks, though the first bank is not implemented (RAZ/WI).
> In contrast to previous SoCs, the count of the IRQ banks starts with this
> first unimplemented bank, so we need to provide an interrupt for it.
> And indeed the A523 user manual lists an interrupt number for PortA, so we
> need to increase the maximum number of interrupts per pin controller to 11,
> to be able to assign the correct interrupt number for each bank.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>

Re: [PATCH 3/5] dt-bindings: pinctrl: sun55i-a523: increase IRQ bank number

[Rob Herring (Arm)]

On Mon, 23 Mar 2026 12:01:49 +0100, Andre Przywara wrote:
> The Allwinner A523 SoC implements 10 GPIO banks in the first pinctrl
> instance, but it skips the first bank (PortA), so their index goes from
> 1 to 10. The same is actually true for the IRQ banks: there are registers
> for 11 banks, though the first bank is not implemented (RAZ/WI).
> In contrast to previous SoCs, the count of the IRQ banks starts with this
> first unimplemented bank, so we need to provide an interrupt for it.
> And indeed the A523 user manual lists an interrupt number for PortA, so we
> need to increase the maximum number of interrupts per pin controller to 11,
> to be able to assign the correct interrupt number for each bank.
> 
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  .../bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml   | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 4/5] arm64: dts: allwinner: a523: Add missing GPIO interrupt

[Andre Przywara]

Even though the Allwinner A523 SoC implements 10 GPIO banks, it has
actually registers for 11 IRQ banks, and even an interrupt assigned to
the first, non-implemented IRQ bank.
Add that first interrupt to the list of GPIO interrupts, to correct the
association between IRQs and GPIO banks.

This fixes GPIO IRQ operation on boards with A523 SoCs, as seen by
broken SD card detect functionality, for instance.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Fixes: 35ac96f79664 ("arm64: dts: allwinner: Add Allwinner A523 .dtsi file")
---
 arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 9335977751e2..cea5b166c00f 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -128,7 +128,8 @@ gpu: gpu@1800000 {
 		pio: pinctrl@2000000 {
 			compatible = "allwinner,sun55i-a523-pinctrl";
 			reg = <0x2000000 0x800>;
-			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
-- 
2.43.0

Re: [PATCH 4/5] arm64: dts: allwinner: a523: Add missing GPIO interrupt

[Chen-Yu Tsai]

On Mon, Mar 23, 2026 at 7:02 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> Even though the Allwinner A523 SoC implements 10 GPIO banks, it has
> actually registers for 11 IRQ banks, and even an interrupt assigned to
> the first, non-implemented IRQ bank.
> Add that first interrupt to the list of GPIO interrupts, to correct the
> association between IRQs and GPIO banks.
>
> This fixes GPIO IRQ operation on boards with A523 SoCs, as seen by
> broken SD card detect functionality, for instance.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> Fixes: 35ac96f79664 ("arm64: dts: allwinner: Add Allwinner A523 .dtsi file")

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>

[PATCH 5/5] pinctrl: sunxi: a523: add missing IRQ bank (plus old DT workaround)

[Andre Przywara]

The Allwinner A532 SoC implements 10 GPIO banks, each of which is
interrupt capable. However the first bank (PortA) is skipped, so the
indicies of those banks range from 1 to 10, not 0 to 9.
We described the skipped bank correctly, but missed that for the IRQ
banks, where we rely on the IRQ bank index to be aligned with the MMIO
register offset, starting at 0x200.

Correct that by increasing the number of IRQ banks to 11, to cover both
the first skipped one, but also the last one (PortK). This fixes a bug
where the interrupt numbers would be off-by-one, due to that
mis-enumeration.
The big caveat is that now old DTs break the kernel, since they only
provide 10 interrupts, and the driver bails out entirely due to the last
missing one. So add a workaround for this particular case, where we
detect the requirement for 11 banks, but only 10 interrupts provided,
and continue with 10 IRQs, albeit emitting a warning about a DT update.
This would still be broken in terms of interrupt assignment, but it was
broken the whole time before, so it's not a regression.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c |  2 +-
 drivers/pinctrl/sunxi/pinctrl-sunxi.c       | 22 +++++++++++++--------
 2 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
index b6f78f1f30ac..a1d157de53d2 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
@@ -17,7 +17,7 @@ static const u8 a523_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] =
 /*	  PA  PB  PC  PD  PE  PF  PG  PH  PI  PJ  PK */
 	{  0, 15, 17, 24, 16,  7, 15, 20, 17, 28, 24 };
 
-static const unsigned int a523_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
+static const unsigned int a523_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
 
 static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
 /*	  PA  PB  PC  PD  PE  PF  PG  PH  PI  PJ  PK */
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
index 6a86b7989b25..ffee79397590 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
@@ -19,6 +19,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_clk.h>
+#include <linux/of_irq.h>
 #include <linux/platform_device.h>
 #include <linux/regulator/consumer.h>
 #include <linux/slab.h>
@@ -1582,6 +1583,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
 	struct sunxi_pinctrl *pctl;
 	struct pinmux_ops *pmxops;
 	int i, ret, last_pin, pin_idx;
+	int num_irq_banks;
 	struct clk *clk;
 
 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
@@ -1715,16 +1717,20 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
 		goto gpiochip_error;
 	}
 
-	pctl->irq = devm_kcalloc(&pdev->dev,
-				 pctl->desc->irq_banks,
-				 sizeof(*pctl->irq),
-				 GFP_KERNEL);
+	num_irq_banks = pctl->desc->irq_banks;
+	/* Workaround for old A523 DT, exposing one less interrupt. */
+	if (num_irq_banks == 11 && of_irq_count(node) < 11) {
+		num_irq_banks = 10;
+		pr_warn("Not enough PIO interrupts, please update your DT!\n");
+	}
+	pctl->irq = devm_kcalloc(&pdev->dev, num_irq_banks,
+				 sizeof(*pctl->irq), GFP_KERNEL);
 	if (!pctl->irq) {
 		ret = -ENOMEM;
 		goto gpiochip_error;
 	}
 
-	for (i = 0; i < pctl->desc->irq_banks; i++) {
+	for (i = 0; i < num_irq_banks; i++) {
 		pctl->irq[i] = platform_get_irq(pdev, i);
 		if (pctl->irq[i] < 0) {
 			ret = pctl->irq[i];
@@ -1733,7 +1739,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
 	}
 
 	pctl->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev),
-						pctl->desc->irq_banks * IRQ_PER_BANK,
+						num_irq_banks * IRQ_PER_BANK,
 						&sunxi_pinctrl_irq_domain_ops, pctl);
 	if (!pctl->domain) {
 		dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
@@ -1741,7 +1747,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
 		goto gpiochip_error;
 	}
 
-	for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
+	for (i = 0; i < (num_irq_banks * IRQ_PER_BANK); i++) {
 		int irqno = irq_create_mapping(pctl->domain, i);
 
 		irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
@@ -1751,7 +1757,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
 		irq_set_chip_data(irqno, pctl);
 	}
 
-	for (i = 0; i < pctl->desc->irq_banks; i++) {
+	for (i = 0; i < num_irq_banks; i++) {
 		/* Mask and clear all IRQs before registering a handler */
 		writel(0, pctl->membase +
 			  sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
-- 
2.43.0

Re: [PATCH 5/5] pinctrl: sunxi: a523: add missing IRQ bank (plus old DT workaround)

[Chen-Yu Tsai]

On Mon, Mar 23, 2026 at 7:02 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> The Allwinner A532 SoC implements 10 GPIO banks, each of which is
> interrupt capable. However the first bank (PortA) is skipped, so the
> indicies of those banks range from 1 to 10, not 0 to 9.
> We described the skipped bank correctly, but missed that for the IRQ
> banks, where we rely on the IRQ bank index to be aligned with the MMIO
> register offset, starting at 0x200.
>
> Correct that by increasing the number of IRQ banks to 11, to cover both
> the first skipped one, but also the last one (PortK). This fixes a bug
> where the interrupt numbers would be off-by-one, due to that
> mis-enumeration.
> The big caveat is that now old DTs break the kernel, since they only
> provide 10 interrupts, and the driver bails out entirely due to the last
> missing one. So add a workaround for this particular case, where we
> detect the requirement for 11 banks, but only 10 interrupts provided,
> and continue with 10 IRQs, albeit emitting a warning about a DT update.
> This would still be broken in terms of interrupt assignment, but it was
> broken the whole time before, so it's not a regression.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
>  drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c |  2 +-
>  drivers/pinctrl/sunxi/pinctrl-sunxi.c       | 22 +++++++++++++--------
>  2 files changed, 15 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
> index b6f78f1f30ac..a1d157de53d2 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
> @@ -17,7 +17,7 @@ static const u8 a523_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] =
>  /*       PA  PB  PC  PD  PE  PF  PG  PH  PI  PJ  PK */
>         {  0, 15, 17, 24, 16,  7, 15, 20, 17, 28, 24 };
>
> -static const unsigned int a523_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
> +static const unsigned int a523_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };

Actually you don't even need this, since this is a linear mapping.

From sunxi_irq_hw_bank_num():

    if (!desc->irq_bank_map)
            return bank;
    else
            return desc->irq_bank_map[bank];

>  static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
>  /*       PA  PB  PC  PD  PE  PF  PG  PH  PI  PJ  PK */
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> index 6a86b7989b25..ffee79397590 100644
> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
> @@ -19,6 +19,7 @@
>  #include <linux/irqdomain.h>
>  #include <linux/of.h>
>  #include <linux/of_clk.h>
> +#include <linux/of_irq.h>
>  #include <linux/platform_device.h>
>  #include <linux/regulator/consumer.h>
>  #include <linux/slab.h>
> @@ -1582,6 +1583,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>         struct sunxi_pinctrl *pctl;
>         struct pinmux_ops *pmxops;
>         int i, ret, last_pin, pin_idx;
> +       int num_irq_banks;
>         struct clk *clk;
>
>         pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
> @@ -1715,16 +1717,20 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>                 goto gpiochip_error;
>         }
>
> -       pctl->irq = devm_kcalloc(&pdev->dev,
> -                                pctl->desc->irq_banks,
> -                                sizeof(*pctl->irq),
> -                                GFP_KERNEL);
> +       num_irq_banks = pctl->desc->irq_banks;
> +       /* Workaround for old A523 DT, exposing one less interrupt. */
> +       if (num_irq_banks == 11 && of_irq_count(node) < 11) {
> +               num_irq_banks = 10;
> +               pr_warn("Not enough PIO interrupts, please update your DT!\n");
> +       }

I would probably make the check universal, and also use dev_warn().

    num_irq_banks = of_irq_count(node);
    if (num_irq_banks != pctrl->desc->irq_banks) {
        dev_warn(&pdev->dev, "Incorrect number of PIO interrupts,
please update your DT!\n");
        num_irq_banks = min(num_irq_banks, pctrl->desc->irq_banks);
    }

Otherwise,

Reviewed-by: Chen-Yu Tsai <wens@kernel.org>


> +       pctl->irq = devm_kcalloc(&pdev->dev, num_irq_banks,
> +                                sizeof(*pctl->irq), GFP_KERNEL);
>         if (!pctl->irq) {
>                 ret = -ENOMEM;
>                 goto gpiochip_error;
>         }
>
> -       for (i = 0; i < pctl->desc->irq_banks; i++) {
> +       for (i = 0; i < num_irq_banks; i++) {
>                 pctl->irq[i] = platform_get_irq(pdev, i);
>                 if (pctl->irq[i] < 0) {
>                         ret = pctl->irq[i];
> @@ -1733,7 +1739,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>         }
>
>         pctl->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev),
> -                                               pctl->desc->irq_banks * IRQ_PER_BANK,
> +                                               num_irq_banks * IRQ_PER_BANK,
>                                                 &sunxi_pinctrl_irq_domain_ops, pctl);
>         if (!pctl->domain) {
>                 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
> @@ -1741,7 +1747,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>                 goto gpiochip_error;
>         }
>
> -       for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
> +       for (i = 0; i < (num_irq_banks * IRQ_PER_BANK); i++) {
>                 int irqno = irq_create_mapping(pctl->domain, i);
>
>                 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
> @@ -1751,7 +1757,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>                 irq_set_chip_data(irqno, pctl);
>         }
>
> -       for (i = 0; i < pctl->desc->irq_banks; i++) {
> +       for (i = 0; i < num_irq_banks; i++) {
>                 /* Mask and clear all IRQs before registering a handler */
>                 writel(0, pctl->membase +
>                           sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
> --
> 2.43.0
>
>

Re: [PATCH 5/5] pinctrl: sunxi: a523: add missing IRQ bank (plus old DT workaround)

[Andre Przywara]

Hi Chen-Yu,

many thanks for having a look!

On 3/23/26 18:41, Chen-Yu Tsai wrote:
> On Mon, Mar 23, 2026 at 7:02 PM Andre Przywara <andre.przywara@arm.com> wrote:
>>
>> The Allwinner A532 SoC implements 10 GPIO banks, each of which is
>> interrupt capable. However the first bank (PortA) is skipped, so the
>> indicies of those banks range from 1 to 10, not 0 to 9.
>> We described the skipped bank correctly, but missed that for the IRQ
>> banks, where we rely on the IRQ bank index to be aligned with the MMIO
>> register offset, starting at 0x200.
>>
>> Correct that by increasing the number of IRQ banks to 11, to cover both
>> the first skipped one, but also the last one (PortK). This fixes a bug
>> where the interrupt numbers would be off-by-one, due to that
>> mis-enumeration.
>> The big caveat is that now old DTs break the kernel, since they only
>> provide 10 interrupts, and the driver bails out entirely due to the last
>> missing one. So add a workaround for this particular case, where we
>> detect the requirement for 11 banks, but only 10 interrupts provided,
>> and continue with 10 IRQs, albeit emitting a warning about a DT update.
>> This would still be broken in terms of interrupt assignment, but it was
>> broken the whole time before, so it's not a regression.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>>   drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c |  2 +-
>>   drivers/pinctrl/sunxi/pinctrl-sunxi.c       | 22 +++++++++++++--------
>>   2 files changed, 15 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
>> index b6f78f1f30ac..a1d157de53d2 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sun55i-a523.c
>> @@ -17,7 +17,7 @@ static const u8 a523_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] =
>>   /*       PA  PB  PC  PD  PE  PF  PG  PH  PI  PJ  PK */
>>          {  0, 15, 17, 24, 16,  7, 15, 20, 17, 28, 24 };
>>
>> -static const unsigned int a523_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
>> +static const unsigned int a523_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 };
> 
> Actually you don't even need this, since this is a linear mapping.
> 
>  From sunxi_irq_hw_bank_num():
> 
>      if (!desc->irq_bank_map)
>              return bank;
>      else
>              return desc->irq_bank_map[bank];

Yeah, I was wondering about that as well, and there are other cases were 
we wouldn't need the map, espeically in the PRMC pinctrl instances. I 
might add a separate patch for that.

>>   static const u8 a523_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
>>   /*       PA  PB  PC  PD  PE  PF  PG  PH  PI  PJ  PK */
>> diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> index 6a86b7989b25..ffee79397590 100644
>> --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
>> @@ -19,6 +19,7 @@
>>   #include <linux/irqdomain.h>
>>   #include <linux/of.h>
>>   #include <linux/of_clk.h>
>> +#include <linux/of_irq.h>
>>   #include <linux/platform_device.h>
>>   #include <linux/regulator/consumer.h>
>>   #include <linux/slab.h>
>> @@ -1582,6 +1583,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>>          struct sunxi_pinctrl *pctl;
>>          struct pinmux_ops *pmxops;
>>          int i, ret, last_pin, pin_idx;
>> +       int num_irq_banks;
>>          struct clk *clk;
>>
>>          pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
>> @@ -1715,16 +1717,20 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>>                  goto gpiochip_error;
>>          }
>>
>> -       pctl->irq = devm_kcalloc(&pdev->dev,
>> -                                pctl->desc->irq_banks,
>> -                                sizeof(*pctl->irq),
>> -                                GFP_KERNEL);
>> +       num_irq_banks = pctl->desc->irq_banks;
>> +       /* Workaround for old A523 DT, exposing one less interrupt. */
>> +       if (num_irq_banks == 11 && of_irq_count(node) < 11) {
>> +               num_irq_banks = 10;
>> +               pr_warn("Not enough PIO interrupts, please update your DT!\n");
>> +       }
> 
> I would probably make the check universal, and also use dev_warn().
> 
>      num_irq_banks = of_irq_count(node);
>      if (num_irq_banks != pctrl->desc->irq_banks) {
>          dev_warn(&pdev->dev, "Incorrect number of PIO interrupts,
> please update your DT!\n");
>          num_irq_banks = min(num_irq_banks, pctrl->desc->irq_banks);
>      }

Ah, nice one, that's of course much better. But I see that there is 
other code using desc->irq_banks, and if the array allocation is 
different, that will not end well. I will check how we can use 
num_irq_banks there as well.

Thanks!
Andre



> 
> Otherwise,
> 
> Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
> 
> 
>> +       pctl->irq = devm_kcalloc(&pdev->dev, num_irq_banks,
>> +                                sizeof(*pctl->irq), GFP_KERNEL);
>>          if (!pctl->irq) {
>>                  ret = -ENOMEM;
>>                  goto gpiochip_error;
>>          }
>>
>> -       for (i = 0; i < pctl->desc->irq_banks; i++) {
>> +       for (i = 0; i < num_irq_banks; i++) {
>>                  pctl->irq[i] = platform_get_irq(pdev, i);
>>                  if (pctl->irq[i] < 0) {
>>                          ret = pctl->irq[i];
>> @@ -1733,7 +1739,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>>          }
>>
>>          pctl->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev),
>> -                                               pctl->desc->irq_banks * IRQ_PER_BANK,
>> +                                               num_irq_banks * IRQ_PER_BANK,
>>                                                  &sunxi_pinctrl_irq_domain_ops, pctl);
>>          if (!pctl->domain) {
>>                  dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
>> @@ -1741,7 +1747,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>>                  goto gpiochip_error;
>>          }
>>
>> -       for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
>> +       for (i = 0; i < (num_irq_banks * IRQ_PER_BANK); i++) {
>>                  int irqno = irq_create_mapping(pctl->domain, i);
>>
>>                  irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
>> @@ -1751,7 +1757,7 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
>>                  irq_set_chip_data(irqno, pctl);
>>          }
>>
>> -       for (i = 0; i < pctl->desc->irq_banks; i++) {
>> +       for (i = 0; i < num_irq_banks; i++) {
>>                  /* Mask and clear all IRQs before registering a handler */
>>                  writel(0, pctl->membase +
>>                            sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
>> --
>> 2.43.0
>>
>>