[PATCH 00/12] arm64: dts: qcom: qcs6490: Radxa Dragon Q6A feature enablement and fixes

[PATCH 00/12] arm64: dts: qcom: qcs6490: Radxa Dragon Q6A feature enablement and fixes

[Xilin Wu]

This series brings the Radxa Dragon Q6A (QCS6490) board support up to
date with the latest official firmware and enables additional hardware.

Fixes and alignment with latest firmware:

- Allow QSEECOM for UEFI/efivars support
- Align reserved-memory with the latest firmware memory map
- Drop QSPI node now restricted by TrustZone
- Switch to board-specific CDSP firmware matching new WP boot firmware
- Correct GPIO_27 label

Hardware enablement:

- Enable UFS controller (Gear-4 Rate-A)
- Enable USB 3.0 and HDMI (via DP-to-HDMI bridge)
- Mark secondary USB controller as wakeup source
- Add I2C aliases for CCI buses

Variant for LPASS CPU audio:

- Factor out common board dtsi for sharing between variants
- Add dt-bindings for Dragon Q6A sound card
- Add LPASS CPU audio variant for EL2 direct hardware access

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
Stephen Chen (3):
      arm64: dts: qcom: kodiak: Add I2C aliases for CCI
      arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Correct GPIO_27 label
      arm64: dts: qcom: kodiak: Mark secondary USB controller as wakeup source

Xilin Wu (9):
      firmware: qcom: scm: Allow QSEECOM for Radxa Dragon Q6A
      arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller
      arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports
      arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Use board-specific CDSP firmware
      arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Drop QSPI node and reserve its pins
      arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Align reserved-memory with latest firmware map
      arm64: dts: qcom: qcs6490-radxa-dragon-q6a: factor out common board dtsi
      ASoC: dt-bindings: google,sc7280-herobrine: Add Radxa Dragon Q6A sound card
      arm64: dts: qcom: qcs6490-radxa-dragon-q6a: add LPASS CPU audio variant

 .../bindings/sound/google,sc7280-herobrine.yaml    |    9 +-
 arch/arm64/boot/dts/qcom/Makefile                  |    1 +
 arch/arm64/boot/dts/qcom/kodiak.dtsi               |    5 +
 .../qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts    |  131 +++
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 1047 +-----------------
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi    | 1137 ++++++++++++++++++++
 drivers/firmware/qcom/qcom_scm.c                   |    1 +
 7 files changed, 1300 insertions(+), 1031 deletions(-)
---
base-commit: 816f193dd0d95246f208590924dd962b192def78
change-id: 20260407-dragon-q6a-feat-fixes-6a30f6ba8b18

Best regards,
--  
Xilin Wu <sophon@radxa.com>

[PATCH 01/12] firmware: qcom: scm: Allow QSEECOM for Radxa Dragon Q6A

[Xilin Wu]

add "radxa,dragon-q6a" as compatible device for QSEECOM

This is required to get access to efivars and uefi boot loader support.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 drivers/firmware/qcom/qcom_scm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 9b06a69d3a6d..55b18463560a 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -2319,6 +2319,7 @@ static const struct of_device_id qcom_scm_qseecom_allowlist[] __maybe_unused = {
 	{ .compatible = "qcom,x1e80100-crd" },
 	{ .compatible = "qcom,x1e80100-qcp" },
 	{ .compatible = "qcom,x1p42100-crd" },
+	{ .compatible = "radxa,dragon-q6a" },
 	{ }
 };
 

-- 
2.53.0

Re: [PATCH 01/12] firmware: qcom: scm: Allow QSEECOM for Radxa Dragon Q6A

[Dmitry Baryshkov]

On Tue, Apr 07, 2026 at 11:19:53PM +0800, Xilin Wu wrote:
> add "radxa,dragon-q6a" as compatible device for QSEECOM
> 
> This is required to get access to efivars and uefi boot loader support.
> 
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---
>  drivers/firmware/qcom/qcom_scm.c | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

[PATCH 02/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller

[Xilin Wu]

Add and enable UFS related nodes for this board.

Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design
limitations. UFS on this board is stable when working at Gear-4 Rate-A.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index bb5a42b038f1..c961d3ec625f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -959,6 +959,29 @@ &uart5 {
 	status = "okay";
 };
 
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l7b_2p96>;
+	vcc-max-microamp = <800000>;
+	vccq-supply = <&vreg_l9b_1p2>;
+	vccq-max-microamp = <900000>;
+	vccq2-supply = <&vreg_l9b_1p2>;
+	vccq2-max-microamp = <1300000>;
+
+	/* Gear-4 Rate-B is unstable due to board */
+	/* and UFS module design limitations */
+	limit-gear-rate = "rate-a";
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l10c_0p88>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+
+	status = "okay";
+};
+
 &usb_2 {
 	dr_mode = "host";
 

-- 
2.53.0

Re: [PATCH 02/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller

[Konrad Dybcio]

On 4/7/26 5:19 PM, Xilin Wu wrote:
> Add and enable UFS related nodes for this board.
> 
> Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design
> limitations. UFS on this board is stable when working at Gear-4 Rate-A.
> 
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---
>  .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> index bb5a42b038f1..c961d3ec625f 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> @@ -959,6 +959,29 @@ &uart5 {
>  	status = "okay";
>  };
>  
> +&ufs_mem_hc {
> +	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
> +	vcc-supply = <&vreg_l7b_2p96>;
> +	vcc-max-microamp = <800000>;
> +	vccq-supply = <&vreg_l9b_1p2>;
> +	vccq-max-microamp = <900000>;
> +	vccq2-supply = <&vreg_l9b_1p2>;
> +	vccq2-max-microamp = <1300000>;
> +
> +	/* Gear-4 Rate-B is unstable due to board */
> +	/* and UFS module design limitations */

/* it's a bit weird to add two single-line */
/* comments near one another for a single paragraph */

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 02/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable UFS controller

[Xilin Wu]

On 4/8/2026 4:59 PM, Konrad Dybcio wrote:
> On 4/7/26 5:19 PM, Xilin Wu wrote:
>> Add and enable UFS related nodes for this board.
>>
>> Note that UFS Gear-4 Rate-B is unstable due to board and UFS module design
>> limitations. UFS on this board is stable when working at Gear-4 Rate-A.
>>
>> Signed-off-by: Xilin Wu <sophon@radxa.com>
>> ---
>>   .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 23 ++++++++++++++++++++++
>>   1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> index bb5a42b038f1..c961d3ec625f 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> @@ -959,6 +959,29 @@ &uart5 {
>>   	status = "okay";
>>   };
>>   
>> +&ufs_mem_hc {
>> +	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
>> +	vcc-supply = <&vreg_l7b_2p96>;
>> +	vcc-max-microamp = <800000>;
>> +	vccq-supply = <&vreg_l9b_1p2>;
>> +	vccq-max-microamp = <900000>;
>> +	vccq2-supply = <&vreg_l9b_1p2>;
>> +	vccq2-max-microamp = <1300000>;
>> +
>> +	/* Gear-4 Rate-B is unstable due to board */
>> +	/* and UFS module design limitations */
> 
> /* it's a bit weird to add two single-line */
> /* comments near one another for a single paragraph */

Ack. I'll change the comment to single-line in v2.
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Konrad
> 


-- 
Best regards,
Xilin Wu <sophon@radxa.com>

[PATCH 03/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports

[Xilin Wu]

This board doesn't feature a regular Type-C port. The usb_1_qmpphy's
RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0
pair is connected to the RA620 DP-to-HDMI bridge.

Add and enable the nodes for the features to work.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 152 +++++++++++++++++++++
 1 file changed, 152 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index c961d3ec625f..8d649b3a1cfa 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -111,6 +111,71 @@ usb2_3_connector: endpoint {
 		};
 	};
 
+	usb3_con: connector {
+		compatible = "usb-a-connector";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				usb3_con_hs_in: endpoint {
+					remote-endpoint = <&usb_1_dwc3_hs>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				usb3_con_ss_in: endpoint {
+					remote-endpoint = <&usb_1_qmpphy_out_usb>;
+				};
+			};
+		};
+	};
+
+	hdmi-bridge {
+		compatible = "radxa,ra620";
+
+		pinctrl-0 = <&dp_hot_plug_det>;
+		pinctrl-names = "default";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				hdmi_bridge_in: endpoint {
+					remote-endpoint = <&usb_1_qmpphy_out_dp>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				hdmi_bridge_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
+		};
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_bridge_out>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -521,6 +586,21 @@ &lpass_va_macro {
 	status = "okay";
 };
 
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp {
+	sound-name-prefix = "Display Port0";
+
+	status = "okay";
+};
+
+&mdss_dp_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
 &pcie0 {
 	perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
 	wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
@@ -738,6 +818,22 @@ &sound {
 			"AMIC2", "MIC BIAS2",
 			"TX SWR_ADC1", "ADC2_OUTPUT";
 
+	dp0-dai-link {
+		link-name = "DP0 Playback";
+
+		codec {
+			sound-dai = <&mdss_dp>;
+		};
+
+		cpu {
+			sound-dai = <&q6apmbedai DISPLAY_PORT_RX_0>;
+		};
+
+		platform {
+			sound-dai = <&q6apm>;
+		};
+	};
+
 	wcd-playback-dai-link {
 		link-name = "WCD Playback";
 
@@ -982,6 +1078,58 @@ &ufs_mem_phy {
 	status = "okay";
 };
 
+&usb_1 {
+	dr_mode = "host";
+
+	status = "okay";
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&usb3_con_hs_in>;
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l10c_0p88>;
+	vdda33-supply = <&vreg_l2b_3p072>;
+	vdda18-supply = <&vreg_l1c_1p8>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vreg_l6b_1p2>;
+	vdda-pll-supply = <&vreg_l1b_0p912>;
+
+	/delete-property/ orientation-switch;
+
+	status = "okay";
+
+	ports {
+		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/delete-node/ endpoint;
+
+			/* RX0/TX0 is statically connected to RA620 bridge */
+			usb_1_qmpphy_out_dp: endpoint@0 {
+				reg = <0>;
+
+				data-lanes = <0 1>;
+				remote-endpoint = <&hdmi_bridge_in>;
+			};
+
+			/* RX1/TX1 is statically connected to USB-A port */
+			usb_1_qmpphy_out_usb: endpoint@1 {
+				reg = <1>;
+
+				data-lanes = <2 3>;
+				remote-endpoint = <&usb3_con_ss_in>;
+			};
+		};
+	};
+};
+
 &usb_2 {
 	dr_mode = "host";
 
@@ -1048,6 +1196,10 @@ &venus {
 };
 
 /* PINCTRL - additions to nodes defined in sc7280.dtsi */
+&dp_hot_plug_det {
+	bias-disable;
+};
+
 &pcie0_clkreq_n {
 	bias-pull-up;
 	drive-strength = <2>;

-- 
2.53.0

Re: [PATCH 03/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports

[Konrad Dybcio]

On 4/7/26 5:19 PM, Xilin Wu wrote:
> This board doesn't feature a regular Type-C port. The usb_1_qmpphy's

I guess the receptacle on board is power-only?

> RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0
> pair is connected to the RA620 DP-to-HDMI bridge.
> 
> Add and enable the nodes for the features to work.
> 
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---
>  .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 152 +++++++++++++++++++++
>  1 file changed, 152 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> index c961d3ec625f..8d649b3a1cfa 100644
> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
> @@ -111,6 +111,71 @@ usb2_3_connector: endpoint {
>  		};
>  	};
>  
> +	usb3_con: connector {

This label is unused

> +		compatible = "usb-a-connector";

No vbus-supply?

[...]

> +&mdss_dp {
> +	sound-name-prefix = "Display Port0";

Hmmmmm.. other platforms call it "DisplayPort0" (without a space)..
But I suppose this name needs to match UCM..

We'd also normally push this property to the SoC DTSI

Konrad

Re: [PATCH 03/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports

[Xilin Wu]

On 4/8/2026 5:03 PM, Konrad Dybcio wrote:
> On 4/7/26 5:19 PM, Xilin Wu wrote:
>> This board doesn't feature a regular Type-C port. The usb_1_qmpphy's
> 
> I guess the receptacle on board is power-only?

Yes. The Type-C port is power only.

> 
>> RX1/TX1 pair is statically connected to the USB-A port, while its RX0/TX0
>> pair is connected to the RA620 DP-to-HDMI bridge.
>>
>> Add and enable the nodes for the features to work.
>>
>> Signed-off-by: Xilin Wu <sophon@radxa.com>
>> ---
>>   .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 152 +++++++++++++++++++++
>>   1 file changed, 152 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> index c961d3ec625f..8d649b3a1cfa 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
>> @@ -111,6 +111,71 @@ usb2_3_connector: endpoint {
>>   		};
>>   	};
>>   
>> +	usb3_con: connector {
> 
> This label is unused

Ack. I will remove the label.

> 
>> +		compatible = "usb-a-connector";
> 
> No vbus-supply?

It's supplied by vcc_5v_peri. I'll add it in v2.

> 
> [...]
> 
>> +&mdss_dp {
>> +	sound-name-prefix = "Display Port0";
> 
> Hmmmmm.. other platforms call it "DisplayPort0" (without a space)..
> But I suppose this name needs to match UCM..
> 
> We'd also normally push this property to the SoC DTSI

Actually I don't think the name is used in UCM. I can rename it and push 
the property to SoC DTSI if necessary.

> 
> Konrad
> 


-- 
Best regards,
Xilin Wu <sophon@radxa.com>

Re: [PATCH 03/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Enable USB 3.0 and HDMI ports

[Konrad Dybcio]

On 4/12/26 5:14 AM, Xilin Wu wrote:
> On 4/8/2026 5:03 PM, Konrad Dybcio wrote:
>> On 4/7/26 5:19 PM, Xilin Wu wrote:
>>> This board doesn't feature a regular Type-C port. The usb_1_qmpphy's
>>
>> I guess the receptacle on board is power-only?
> 
> Yes. The Type-C port is power only.

[...]

>>> +&mdss_dp {
>>> +    sound-name-prefix = "Display Port0";
>>
>> Hmmmmm.. other platforms call it "DisplayPort0" (without a space)..
>> But I suppose this name needs to match UCM..
>>
>> We'd also normally push this property to the SoC DTSI
> 
> Actually I don't think the name is used in UCM. I can rename it and push the property to SoC DTSI if necessary.

Let's do that

Konrad

[PATCH 04/12] arm64: dts: qcom: kodiak: Add I2C aliases for CCI

[Xilin Wu]

From: Stephen Chen <stephen@radxa.com>

Add I2C bus aliases (i2c16-i2c19) for the CCI (Camera Control Interface)
I2C buses, allowing a stable numbering of these buses independent of
probe order.

Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 arch/arm64/boot/dts/qcom/kodiak.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 988ca5f7c8a0..3a30126af3d4 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -57,6 +57,10 @@ aliases {
 		i2c13 = &i2c13;
 		i2c14 = &i2c14;
 		i2c15 = &i2c15;
+		i2c16 = &cci0_i2c0;
+		i2c17 = &cci0_i2c1;
+		i2c18 = &cci1_i2c0;
+		i2c19 = &cci1_i2c1;
 		mmc1 = &sdhc_1;
 		mmc2 = &sdhc_2;
 		spi0 = &spi0;

-- 
2.53.0

[PATCH 05/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Use board-specific CDSP firmware

[Xilin Wu]

The official boot firmware for Dragon Q6A has been switched to the
Qualcomm WP (Windows) boot firmware. Use the matching board-specific
CDSP firmware instead of the generic one so that the DSP firmware stack
remains compatible with the new boot firmware.

The corresponding custom DSP firmware has already been added to
linux-firmware:

https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/882

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 8d649b3a1cfa..91f1b4f57915 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -783,7 +783,7 @@ &remoteproc_adsp {
 };
 
 &remoteproc_cdsp {
-	firmware-name = "qcom/qcs6490/cdsp.mbn";
+	firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
 	status = "okay";
 };
 

-- 
2.53.0

Re: [PATCH 05/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Use board-specific CDSP firmware

[Konrad Dybcio]

On 4/7/26 5:19 PM, Xilin Wu wrote:
> The official boot firmware for Dragon Q6A has been switched to the
> Qualcomm WP (Windows) boot firmware. Use the matching board-specific
> CDSP firmware instead of the generic one so that the DSP firmware stack
> remains compatible with the new boot firmware.
> 
> The corresponding custom DSP firmware has already been added to
> linux-firmware:
> 
> https://gitlab.com/kernel-firmware/linux-firmware/-/merge_requests/882
> 
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---

It's a little shaky given you say it must be changed to remain compatible..

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH 06/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Drop QSPI node and reserve its pins

[Xilin Wu]

The latest official boot firmware configures TrustZone to restrict
direct access to the QSPI controller. Any attempt to access it from
the non-secure world causes an immediate board reset.

Remove the QSPI flash node and its associated pinctrl states, mark
GPIOs 12-17 as reserved, and protect the QSPI clocks in the GCC
node to prevent the kernel from touching this hardware.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 60 +++-------------------
 1 file changed, 7 insertions(+), 53 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 91f1b4f57915..8d6bb4b0724b 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -513,6 +513,9 @@ &gcc {
 			   <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
 			   <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
 			   <GCC_MSS_SNOC_AXI_CLK>,
+			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+			   <GCC_QSPI_CORE_CLK>,
+			   <GCC_QSPI_CORE_CLK_SRC>,
 			   <GCC_SEC_CTRL_CLK_SRC>,
 			   <GCC_WPSS_AHB_BDG_MST_CLK>,
 			   <GCC_WPSS_AHB_CLK>,
@@ -745,28 +748,6 @@ &pon_pwrkey {
 	status = "okay";
 };
 
-&qspi {
-	/* It's not possible to use QSPI with iommu */
-	/* due to an error in qcom_smmu_write_s2cr */
-	/delete-property/ iommus;
-
-	pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>,
-				<&qspi_data1>, <&qspi_data23>;
-	pinctrl-1 = <&qspi_sleep>;
-	pinctrl-names = "default", "sleep";
-
-	status = "okay";
-
-	spi_flash: flash@0 {
-		compatible = "winbond,w25q256", "jedec,spi-nor";
-		reg = <0>;
-
-		spi-max-frequency = <104000000>;
-		spi-tx-bus-width = <4>;
-		spi-rx-bus-width = <4>;
-	};
-};
-
 &qupv3_id_0 {
 	firmware-name = "qcom/qcm6490/qupv3fw.elf";
 	status = "okay";
@@ -906,6 +887,10 @@ wcd_tx: codec@0,3 {
 };
 
 &tlmm {
+	/*
+	 * 12-17: reserved for QSPI flash
+	 */
+	gpio-reserved-ranges = <12 6>;
 	gpio-line-names =
 		/* GPIO_0 ~ GPIO_3 */
 		"PIN_13", "PIN_15", "", "",
@@ -1024,12 +1009,6 @@ pcie1_wake_n: pcie1-wake-n-state {
 		bias-pull-up;
 	};
 
-	qspi_sleep: qspi-sleep-state {
-		pins = "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17";
-		function = "gpio";
-		output-disable;
-	};
-
 	sd_cd: sd-cd-state {
 		pins = "gpio91";
 		function = "gpio";
@@ -1210,31 +1189,6 @@ &pcie1_clkreq_n {
 	drive-strength = <2>;
 };
 
-&qspi_clk {
-	bias-disable;
-	drive-strength = <16>;
-};
-
-&qspi_cs0 {
-	bias-disable;
-	drive-strength = <8>;
-};
-
-&qspi_data0 {
-	bias-disable;
-	drive-strength = <8>;
-};
-
-&qspi_data1 {
-	bias-disable;
-	drive-strength = <8>;
-};
-
-&qspi_data23 {
-	bias-disable;
-	drive-strength = <8>;
-};
-
 &sdc1_clk {
 	bias-disable;
 	drive-strength = <16>;

-- 
2.53.0

[PATCH 07/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Correct GPIO_27 label

[Xilin Wu]

From: Stephen Chen <stephen@radxa.com>

The label of GPIO_27 is wrong. Fix it.

Fixes: ef254b12ec60 ("arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A")
Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 8d6bb4b0724b..fe3f60f8ed5a 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -905,7 +905,7 @@ &tlmm {
 		/* GPIO_20 ~ GPIO_23 */
 		"", "", "PIN_8", "PIN_10",
 		/* GPIO_24 ~ GPIO_27 */
-		"PIN_3", "PIN_5", "PIN_16", "PIN_27",
+		"PIN_3", "PIN_5", "PIN_16", "PIN_18",
 		/* GPIO_28 ~ GPIO_31 */
 		"PIN_31", "PIN_11", "PIN_32", "PIN_29",
 		/* GPIO_32 ~ GPIO_35 */

-- 
2.53.0

Re: [PATCH 07/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Correct GPIO_27 label

[Konrad Dybcio]

On 4/7/26 5:19 PM, Xilin Wu wrote:
> From: Stephen Chen <stephen@radxa.com>
> 
> The label of GPIO_27 is wrong. Fix it.
> 
> Fixes: ef254b12ec60 ("arm64: dts: qcom: qcs6490: Introduce Radxa Dragon Q6A")
> Signed-off-by: Stephen Chen <stephen@radxa.com>
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH 08/12] arm64: dts: qcom: kodiak: Mark secondary USB controller as wakeup source

[Xilin Wu]

From: Stephen Chen <stephen@radxa.com>

Mark the secondary USB controller (usb_2) as a wakeup source so that it
can be used to wake the system from suspend.

Signed-off-by: Stephen Chen <stephen@radxa.com>
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 arch/arm64/boot/dts/qcom/kodiak.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi
index 3a30126af3d4..940ec799e905 100644
--- a/arch/arm64/boot/dts/qcom/kodiak.dtsi
+++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi
@@ -4404,6 +4404,7 @@ usb_2: usb@8c00000 {
 			phy-names = "usb2-phy";
 			maximum-speed = "high-speed";
 			usb-role-switch;
+			wakeup-source;
 
 			port {
 				usb2_role_switch: endpoint {

-- 
2.53.0

Re: [PATCH 08/12] arm64: dts: qcom: kodiak: Mark secondary USB controller as wakeup source

[Konrad Dybcio]

On 4/7/26 5:20 PM, Xilin Wu wrote:
> From: Stephen Chen <stephen@radxa.com>
> 
> Mark the secondary USB controller (usb_2) as a wakeup source so that it
> can be used to wake the system from suspend.
> 
> Signed-off-by: Stephen Chen <stephen@radxa.com>
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

[PATCH 09/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: Align reserved-memory with latest firmware map

[Xilin Wu]

The current board DTS no longer matches the reserved-memory carveouts
used by the latest official Dragon Q6A firmware. Update the memory map
to keep the DTS in sync with firmware expectations.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 43 +++++++++-------------
 1 file changed, 17 insertions(+), 26 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index fe3f60f8ed5a..5679f38de5b3 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -22,7 +22,9 @@
 #include "qcs6490-audioreach.dtsi"
 
 /delete-node/ &adsp_mem;
+/delete-node/ &adsp_rpc_remote_heap_mem;
 /delete-node/ &cdsp_mem;
+/delete-node/ &gpu_zap_mem;
 /delete-node/ &ipa_fw_mem;
 /delete-node/ &mpss_mem;
 /delete-node/ &remoteproc_mpss;
@@ -33,7 +35,6 @@
 /delete-node/ &wlan_ce_mem;
 /delete-node/ &wlan_fw_mem;
 /delete-node/ &wpss_mem;
-/delete-node/ &xbl_mem;
 
 / {
 	model = "Radxa Dragon Q6A";
@@ -193,43 +194,33 @@ user-led {
 	};
 
 	reserved-memory {
-		xbl_mem: xbl@80700000 {
-			reg = <0x0 0x80700000 0x0 0x100000>;
+		lpass_ml_mem: lpass-ml@81800000 {
+			reg = <0x0 0x81800000 0x0 0xf00000>;
 			no-map;
 		};
 
-		cdsp_secure_heap_mem: cdsp-secure-heap@81800000 {
-			reg = <0x0 0x81800000 0x0 0x1e00000>;
+		cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
+			reg = <0x0 0x82700000 0x0 0x10000>;
 			no-map;
 		};
 
-		camera_mem: camera@84300000 {
-			reg = <0x0 0x84300000 0x0 0x500000>;
+		adsp_mem: adsp@8b800000 {
+			reg = <0x0 0x8b800000 0x0 0x2800000>;
 			no-map;
 		};
 
-		adsp_mem: adsp@84800000 {
-			reg = <0x0 0x84800000 0x0 0x2800000>;
+		cdsp_mem: cdsp@8e000000 {
+			reg = <0x0 0x8e000000 0x0 0x1e00000>;
 			no-map;
 		};
 
-		cdsp_mem: cdsp@87000000 {
-			reg = <0x0 0x87000000 0x0 0x1e00000>;
+		video_mem: video@8fe00000 {
+			reg = <0x0 0x8fe00000 0x0 0x500000>;
 			no-map;
 		};
 
-		video_mem: video@88e00000 {
-			reg = <0x0 0x88e00000 0x0 0x700000>;
-			no-map;
-		};
-
-		cvp_mem: cvp@89500000 {
-			reg = <0x0 0x89500000 0x0 0x500000>;
-			no-map;
-		};
-
-		gpu_microcode_mem: gpu-microcode@89a00000 {
-			reg = <0x0 0x89a00000 0x0 0x2000>;
+		gpu_zap_mem: zap@90300000 {
+			reg = <0x0 0x90300000 0x0 0x5000>;
 			no-map;
 		};
 
@@ -249,12 +240,12 @@ qtee_mem: qtee@c1300000 {
 		};
 
 		trusted_apps_mem: trusted-apps@c1800000 {
-			reg = <0x0 0xc1800000 0x0 0x1c00000>;
+			reg = <0x0 0xc1800000 0x0 0x2200000>;
 			no-map;
 		};
 
-		debug_vm_mem: debug-vm@d0600000 {
-			reg = <0x0 0xd0600000 0x0 0x100000>;
+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
+			reg = <0x0 0xc6500000 0x0 0x800000>;
 			no-map;
 		};
 	};

-- 
2.53.0

[PATCH 10/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: factor out common board dtsi

[Xilin Wu]

Move the common Radxa Dragon Q6A board description from
qcs6490-radxa-dragon-q6a.dts to a new qcs6490-radxa-dragon-q6a.dtsi so
it can be shared by multiple board variants.

Keep the existing Audioreach-based qcs6490-radxa-dragon-q6a.dts as the
default configuration by including the new common .dtsi and
qcs6490-audioreach.dtsi.

No functional change intended.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts     | 1135 +------------------
 .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi    | 1137 ++++++++++++++++++++
 2 files changed, 1139 insertions(+), 1133 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
index 5679f38de5b3..f52328fbaef9 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
@@ -1,568 +1,13 @@
 // SPDX-License-Identifier: BSD-3-Clause
 /*
- * Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd.
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
  */
 
 /dts-v1/;
 
-/* PM7250B is configured to use SID8/9 */
-#define PM7250B_SID 8
-#define PM7250B_SID1 9
-
-#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
-#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
-#include <dt-bindings/leds/common.h>
-#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
-#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
-#include "kodiak.dtsi"
-#include "pm7250b.dtsi"
-#include "pm7325.dtsi"
-#include "pm8350c.dtsi" /* PM7350C */
-#include "pmk8350.dtsi" /* PMK7325 */
+#include "qcs6490-radxa-dragon-q6a.dtsi"
 #include "qcs6490-audioreach.dtsi"
 
-/delete-node/ &adsp_mem;
-/delete-node/ &adsp_rpc_remote_heap_mem;
-/delete-node/ &cdsp_mem;
-/delete-node/ &gpu_zap_mem;
-/delete-node/ &ipa_fw_mem;
-/delete-node/ &mpss_mem;
-/delete-node/ &remoteproc_mpss;
-/delete-node/ &remoteproc_wpss;
-/delete-node/ &rmtfs_mem;
-/delete-node/ &video_mem;
-/delete-node/ &wifi;
-/delete-node/ &wlan_ce_mem;
-/delete-node/ &wlan_fw_mem;
-/delete-node/ &wpss_mem;
-
-/ {
-	model = "Radxa Dragon Q6A";
-	compatible = "radxa,dragon-q6a", "qcom,qcm6490";
-	chassis-type = "embedded";
-
-	aliases {
-		mmc0 = &sdhc_1;
-		mmc1 = &sdhc_2;
-		serial0 = &uart5;
-	};
-
-	wcd938x: audio-codec {
-		compatible = "qcom,wcd9380-codec";
-
-		pinctrl-0 = <&wcd_default>;
-		pinctrl-names = "default";
-
-		reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
-
-		vdd-rxtx-supply = <&vreg_l18b_1p8>;
-		vdd-io-supply = <&vreg_l18b_1p8>;
-		vdd-buck-supply = <&vreg_l17b_1p8>;
-		vdd-mic-bias-supply = <&vreg_bob_3p296>;
-
-		qcom,micbias1-microvolt = <1800000>;
-		qcom,micbias2-microvolt = <1800000>;
-		qcom,micbias3-microvolt = <1800000>;
-		qcom,micbias4-microvolt = <1800000>;
-		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
-		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
-		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
-		qcom,rx-device = <&wcd_rx>;
-		qcom,tx-device = <&wcd_tx>;
-
-		qcom,hphl-jack-type-normally-closed;
-
-		#sound-dai-cells = <1>;
-	};
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	usb2_1_con: connector-0 {
-		compatible = "usb-a-connector";
-		vbus-supply = <&vcc_5v_peri>;
-
-		port {
-			usb2_1_connector: endpoint {
-				remote-endpoint = <&usb_hub_2_1>;
-			};
-		};
-	};
-
-	usb2_2_con: connector-1 {
-		compatible = "usb-a-connector";
-		vbus-supply = <&vcc_5v_peri>;
-
-		port {
-			usb2_2_connector: endpoint {
-				remote-endpoint = <&usb_hub_2_2>;
-			};
-		};
-	};
-
-	usb2_3_con: connector-2 {
-		compatible = "usb-a-connector";
-		vbus-supply = <&vcc_5v_peri>;
-
-		port {
-			usb2_3_connector: endpoint {
-				remote-endpoint = <&usb_hub_2_3>;
-			};
-		};
-	};
-
-	usb3_con: connector {
-		compatible = "usb-a-connector";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-
-				usb3_con_hs_in: endpoint {
-					remote-endpoint = <&usb_1_dwc3_hs>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				usb3_con_ss_in: endpoint {
-					remote-endpoint = <&usb_1_qmpphy_out_usb>;
-				};
-			};
-		};
-	};
-
-	hdmi-bridge {
-		compatible = "radxa,ra620";
-
-		pinctrl-0 = <&dp_hot_plug_det>;
-		pinctrl-names = "default";
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@0 {
-				reg = <0>;
-
-				hdmi_bridge_in: endpoint {
-					remote-endpoint = <&usb_1_qmpphy_out_dp>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				hdmi_bridge_out: endpoint {
-					remote-endpoint = <&hdmi_connector_in>;
-				};
-			};
-		};
-	};
-
-	hdmi-connector {
-		compatible = "hdmi-connector";
-		label = "hdmi";
-		type = "a";
-
-		port {
-			hdmi_connector_in: endpoint {
-				remote-endpoint = <&hdmi_bridge_out>;
-			};
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		pinctrl-0 = <&user_led>;
-		pinctrl-names = "default";
-
-		user-led {
-			color = <LED_COLOR_ID_BLUE>;
-			function = LED_FUNCTION_INDICATOR;
-			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
-			linux,default-trigger = "none";
-			default-state = "off";
-			panic-indicator;
-		};
-	};
-
-	reserved-memory {
-		lpass_ml_mem: lpass-ml@81800000 {
-			reg = <0x0 0x81800000 0x0 0xf00000>;
-			no-map;
-		};
-
-		cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
-			reg = <0x0 0x82700000 0x0 0x10000>;
-			no-map;
-		};
-
-		adsp_mem: adsp@8b800000 {
-			reg = <0x0 0x8b800000 0x0 0x2800000>;
-			no-map;
-		};
-
-		cdsp_mem: cdsp@8e000000 {
-			reg = <0x0 0x8e000000 0x0 0x1e00000>;
-			no-map;
-		};
-
-		video_mem: video@8fe00000 {
-			reg = <0x0 0x8fe00000 0x0 0x500000>;
-			no-map;
-		};
-
-		gpu_zap_mem: zap@90300000 {
-			reg = <0x0 0x90300000 0x0 0x5000>;
-			no-map;
-		};
-
-		tz_stat_mem: tz-stat@c0000000 {
-			reg = <0x0 0xc0000000 0x0 0x100000>;
-			no-map;
-		};
-
-		tags_mem: tags@c0100000 {
-			reg = <0x0 0xc0100000 0x0 0x1200000>;
-			no-map;
-		};
-
-		qtee_mem: qtee@c1300000 {
-			reg = <0x0 0xc1300000 0x0 0x500000>;
-			no-map;
-		};
-
-		trusted_apps_mem: trusted-apps@c1800000 {
-			reg = <0x0 0xc1800000 0x0 0x2200000>;
-			no-map;
-		};
-
-		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
-			reg = <0x0 0xc6500000 0x0 0x800000>;
-			no-map;
-		};
-	};
-
-	thermal-zones {
-		msm-skin-thermal {
-			polling-delay-passive = <0>;
-			thermal-sensors = <&pmk8350_adc_tm 2>;
-		};
-
-		quiet-thermal {
-			polling-delay-passive = <0>;
-			thermal-sensors = <&pmk8350_adc_tm 1>;
-		};
-
-		ufs-thermal {
-			polling-delay-passive = <0>;
-			thermal-sensors = <&pmk8350_adc_tm 3>;
-		};
-
-		xo-thermal {
-			polling-delay-passive = <0>;
-			thermal-sensors = <&pmk8350_adc_tm 0>;
-		};
-	};
-
-	vcc_1v8: regulator-vcc-1v8 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_1v8";
-		regulator-min-microvolt = <1800000>;
-		regulator-max-microvolt = <1800000>;
-		vin-supply = <&vcc_5v_peri>;
-
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	vcc_3v3: regulator-vcc-3v3 {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_3v3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		vin-supply = <&vcc_5v_peri>;
-
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	vcc_5v_peri: regulator-vcc-5v-peri {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_5v_peri";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		vin-supply = <&vph_pwr>;
-
-		regulator-boot-on;
-		regulator-always-on;
-	};
-
-	vph_pwr: regulator-vph-pwr {
-		compatible = "regulator-fixed";
-		regulator-name = "vph_pwr";
-		regulator-min-microvolt = <3700000>;
-		regulator-max-microvolt = <3700000>;
-
-		regulator-boot-on;
-		regulator-always-on;
-	};
-};
-
-&apps_rsc {
-	regulators-0 {
-		compatible = "qcom,pm7325-rpmh-regulators";
-		qcom,pmic-id = "b";
-
-		vdd-s1-supply = <&vph_pwr>;
-		vdd-s2-supply = <&vph_pwr>;
-		vdd-s3-supply = <&vph_pwr>;
-		vdd-s4-supply = <&vph_pwr>;
-		vdd-s5-supply = <&vph_pwr>;
-		vdd-s6-supply = <&vph_pwr>;
-		vdd-s7-supply = <&vph_pwr>;
-		vdd-s8-supply = <&vph_pwr>;
-		vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>;
-		vdd-l2-l7-supply = <&vreg_bob_3p296>;
-		vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>;
-		vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>;
-
-		vreg_s1b_1p84: smps1 {
-			regulator-name = "vreg_s1b_1p84";
-			regulator-min-microvolt = <1840000>;
-			regulator-max-microvolt = <2040000>;
-		};
-
-		vreg_s7b_0p536: smps7 {
-			regulator-name = "vreg_s7b_0p536";
-			regulator-min-microvolt = <536000>;
-			regulator-max-microvolt = <1120000>;
-		};
-
-		vreg_s8b_1p2: smps8 {
-			regulator-name = "vreg_s8b_1p2";
-			regulator-min-microvolt = <1200000>;
-			regulator-max-microvolt = <1496000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
-		};
-
-		vreg_l1b_0p912: ldo1 {
-			regulator-name = "vreg_l1b_0p912";
-			regulator-min-microvolt = <832000>;
-			regulator-max-microvolt = <920000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-							RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l2b_3p072: ldo2 {
-			regulator-name = "vreg_l2b_3p072";
-			regulator-min-microvolt = <2704000>;
-			regulator-max-microvolt = <3544000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-							RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l6b_1p2: ldo6 {
-			regulator-name = "vreg_l6b_1p2";
-			regulator-min-microvolt = <1200000>;
-			regulator-max-microvolt = <1256000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-							RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l7b_2p96: ldo7 {
-			regulator-name = "vreg_l7b_2p96";
-			regulator-min-microvolt = <2960000>;
-			regulator-max-microvolt = <2960000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-							RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l9b_1p2: ldo9 {
-			regulator-name = "vreg_l9b_1p2";
-			regulator-min-microvolt = <1200000>;
-			regulator-max-microvolt = <1304000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-						   RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l17b_1p8: ldo17 {
-			regulator-name = "vreg_l17b_1p8";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1896000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l18b_1p8: ldo18 {
-			regulator-name = "vreg_l18b_1p8";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <2000000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-always-on;
-		};
-
-		vreg_l19b_1p8: ldo19 {
-			regulator-name = "vreg_l19b_1p8";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <2000000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-						   RPMH_REGULATOR_MODE_HPM>;
-		};
-	};
-
-	regulators-1 {
-		compatible = "qcom,pm8350c-rpmh-regulators";
-		qcom,pmic-id = "c";
-
-		vdd-s1-supply = <&vph_pwr>;
-		vdd-s2-supply = <&vph_pwr>;
-		vdd-s3-supply = <&vph_pwr>;
-		vdd-s4-supply = <&vph_pwr>;
-		vdd-s5-supply = <&vph_pwr>;
-		vdd-s6-supply = <&vph_pwr>;
-		vdd-s7-supply = <&vph_pwr>;
-		vdd-s8-supply = <&vph_pwr>;
-		vdd-s9-supply = <&vph_pwr>;
-		vdd-s10-supply = <&vph_pwr>;
-		vdd-l1-l12-supply = <&vreg_s1b_1p84>;
-		vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
-		vdd-l10-supply = <&vreg_s7b_0p536>;
-		vdd-bob-supply = <&vph_pwr>;
-
-		vreg_l1c_1p8: ldo1 {
-			regulator-name = "vreg_l1c_1p8";
-			regulator-min-microvolt = <1800000>;
-			regulator-max-microvolt = <1976000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-						   RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l6c_2p96: ldo6 {
-			regulator-name = "vreg_l6c_2p96";
-			regulator-min-microvolt = <1650000>;
-			regulator-max-microvolt = <3544000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-						   RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l9c_2p96: ldo9 {
-			regulator-name = "vreg_l9c_2p96";
-			regulator-min-microvolt = <2704000>;
-			regulator-max-microvolt = <3544000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-						   RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_l10c_0p88: ldo10 {
-			regulator-name = "vreg_l10c_0p88";
-			regulator-min-microvolt = <720000>;
-			regulator-max-microvolt = <1048000>;
-			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
-			regulator-allow-set-load;
-			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
-						   RPMH_REGULATOR_MODE_HPM>;
-		};
-
-		vreg_bob_3p296: bob {
-			regulator-name = "vreg_bob_3p296";
-			regulator-min-microvolt = <3032000>;
-			regulator-max-microvolt = <3960000>;
-		};
-	};
-};
-
-&gcc {
-	protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
-			   <GCC_MSS_CFG_AHB_CLK>,
-			   <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
-			   <GCC_MSS_OFFLINE_AXI_CLK>,
-			   <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
-			   <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
-			   <GCC_MSS_SNOC_AXI_CLK>,
-			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
-			   <GCC_QSPI_CORE_CLK>,
-			   <GCC_QSPI_CORE_CLK_SRC>,
-			   <GCC_SEC_CTRL_CLK_SRC>,
-			   <GCC_WPSS_AHB_BDG_MST_CLK>,
-			   <GCC_WPSS_AHB_CLK>,
-			   <GCC_WPSS_RSCP_CLK>;
-};
-
-&gpi_dma0 {
-	status = "okay";
-};
-
-&gpi_dma1 {
-	status = "okay";
-};
-
-&gpu {
-	status = "okay";
-};
-
-&gpu_zap_shader {
-	firmware-name = "qcom/qcs6490/a660_zap.mbn";
-};
-
-/* Pin 13, 15 in GPIO header */
-&i2c0 {
-	qcom,enable-gsi-dma;
-	status = "okay";
-};
-
-/* Pin 27, 28 in GPIO header */
-&i2c2 {
-	qcom,enable-gsi-dma;
-	status = "okay";
-};
-
-/* Pin 3, 5 in GPIO header */
-&i2c6 {
-	qcom,enable-gsi-dma;
-	status = "okay";
-};
-
-&i2c10 {
-	qcom,enable-gsi-dma;
-	status = "okay";
-
-	rtc: rtc@68 {
-		compatible = "st,m41t11";
-		reg = <0x68>;
-	};
-};
-
-/* External touchscreen */
-&i2c13 {
-	qcom,enable-gsi-dma;
-	status = "okay";
-};
-
 &lpass_audiocc {
 	compatible = "qcom,qcm6490-lpassaudiocc";
 	/delete-property/ power-domains;
@@ -580,207 +25,6 @@ &lpass_va_macro {
 	status = "okay";
 };
 
-&mdss {
-	status = "okay";
-};
-
-&mdss_dp {
-	sound-name-prefix = "Display Port0";
-
-	status = "okay";
-};
-
-&mdss_dp_out {
-	data-lanes = <0 1>;
-	remote-endpoint = <&usb_dp_qmpphy_dp_in>;
-};
-
-&pcie0 {
-	perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
-	wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
-
-	pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
-	pinctrl-names = "default";
-
-	status = "okay";
-};
-
-&pcie0_phy {
-	vdda-phy-supply = <&vreg_l10c_0p88>;
-	vdda-pll-supply = <&vreg_l6b_1p2>;
-
-	status = "okay";
-};
-
-&pcie1 {
-	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
-	wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
-
-	pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
-	pinctrl-names = "default";
-
-	/* Support for QPS615 PCIe switch */
-	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
-		    <0x100 &apps_smmu 0x1c81 0x1>,
-		    <0x208 &apps_smmu 0x1c84 0x1>,
-		    <0x210 &apps_smmu 0x1c85 0x1>,
-		    <0x218 &apps_smmu 0x1c86 0x1>,
-		    <0x300 &apps_smmu 0x1c87 0x1>,
-		    <0x400 &apps_smmu 0x1c88 0x1>,
-		    <0x500 &apps_smmu 0x1c89 0x1>,
-		    <0x501 &apps_smmu 0x1c90 0x1>;
-
-	status = "okay";
-};
-
-&pcie1_phy {
-	vdda-phy-supply = <&vreg_l10c_0p88>;
-	vdda-pll-supply = <&vreg_l6b_1p2>;
-
-	status = "okay";
-};
-
-&pm7325_gpios {
-	pm7325_adc_default: adc-default-state {
-		pins = "gpio2";
-		function = PMIC_GPIO_FUNC_NORMAL;
-		bias-high-impedance;
-	};
-};
-
-&pm7325_temp_alarm {
-	io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>;
-	io-channel-names = "thermal";
-};
-
-&pmk8350_adc_tm {
-	status = "okay";
-
-	xo-therm@0 {
-		reg = <0>;
-		io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
-		qcom,ratiometric;
-		qcom,hw-settle-time-us = <200>;
-	};
-
-	quiet-therm@1 {
-		reg = <1>;
-		io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
-		qcom,ratiometric;
-		qcom,hw-settle-time-us = <200>;
-	};
-
-	msm-skin-therm@2 {
-		reg = <2>;
-		io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
-		qcom,ratiometric;
-		qcom,hw-settle-time-us = <200>;
-	};
-
-	ufs-therm@3 {
-		reg = <3>;
-		io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>;
-		qcom,ratiometric;
-		qcom,hw-settle-time-us = <200>;
-	};
-};
-
-&pmk8350_vadc {
-	pinctrl-0 = <&pm7325_adc_default>;
-	pinctrl-names = "default";
-
-	channel@3 {
-		reg = <PMK8350_ADC7_DIE_TEMP>;
-		label = "pmk7325_die_temp";
-		qcom,pre-scaling = <1 1>;
-	};
-
-	channel@44 {
-		reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
-		label = "xo_therm";
-		qcom,hw-settle-time = <200>;
-		qcom,pre-scaling = <1 1>;
-		qcom,ratiometric;
-	};
-
-	channel@103 {
-		reg = <PM7325_ADC7_DIE_TEMP>;
-		label = "pm7325_die_temp";
-		qcom,pre-scaling = <1 1>;
-	};
-
-	channel@144 {
-		reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
-		qcom,ratiometric;
-		qcom,hw-settle-time = <200>;
-		qcom,pre-scaling = <1 1>;
-		label = "quiet_therm";
-	};
-
-	channel@146 {
-		reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
-		qcom,ratiometric;
-		qcom,hw-settle-time = <200>;
-		qcom,pre-scaling = <1 1>;
-		label = "msm_skin_therm";
-	};
-
-	channel@14a {
-		/* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */
-		reg = <PM7325_ADC7_GPIO1_100K_PU>;
-		qcom,ratiometric;
-		qcom,hw-settle-time = <200>;
-		qcom,pre-scaling = <1 1>;
-		label = "ufs_therm";
-	};
-};
-
-&pon_pwrkey {
-	status = "okay";
-};
-
-&qupv3_id_0 {
-	firmware-name = "qcom/qcm6490/qupv3fw.elf";
-	status = "okay";
-};
-
-&qupv3_id_1 {
-	firmware-name = "qcom/qcm6490/qupv3fw.elf";
-	status = "okay";
-};
-
-&remoteproc_adsp {
-	firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn";
-	status = "okay";
-};
-
-&remoteproc_cdsp {
-	firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
-	status = "okay";
-};
-
-&sdhc_1 {
-	non-removable;
-	no-sd;
-	no-sdio;
-
-	vmmc-supply = <&vreg_l7b_2p96>;
-	vqmmc-supply = <&vreg_l19b_1p8>;
-
-	status = "okay";
-};
-
-&sdhc_2 {
-	pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
-	pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
-
-	vmmc-supply = <&vreg_l9c_2p96>;
-	vqmmc-supply = <&vreg_l6c_2p96>;
-
-	cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
-	status = "okay";
-};
-
 &sound {
 	compatible = "qcom,qcs6490-rb3gen2-sndcard";
 	model = "QCS6490-Radxa-Dragon-Q6A";
@@ -838,378 +82,3 @@ platform {
 		};
 	};
 };
-
-/* Pin 11, 29, 31, 32 in GPIO header */
-&spi7 {
-	qcom,enable-gsi-dma;
-	status = "okay";
-};
-
-/* Pin 19, 21, 23, 24, 26 in GPIO header */
-&spi12 {
-	qcom,enable-gsi-dma;
-	status = "okay";
-};
-
-/* Pin 22, 33, 36, 37 in GPIO header */
-&spi14 {
-	qcom,enable-gsi-dma;
-	status = "okay";
-};
-
-&swr0 {
-	status = "okay";
-
-	wcd_rx: codec@0,4 {
-		compatible = "sdw20217010d00";
-		reg = <0 4>;
-		qcom,rx-port-mapping = <1 2 3 4 5>;
-	};
-};
-
-&swr1 {
-	status = "okay";
-
-	wcd_tx: codec@0,3 {
-		compatible = "sdw20217010d00";
-		reg = <0 3>;
-		qcom,tx-port-mapping = <1 1 2 3>;
-	};
-};
-
-&tlmm {
-	/*
-	 * 12-17: reserved for QSPI flash
-	 */
-	gpio-reserved-ranges = <12 6>;
-	gpio-line-names =
-		/* GPIO_0 ~ GPIO_3 */
-		"PIN_13", "PIN_15", "", "",
-		/* GPIO_4 ~ GPIO_7 */
-		"", "", "", "",
-		/* GPIO_8 ~ GPIO_11 */
-		"PIN_27", "PIN_28", "", "",
-		/* GPIO_12 ~ GPIO_15 */
-		"", "", "", "",
-		/* GPIO_16 ~ GPIO_19 */
-		"", "", "", "",
-		/* GPIO_20 ~ GPIO_23 */
-		"", "", "PIN_8", "PIN_10",
-		/* GPIO_24 ~ GPIO_27 */
-		"PIN_3", "PIN_5", "PIN_16", "PIN_18",
-		/* GPIO_28 ~ GPIO_31 */
-		"PIN_31", "PIN_11", "PIN_32", "PIN_29",
-		/* GPIO_32 ~ GPIO_35 */
-		"", "", "", "",
-		/* GPIO_36 ~ GPIO_39 */
-		"", "", "", "",
-		/* GPIO_40 ~ GPIO_43 */
-		"", "", "", "",
-		/* GPIO_44 ~ GPIO_47 */
-		"", "", "", "",
-		/* GPIO_48 ~ GPIO_51 */
-		"PIN_21", "PIN_19", "PIN_23", "PIN_24",
-		/* GPIO_52 ~ GPIO_55 */
-		"", "", "", "PIN_26",
-		/* GPIO_56 ~ GPIO_59 */
-		"PIN_33", "PIN_22", "PIN_37", "PIN_36",
-		/* GPIO_60 ~ GPIO_63 */
-		"", "", "", "",
-		/* GPIO_64 ~ GPIO_67 */
-		"", "", "", "",
-		/* GPIO_68 ~ GPIO_71 */
-		"", "", "", "",
-		/* GPIO_72 ~ GPIO_75 */
-		"", "", "", "",
-		/* GPIO_76 ~ GPIO_79 */
-		"", "", "", "",
-		/* GPIO_80 ~ GPIO_83 */
-		"", "", "", "",
-		/* GPIO_84 ~ GPIO_87 */
-		"", "", "", "",
-		/* GPIO_88 ~ GPIO_91 */
-		"", "", "", "",
-		/* GPIO_92 ~ GPIO_95 */
-		"", "", "", "",
-		/* GPIO_96 ~ GPIO_99 */
-		"PIN_7", "PIN_12", "PIN_38", "PIN_40",
-		/* GPIO_100 ~ GPIO_103 */
-		"PIN_35", "", "", "",
-		/* GPIO_104 ~ GPIO_107 */
-		"", "", "", "",
-		/* GPIO_108 ~ GPIO_111 */
-		"", "", "", "",
-		/* GPIO_112 ~ GPIO_115 */
-		"", "", "", "",
-		/* GPIO_116 ~ GPIO_119 */
-		"", "", "", "",
-		/* GPIO_120 ~ GPIO_123 */
-		"", "", "", "",
-		/* GPIO_124 ~ GPIO_127 */
-		"", "", "", "",
-		/* GPIO_128 ~ GPIO_131 */
-		"", "", "", "",
-		/* GPIO_132 ~ GPIO_135 */
-		"", "", "", "",
-		/* GPIO_136 ~ GPIO_139 */
-		"", "", "", "",
-		/* GPIO_140 ~ GPIO_143 */
-		"", "", "", "",
-		/* GPIO_144 ~ GPIO_147 */
-		"", "", "", "",
-		/* GPIO_148 ~ GPIO_151 */
-		"", "", "", "",
-		/* GPIO_152 ~ GPIO_155 */
-		"", "", "", "",
-		/* GPIO_156 ~ GPIO_159 */
-		"", "", "", "",
-		/* GPIO_160 ~ GPIO_163 */
-		"", "", "", "",
-		/* GPIO_164 ~ GPIO_167 */
-		"", "", "", "",
-		/* GPIO_168 ~ GPIO_171 */
-		"", "", "", "",
-		/* GPIO_172 ~ GPIO_174 */
-		"", "", "";
-
-	pcie0_reset_n: pcie0-reset-n-state {
-		pins = "gpio87";
-		function = "gpio";
-		drive-strength = <2>;
-		bias-disable;
-	};
-
-	pcie0_wake_n: pcie0-wake-n-state {
-		pins = "gpio89";
-		function = "gpio";
-		drive-strength = <2>;
-		bias-pull-up;
-	};
-
-	pcie1_reset_n: pcie1-reset-n-state {
-		pins = "gpio2";
-		function = "gpio";
-		drive-strength = <2>;
-		bias-disable;
-	};
-
-	pcie1_wake_n: pcie1-wake-n-state {
-		pins = "gpio3";
-		function = "gpio";
-		drive-strength = <2>;
-		bias-pull-up;
-	};
-
-	sd_cd: sd-cd-state {
-		pins = "gpio91";
-		function = "gpio";
-		bias-pull-up;
-	};
-
-	user_led: user-led-state {
-		pins = "gpio42";
-		function = "gpio";
-		bias-pull-up;
-	};
-
-	wcd_default: wcd-reset-n-active-state {
-		pins = "gpio83";
-		function = "gpio";
-		drive-strength = <16>;
-		bias-disable;
-		output-low;
-	};
-};
-
-&uart5 {
-	status = "okay";
-};
-
-&ufs_mem_hc {
-	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
-	vcc-supply = <&vreg_l7b_2p96>;
-	vcc-max-microamp = <800000>;
-	vccq-supply = <&vreg_l9b_1p2>;
-	vccq-max-microamp = <900000>;
-	vccq2-supply = <&vreg_l9b_1p2>;
-	vccq2-max-microamp = <1300000>;
-
-	/* Gear-4 Rate-B is unstable due to board */
-	/* and UFS module design limitations */
-	limit-gear-rate = "rate-a";
-
-	status = "okay";
-};
-
-&ufs_mem_phy {
-	vdda-phy-supply = <&vreg_l10c_0p88>;
-	vdda-pll-supply = <&vreg_l6b_1p2>;
-
-	status = "okay";
-};
-
-&usb_1 {
-	dr_mode = "host";
-
-	status = "okay";
-};
-
-&usb_1_dwc3_hs {
-	remote-endpoint = <&usb3_con_hs_in>;
-};
-
-&usb_1_hsphy {
-	vdda-pll-supply = <&vreg_l10c_0p88>;
-	vdda33-supply = <&vreg_l2b_3p072>;
-	vdda18-supply = <&vreg_l1c_1p8>;
-
-	status = "okay";
-};
-
-&usb_1_qmpphy {
-	vdda-phy-supply = <&vreg_l6b_1p2>;
-	vdda-pll-supply = <&vreg_l1b_0p912>;
-
-	/delete-property/ orientation-switch;
-
-	status = "okay";
-
-	ports {
-		port@0 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/delete-node/ endpoint;
-
-			/* RX0/TX0 is statically connected to RA620 bridge */
-			usb_1_qmpphy_out_dp: endpoint@0 {
-				reg = <0>;
-
-				data-lanes = <0 1>;
-				remote-endpoint = <&hdmi_bridge_in>;
-			};
-
-			/* RX1/TX1 is statically connected to USB-A port */
-			usb_1_qmpphy_out_usb: endpoint@1 {
-				reg = <1>;
-
-				data-lanes = <2 3>;
-				remote-endpoint = <&usb3_con_ss_in>;
-			};
-		};
-	};
-};
-
-&usb_2 {
-	dr_mode = "host";
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	status = "okay";
-
-	/* Onboard USB 2.0 hub */
-	usb_hub_2_x: hub@1 {
-		compatible = "usb1a40,0101";
-		reg = <1>;
-		vdd-supply = <&vcc_5v_peri>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			port@1 {
-				reg = <1>;
-
-				usb_hub_2_1: endpoint {
-					remote-endpoint = <&usb2_1_connector>;
-				};
-			};
-
-			port@2 {
-				reg = <2>;
-
-				usb_hub_2_2: endpoint {
-					remote-endpoint = <&usb2_2_connector>;
-				};
-			};
-
-			port@3 {
-				reg = <3>;
-
-				usb_hub_2_3: endpoint {
-					remote-endpoint = <&usb2_3_connector>;
-				};
-			};
-		};
-
-		/* FCU760K Wi-Fi & Bluetooth module */
-		wifi@4 {
-			compatible = "usba69c,8d80";
-			reg = <4>;
-		};
-	};
-};
-
-&usb_2_hsphy {
-	vdda-pll-supply = <&vreg_l10c_0p88>;
-	vdda33-supply = <&vreg_l2b_3p072>;
-	vdda18-supply = <&vreg_l1c_1p8>;
-
-	status = "okay";
-};
-
-&venus {
-	status = "okay";
-};
-
-/* PINCTRL - additions to nodes defined in sc7280.dtsi */
-&dp_hot_plug_det {
-	bias-disable;
-};
-
-&pcie0_clkreq_n {
-	bias-pull-up;
-	drive-strength = <2>;
-};
-
-&pcie1_clkreq_n {
-	bias-pull-up;
-	drive-strength = <2>;
-};
-
-&sdc1_clk {
-	bias-disable;
-	drive-strength = <16>;
-};
-
-&sdc1_cmd {
-	bias-pull-up;
-	drive-strength = <10>;
-};
-
-&sdc1_data {
-	bias-pull-up;
-	drive-strength = <10>;
-};
-
-&sdc1_rclk {
-	bias-pull-down;
-};
-
-&sdc2_clk {
-	bias-disable;
-	drive-strength = <16>;
-};
-
-&sdc2_cmd {
-	bias-pull-up;
-	drive-strength = <10>;
-};
-
-&sdc2_data {
-	bias-pull-up;
-	drive-strength = <10>;
-};
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi
new file mode 100644
index 000000000000..52c2f053c820
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dtsi
@@ -0,0 +1,1137 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
+ */
+
+/* PM7250B is configured to use SID8/9 */
+#define PM7250B_SID 8
+#define PM7250B_SID1 9
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+#include <dt-bindings/iio/qcom,spmi-adc7-pm7325.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include "kodiak.dtsi"
+#include "pm7250b.dtsi"
+#include "pm7325.dtsi"
+#include "pm8350c.dtsi" /* PM7350C */
+#include "pmk8350.dtsi" /* PMK7325 */
+
+/delete-node/ &adsp_mem;
+/delete-node/ &adsp_rpc_remote_heap_mem;
+/delete-node/ &cdsp_mem;
+/delete-node/ &gpu_zap_mem;
+/delete-node/ &ipa_fw_mem;
+/delete-node/ &mpss_mem;
+/delete-node/ &remoteproc_mpss;
+/delete-node/ &remoteproc_wpss;
+/delete-node/ &rmtfs_mem;
+/delete-node/ &video_mem;
+/delete-node/ &wifi;
+/delete-node/ &wlan_ce_mem;
+/delete-node/ &wlan_fw_mem;
+/delete-node/ &wpss_mem;
+
+/ {
+	model = "Radxa Dragon Q6A";
+	compatible = "radxa,dragon-q6a", "qcom,qcm6490";
+	chassis-type = "embedded";
+
+	aliases {
+		mmc0 = &sdhc_1;
+		mmc1 = &sdhc_2;
+		serial0 = &uart5;
+	};
+
+	wcd938x: audio-codec {
+		compatible = "qcom,wcd9380-codec";
+
+		pinctrl-0 = <&wcd_default>;
+		pinctrl-names = "default";
+
+		reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
+
+		vdd-rxtx-supply = <&vreg_l18b_1p8>;
+		vdd-io-supply = <&vreg_l18b_1p8>;
+		vdd-buck-supply = <&vreg_l17b_1p8>;
+		vdd-mic-bias-supply = <&vreg_bob_3p296>;
+
+		qcom,micbias1-microvolt = <1800000>;
+		qcom,micbias2-microvolt = <1800000>;
+		qcom,micbias3-microvolt = <1800000>;
+		qcom,micbias4-microvolt = <1800000>;
+		qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
+		qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
+		qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
+		qcom,rx-device = <&wcd_rx>;
+		qcom,tx-device = <&wcd_tx>;
+
+		qcom,hphl-jack-type-normally-closed;
+
+		#sound-dai-cells = <1>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	usb2_1_con: connector-0 {
+		compatible = "usb-a-connector";
+		vbus-supply = <&vcc_5v_peri>;
+
+		port {
+			usb2_1_connector: endpoint {
+				remote-endpoint = <&usb_hub_2_1>;
+			};
+		};
+	};
+
+	usb2_2_con: connector-1 {
+		compatible = "usb-a-connector";
+		vbus-supply = <&vcc_5v_peri>;
+
+		port {
+			usb2_2_connector: endpoint {
+				remote-endpoint = <&usb_hub_2_2>;
+			};
+		};
+	};
+
+	usb2_3_con: connector-2 {
+		compatible = "usb-a-connector";
+		vbus-supply = <&vcc_5v_peri>;
+
+		port {
+			usb2_3_connector: endpoint {
+				remote-endpoint = <&usb_hub_2_3>;
+			};
+		};
+	};
+
+	usb3_con: connector {
+		compatible = "usb-a-connector";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				usb3_con_hs_in: endpoint {
+					remote-endpoint = <&usb_1_dwc3_hs>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				usb3_con_ss_in: endpoint {
+					remote-endpoint = <&usb_1_qmpphy_out_usb>;
+				};
+			};
+		};
+	};
+
+	hdmi-bridge {
+		compatible = "radxa,ra620";
+
+		pinctrl-0 = <&dp_hot_plug_det>;
+		pinctrl-names = "default";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				hdmi_bridge_in: endpoint {
+					remote-endpoint = <&usb_1_qmpphy_out_dp>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				hdmi_bridge_out: endpoint {
+					remote-endpoint = <&hdmi_connector_in>;
+				};
+			};
+		};
+	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		label = "hdmi";
+		type = "a";
+
+		port {
+			hdmi_connector_in: endpoint {
+				remote-endpoint = <&hdmi_bridge_out>;
+			};
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		pinctrl-0 = <&user_led>;
+		pinctrl-names = "default";
+
+		user-led {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_INDICATOR;
+			gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "none";
+			default-state = "off";
+			panic-indicator;
+		};
+	};
+
+	reserved-memory {
+		lpass_ml_mem: lpass-ml@81800000 {
+			reg = <0x0 0x81800000 0x0 0xf00000>;
+			no-map;
+		};
+
+		cdsp_secure_heap_mem: cdsp-secure-heap@82700000 {
+			reg = <0x0 0x82700000 0x0 0x10000>;
+			no-map;
+		};
+
+		adsp_mem: adsp@8b800000 {
+			reg = <0x0 0x8b800000 0x0 0x2800000>;
+			no-map;
+		};
+
+		cdsp_mem: cdsp@8e000000 {
+			reg = <0x0 0x8e000000 0x0 0x1e00000>;
+			no-map;
+		};
+
+		video_mem: video@8fe00000 {
+			reg = <0x0 0x8fe00000 0x0 0x500000>;
+			no-map;
+		};
+
+		gpu_zap_mem: zap@90300000 {
+			reg = <0x0 0x90300000 0x0 0x5000>;
+			no-map;
+		};
+
+		tz_stat_mem: tz-stat@c0000000 {
+			reg = <0x0 0xc0000000 0x0 0x100000>;
+			no-map;
+		};
+
+		tags_mem: tags@c0100000 {
+			reg = <0x0 0xc0100000 0x0 0x1200000>;
+			no-map;
+		};
+
+		qtee_mem: qtee@c1300000 {
+			reg = <0x0 0xc1300000 0x0 0x500000>;
+			no-map;
+		};
+
+		trusted_apps_mem: trusted-apps@c1800000 {
+			reg = <0x0 0xc1800000 0x0 0x2200000>;
+			no-map;
+		};
+
+		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@c6500000 {
+			reg = <0x0 0xc6500000 0x0 0x800000>;
+			no-map;
+		};
+	};
+
+	thermal-zones {
+		msm-skin-thermal {
+			polling-delay-passive = <0>;
+			thermal-sensors = <&pmk8350_adc_tm 2>;
+		};
+
+		quiet-thermal {
+			polling-delay-passive = <0>;
+			thermal-sensors = <&pmk8350_adc_tm 1>;
+		};
+
+		ufs-thermal {
+			polling-delay-passive = <0>;
+			thermal-sensors = <&pmk8350_adc_tm 3>;
+		};
+
+		xo-thermal {
+			polling-delay-passive = <0>;
+			thermal-sensors = <&pmk8350_adc_tm 0>;
+		};
+	};
+
+	vcc_1v8: regulator-vcc-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vcc_5v_peri>;
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc_3v3: regulator-vcc-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc_5v_peri>;
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vcc_5v_peri: regulator-vcc-5v-peri {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc_5v_peri";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vph_pwr>;
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	vph_pwr: regulator-vph-pwr {
+		compatible = "regulator-fixed";
+		regulator-name = "vph_pwr";
+		regulator-min-microvolt = <3700000>;
+		regulator-max-microvolt = <3700000>;
+
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm7325-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+		vdd-l1-l4-l12-l15-supply = <&vreg_s7b_0p536>;
+		vdd-l2-l7-supply = <&vreg_bob_3p296>;
+		vdd-l6-l9-l10-supply = <&vreg_s8b_1p2>;
+		vdd-l11-l17-l18-l19-supply = <&vreg_s1b_1p84>;
+
+		vreg_s1b_1p84: smps1 {
+			regulator-name = "vreg_s1b_1p84";
+			regulator-min-microvolt = <1840000>;
+			regulator-max-microvolt = <2040000>;
+		};
+
+		vreg_s7b_0p536: smps7 {
+			regulator-name = "vreg_s7b_0p536";
+			regulator-min-microvolt = <536000>;
+			regulator-max-microvolt = <1120000>;
+		};
+
+		vreg_s8b_1p2: smps8 {
+			regulator-name = "vreg_s8b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1496000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_RET>;
+		};
+
+		vreg_l1b_0p912: ldo1 {
+			regulator-name = "vreg_l1b_0p912";
+			regulator-min-microvolt = <832000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+							RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p072: ldo2 {
+			regulator-name = "vreg_l2b_3p072";
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+							RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p2: ldo6 {
+			regulator-name = "vreg_l6b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1256000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+							RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_2p96: ldo7 {
+			regulator-name = "vreg_l7b_2p96";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <2960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+							RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_1p2: ldo9 {
+			regulator-name = "vreg_l9b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1304000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_1p8: ldo17 {
+			regulator-name = "vreg_l17b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1896000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l18b_1p8: ldo18 {
+			regulator-name = "vreg_l18b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-always-on;
+		};
+
+		vreg_l19b_1p8: ldo19 {
+			regulator-name = "vreg_l19b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8350c-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+		vdd-s7-supply = <&vph_pwr>;
+		vdd-s8-supply = <&vph_pwr>;
+		vdd-s9-supply = <&vph_pwr>;
+		vdd-s10-supply = <&vph_pwr>;
+		vdd-l1-l12-supply = <&vreg_s1b_1p84>;
+		vdd-l6-l9-l11-supply = <&vreg_bob_3p296>;
+		vdd-l10-supply = <&vreg_s7b_0p536>;
+		vdd-bob-supply = <&vph_pwr>;
+
+		vreg_l1c_1p8: ldo1 {
+			regulator-name = "vreg_l1c_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1976000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6c_2p96: ldo6 {
+			regulator-name = "vreg_l6c_2p96";
+			regulator-min-microvolt = <1650000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9c_2p96: ldo9 {
+			regulator-name = "vreg_l9c_2p96";
+			regulator-min-microvolt = <2704000>;
+			regulator-max-microvolt = <3544000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10c_0p88: ldo10 {
+			regulator-name = "vreg_l10c_0p88";
+			regulator-min-microvolt = <720000>;
+			regulator-max-microvolt = <1048000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob_3p296: bob {
+			regulator-name = "vreg_bob_3p296";
+			regulator-min-microvolt = <3032000>;
+			regulator-max-microvolt = <3960000>;
+		};
+	};
+};
+
+&gcc {
+	protected-clocks = <GCC_CFG_NOC_LPASS_CLK>,
+			   <GCC_MSS_CFG_AHB_CLK>,
+			   <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+			   <GCC_MSS_OFFLINE_AXI_CLK>,
+			   <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+			   <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+			   <GCC_MSS_SNOC_AXI_CLK>,
+			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+			   <GCC_QSPI_CORE_CLK>,
+			   <GCC_QSPI_CORE_CLK_SRC>,
+			   <GCC_SEC_CTRL_CLK_SRC>,
+			   <GCC_WPSS_AHB_BDG_MST_CLK>,
+			   <GCC_WPSS_AHB_CLK>,
+			   <GCC_WPSS_RSCP_CLK>;
+};
+
+&gpi_dma0 {
+	status = "okay";
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&gpu_zap_shader {
+	firmware-name = "qcom/qcs6490/a660_zap.mbn";
+};
+
+/* Pin 13, 15 in GPIO header */
+&i2c0 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+/* Pin 27, 28 in GPIO header */
+&i2c2 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+/* Pin 3, 5 in GPIO header */
+&i2c6 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+&i2c10 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+
+	rtc: rtc@68 {
+		compatible = "st,m41t11";
+		reg = <0x68>;
+	};
+};
+
+/* External touchscreen */
+&i2c13 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp {
+	sound-name-prefix = "Display Port0";
+
+	status = "okay";
+};
+
+&mdss_dp_out {
+	data-lanes = <0 1>;
+	remote-endpoint = <&usb_dp_qmpphy_dp_in>;
+};
+
+&pcie0 {
+	perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie0_phy {
+	vdda-phy-supply = <&vreg_l10c_0p88>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+
+	status = "okay";
+};
+
+&pcie1 {
+	perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
+	wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
+
+	pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
+	pinctrl-names = "default";
+
+	/* Support for QPS615 PCIe switch */
+	iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+		    <0x100 &apps_smmu 0x1c81 0x1>,
+		    <0x208 &apps_smmu 0x1c84 0x1>,
+		    <0x210 &apps_smmu 0x1c85 0x1>,
+		    <0x218 &apps_smmu 0x1c86 0x1>,
+		    <0x300 &apps_smmu 0x1c87 0x1>,
+		    <0x400 &apps_smmu 0x1c88 0x1>,
+		    <0x500 &apps_smmu 0x1c89 0x1>,
+		    <0x501 &apps_smmu 0x1c90 0x1>;
+
+	status = "okay";
+};
+
+&pcie1_phy {
+	vdda-phy-supply = <&vreg_l10c_0p88>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+
+	status = "okay";
+};
+
+&pm7325_gpios {
+	pm7325_adc_default: adc-default-state {
+		pins = "gpio2";
+		function = PMIC_GPIO_FUNC_NORMAL;
+		bias-high-impedance;
+	};
+};
+
+&pm7325_temp_alarm {
+	io-channels = <&pmk8350_vadc PM7325_ADC7_DIE_TEMP>;
+	io-channel-names = "thermal";
+};
+
+&pmk8350_adc_tm {
+	status = "okay";
+
+	xo-therm@0 {
+		reg = <0>;
+		io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	quiet-therm@1 {
+		reg = <1>;
+		io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	msm-skin-therm@2 {
+		reg = <2>;
+		io-channels = <&pmk8350_vadc PM7325_ADC7_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+
+	ufs-therm@3 {
+		reg = <3>;
+		io-channels = <&pmk8350_vadc PM7325_ADC7_GPIO1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time-us = <200>;
+	};
+};
+
+&pmk8350_vadc {
+	pinctrl-0 = <&pm7325_adc_default>;
+	pinctrl-names = "default";
+
+	channel@3 {
+		reg = <PMK8350_ADC7_DIE_TEMP>;
+		label = "pmk7325_die_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	channel@44 {
+		reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+		label = "xo_therm";
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		qcom,ratiometric;
+	};
+
+	channel@103 {
+		reg = <PM7325_ADC7_DIE_TEMP>;
+		label = "pm7325_die_temp";
+		qcom,pre-scaling = <1 1>;
+	};
+
+	channel@144 {
+		reg = <PM7325_ADC7_AMUX_THM1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "quiet_therm";
+	};
+
+	channel@146 {
+		reg = <PM7325_ADC7_AMUX_THM3_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "msm_skin_therm";
+	};
+
+	channel@14a {
+		/* According to datasheet, 0x4a = AMUX1_GPIO = GPIO_02 */
+		reg = <PM7325_ADC7_GPIO1_100K_PU>;
+		qcom,ratiometric;
+		qcom,hw-settle-time = <200>;
+		qcom,pre-scaling = <1 1>;
+		label = "ufs_therm";
+	};
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&qupv3_id_0 {
+	firmware-name = "qcom/qcm6490/qupv3fw.elf";
+	status = "okay";
+};
+
+&qupv3_id_1 {
+	firmware-name = "qcom/qcm6490/qupv3fw.elf";
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/qcs6490/radxa/dragon-q6a/adsp.mbn";
+	status = "okay";
+};
+
+&remoteproc_cdsp {
+	firmware-name = "qcom/qcs6490/radxa/dragon-q6a/cdsp.mbn";
+	status = "okay";
+};
+
+&sdhc_1 {
+	non-removable;
+	no-sd;
+	no-sdio;
+
+	vmmc-supply = <&vreg_l7b_2p96>;
+	vqmmc-supply = <&vreg_l19b_1p8>;
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
+	pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
+
+	vmmc-supply = <&vreg_l9c_2p96>;
+	vqmmc-supply = <&vreg_l6c_2p96>;
+
+	cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+/* Pin 11, 29, 31, 32 in GPIO header */
+&spi7 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+/* Pin 19, 21, 23, 24, 26 in GPIO header */
+&spi12 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+/* Pin 22, 33, 36, 37 in GPIO header */
+&spi14 {
+	qcom,enable-gsi-dma;
+	status = "okay";
+};
+
+&swr0 {
+	status = "okay";
+
+	wcd_rx: codec@0,4 {
+		compatible = "sdw20217010d00";
+		reg = <0 4>;
+		qcom,rx-port-mapping = <1 2 3 4 5>;
+	};
+};
+
+&swr1 {
+	status = "okay";
+
+	wcd_tx: codec@0,3 {
+		compatible = "sdw20217010d00";
+		reg = <0 3>;
+		qcom,tx-port-mapping = <1 1 2 3>;
+	};
+};
+
+&tlmm {
+	/*
+	 * 12-17: reserved for QSPI flash
+	 */
+	gpio-reserved-ranges = <12 6>;
+	gpio-line-names =
+		/* GPIO_0 ~ GPIO_3 */
+		"PIN_13", "PIN_15", "", "",
+		/* GPIO_4 ~ GPIO_7 */
+		"", "", "", "",
+		/* GPIO_8 ~ GPIO_11 */
+		"PIN_27", "PIN_28", "", "",
+		/* GPIO_12 ~ GPIO_15 */
+		"", "", "", "",
+		/* GPIO_16 ~ GPIO_19 */
+		"", "", "", "",
+		/* GPIO_20 ~ GPIO_23 */
+		"", "", "PIN_8", "PIN_10",
+		/* GPIO_24 ~ GPIO_27 */
+		"PIN_3", "PIN_5", "PIN_16", "PIN_18",
+		/* GPIO_28 ~ GPIO_31 */
+		"PIN_31", "PIN_11", "PIN_32", "PIN_29",
+		/* GPIO_32 ~ GPIO_35 */
+		"", "", "", "",
+		/* GPIO_36 ~ GPIO_39 */
+		"", "", "", "",
+		/* GPIO_40 ~ GPIO_43 */
+		"", "", "", "",
+		/* GPIO_44 ~ GPIO_47 */
+		"", "", "", "",
+		/* GPIO_48 ~ GPIO_51 */
+		"PIN_21", "PIN_19", "PIN_23", "PIN_24",
+		/* GPIO_52 ~ GPIO_55 */
+		"", "", "", "PIN_26",
+		/* GPIO_56 ~ GPIO_59 */
+		"PIN_33", "PIN_22", "PIN_37", "PIN_36",
+		/* GPIO_60 ~ GPIO_63 */
+		"", "", "", "",
+		/* GPIO_64 ~ GPIO_67 */
+		"", "", "", "",
+		/* GPIO_68 ~ GPIO_71 */
+		"", "", "", "",
+		/* GPIO_72 ~ GPIO_75 */
+		"", "", "", "",
+		/* GPIO_76 ~ GPIO_79 */
+		"", "", "", "",
+		/* GPIO_80 ~ GPIO_83 */
+		"", "", "", "",
+		/* GPIO_84 ~ GPIO_87 */
+		"", "", "", "",
+		/* GPIO_88 ~ GPIO_91 */
+		"", "", "", "",
+		/* GPIO_92 ~ GPIO_95 */
+		"", "", "", "",
+		/* GPIO_96 ~ GPIO_99 */
+		"PIN_7", "PIN_12", "PIN_38", "PIN_40",
+		/* GPIO_100 ~ GPIO_103 */
+		"PIN_35", "", "", "",
+		/* GPIO_104 ~ GPIO_107 */
+		"", "", "", "",
+		/* GPIO_108 ~ GPIO_111 */
+		"", "", "", "",
+		/* GPIO_112 ~ GPIO_115 */
+		"", "", "", "",
+		/* GPIO_116 ~ GPIO_119 */
+		"", "", "", "",
+		/* GPIO_120 ~ GPIO_123 */
+		"", "", "", "",
+		/* GPIO_124 ~ GPIO_127 */
+		"", "", "", "",
+		/* GPIO_128 ~ GPIO_131 */
+		"", "", "", "",
+		/* GPIO_132 ~ GPIO_135 */
+		"", "", "", "",
+		/* GPIO_136 ~ GPIO_139 */
+		"", "", "", "",
+		/* GPIO_140 ~ GPIO_143 */
+		"", "", "", "",
+		/* GPIO_144 ~ GPIO_147 */
+		"", "", "", "",
+		/* GPIO_148 ~ GPIO_151 */
+		"", "", "", "",
+		/* GPIO_152 ~ GPIO_155 */
+		"", "", "", "",
+		/* GPIO_156 ~ GPIO_159 */
+		"", "", "", "",
+		/* GPIO_160 ~ GPIO_163 */
+		"", "", "", "",
+		/* GPIO_164 ~ GPIO_167 */
+		"", "", "", "",
+		/* GPIO_168 ~ GPIO_171 */
+		"", "", "", "",
+		/* GPIO_172 ~ GPIO_174 */
+		"", "", "";
+
+	pcie0_reset_n: pcie0-reset-n-state {
+		pins = "gpio87";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie0_wake_n: pcie0-wake-n-state {
+		pins = "gpio89";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	pcie1_reset_n: pcie1-reset-n-state {
+		pins = "gpio2";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	pcie1_wake_n: pcie1-wake-n-state {
+		pins = "gpio3";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	sd_cd: sd-cd-state {
+		pins = "gpio91";
+		function = "gpio";
+		bias-pull-up;
+	};
+
+	user_led: user-led-state {
+		pins = "gpio42";
+		function = "gpio";
+		bias-pull-up;
+	};
+
+	wcd_default: wcd-reset-n-active-state {
+		pins = "gpio83";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-low;
+	};
+};
+
+&uart5 {
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
+	vcc-supply = <&vreg_l7b_2p96>;
+	vcc-max-microamp = <800000>;
+	vccq-supply = <&vreg_l9b_1p2>;
+	vccq-max-microamp = <900000>;
+	vccq2-supply = <&vreg_l9b_1p2>;
+	vccq2-max-microamp = <1300000>;
+
+	/* Gear-4 Rate-B is unstable due to board */
+	/* and UFS module design limitations */
+	limit-gear-rate = "rate-a";
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l10c_0p88>;
+	vdda-pll-supply = <&vreg_l6b_1p2>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	dr_mode = "host";
+
+	status = "okay";
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&usb3_con_hs_in>;
+};
+
+&usb_1_hsphy {
+	vdda-pll-supply = <&vreg_l10c_0p88>;
+	vdda33-supply = <&vreg_l2b_3p072>;
+	vdda18-supply = <&vreg_l1c_1p8>;
+
+	status = "okay";
+};
+
+&usb_1_qmpphy {
+	vdda-phy-supply = <&vreg_l6b_1p2>;
+	vdda-pll-supply = <&vreg_l1b_0p912>;
+
+	/delete-property/ orientation-switch;
+
+	status = "okay";
+
+	ports {
+		port@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			/delete-node/ endpoint;
+
+			/* RX0/TX0 is statically connected to RA620 bridge */
+			usb_1_qmpphy_out_dp: endpoint@0 {
+				reg = <0>;
+
+				data-lanes = <0 1>;
+				remote-endpoint = <&hdmi_bridge_in>;
+			};
+
+			/* RX1/TX1 is statically connected to USB-A port */
+			usb_1_qmpphy_out_usb: endpoint@1 {
+				reg = <1>;
+
+				data-lanes = <2 3>;
+				remote-endpoint = <&usb3_con_ss_in>;
+			};
+		};
+	};
+};
+
+&usb_2 {
+	dr_mode = "host";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	status = "okay";
+
+	/* Onboard USB 2.0 hub */
+	usb_hub_2_x: hub@1 {
+		compatible = "usb1a40,0101";
+		reg = <1>;
+		vdd-supply = <&vcc_5v_peri>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@1 {
+				reg = <1>;
+
+				usb_hub_2_1: endpoint {
+					remote-endpoint = <&usb2_1_connector>;
+				};
+			};
+
+			port@2 {
+				reg = <2>;
+
+				usb_hub_2_2: endpoint {
+					remote-endpoint = <&usb2_2_connector>;
+				};
+			};
+
+			port@3 {
+				reg = <3>;
+
+				usb_hub_2_3: endpoint {
+					remote-endpoint = <&usb2_3_connector>;
+				};
+			};
+		};
+
+		/* FCU760K Wi-Fi & Bluetooth module */
+		wifi@4 {
+			compatible = "usba69c,8d80";
+			reg = <4>;
+		};
+	};
+};
+
+&usb_2_hsphy {
+	vdda-pll-supply = <&vreg_l10c_0p88>;
+	vdda33-supply = <&vreg_l2b_3p072>;
+	vdda18-supply = <&vreg_l1c_1p8>;
+
+	status = "okay";
+};
+
+&venus {
+	status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+&dp_hot_plug_det {
+	bias-disable;
+};
+
+&pcie0_clkreq_n {
+	bias-pull-up;
+	drive-strength = <2>;
+};
+
+&pcie1_clkreq_n {
+	bias-pull-up;
+	drive-strength = <2>;
+};
+
+&sdc1_clk {
+	bias-disable;
+	drive-strength = <16>;
+};
+
+&sdc1_cmd {
+	bias-pull-up;
+	drive-strength = <10>;
+};
+
+&sdc1_data {
+	bias-pull-up;
+	drive-strength = <10>;
+};
+
+&sdc1_rclk {
+	bias-pull-down;
+};
+
+&sdc2_clk {
+	bias-disable;
+	drive-strength = <16>;
+};
+
+&sdc2_cmd {
+	bias-pull-up;
+	drive-strength = <10>;
+};
+
+&sdc2_data {
+	bias-pull-up;
+	drive-strength = <10>;
+};

-- 
2.53.0

[PATCH 11/12] ASoC: dt-bindings: google,sc7280-herobrine: Add Radxa Dragon Q6A sound card

[Xilin Wu]

The Radxa Dragon Q6A can boot in EL2, allowing the kernel to access the
LPASS hardware directly. Add the compatible for it to the bindings.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 .../devicetree/bindings/sound/google,sc7280-herobrine.yaml       | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
index cdcd7c6f21eb..cd87dfe20618 100644
--- a/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
+++ b/Documentation/devicetree/bindings/sound/google,sc7280-herobrine.yaml
@@ -17,8 +17,13 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - google,sc7280-herobrine
+    oneOf:
+      - enum:
+          - google,sc7280-herobrine
+      - items:
+          - enum:
+              - radxa,dragon-q6a-sndcard
+          - const: google,sc7280-herobrine
 
   "#address-cells":
     const: 1

-- 
2.53.0

Re: [PATCH 11/12] ASoC: dt-bindings: google,sc7280-herobrine: Add Radxa Dragon Q6A sound card

[Krzysztof Kozlowski]

On Tue, Apr 07, 2026 at 11:20:03PM +0800, Xilin Wu wrote:
> The Radxa Dragon Q6A can boot in EL2, allowing the kernel to access the
> LPASS hardware directly. Add the compatible for it to the bindings.

You are not adding compatible for LPASS, but for the sound card. And
since you mentioned it, what happens when you boot in EL1?

You need to post bindings for both cases.

Best regards,
Krzysztof

Re: [PATCH 11/12] ASoC: dt-bindings: google,sc7280-herobrine: Add Radxa Dragon Q6A sound card

[Xilin Wu]

On 4/8/2026 4:48 PM, Krzysztof Kozlowski wrote:
> On Tue, Apr 07, 2026 at 11:20:03PM +0800, Xilin Wu wrote:
>> The Radxa Dragon Q6A can boot in EL2, allowing the kernel to access the
>> LPASS hardware directly. Add the compatible for it to the bindings.
> 
> You are not adding compatible for LPASS, but for the sound card. And
> since you mentioned it, what happens when you boot in EL1?
> 
> You need to post bindings for both cases.
> 
> Best regards,
> Krzysztof
> 
> 

Hi Krzysztof,

Thank you for the review. You are right that this patch adds a 
board-specific compatible for the sound card, not for the LPASS block 
itself.

For EL1, the default Dragon Q6A DTS already uses the generic
"qcom,qcs6490-rb3gen2-sndcard" compatible, and for the EL2 LPASS-CPU
variant I can also just keep using the generic
"google,sc7280-herobrine" compatible.

Would it be better if I simply drop this binding patch and keep both
cases on their existing generic compatibles instead of introducing
"radxa,dragon-q6a-sndcard"?

-- 
Best regards,
Xilin Wu <sophon@radxa.com>

[PATCH 12/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: add LPASS CPU audio variant

[Xilin Wu]

Add a qcs6490-radxa-dragon-q6a-lpass-cpu.dts variant for debugging and
bring-up of the host-controlled LPASS audio path on the Radxa Dragon
Q6A.

This variant enables the LPASS blocks and codec macros needed by the
lpass-cpu driver, wires WCD9380 playback/capture and DisplayPort audio
to the LPASS CDC DMA and DP interfaces, and disables remoteproc_adsp so
that the audio hardware is owned directly by Linux.

This DTB is an optional configuration for systems booted with the kernel
running at EL2, where direct CPU access to the LPASS hardware is
available. It is useful for users who need low-latency and fully
controllable audio.

Signed-off-by: Xilin Wu <sophon@radxa.com>
---
 arch/arm64/boot/dts/qcom/Makefile                  |   1 +
 .../qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts    | 131 +++++++++++++++++++++
 2 files changed, 132 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 4ba8e7306419..2f84ef7109b5 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -169,6 +169,7 @@ qcs615-ride-el2-dtbs := qcs615-ride.dtb talos-el2.dtbo
 
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs615-ride-el2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-radxa-dragon-q6a.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-radxa-dragon-q6a-lpass-cpu.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs6490-rb3gen2.dtb
 
 qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo
diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts
new file mode 100644
index 000000000000..e7ee57372d7e
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a-lpass-cpu.dts
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025-2026 Radxa Computer (Shenzhen) Co., Ltd.
+ *
+ * Direct CPU access to the LPASS hardware block on this platform is
+ * restricted by default. Booting the Linux kernel in EL2 will allow the
+ * kernel to access the LPASS hardware directly.
+ *
+ * You can achieve this by setting the Hypervisor Override BIOS setting to
+ * "Enabled" if you are using the official UEFI firmware.
+ */
+
+/dts-v1/;
+
+#include "qcs6490-radxa-dragon-q6a.dtsi"
+
+&gcc {
+	protected-clocks = <GCC_MSS_CFG_AHB_CLK>,
+			   <GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC>,
+			   <GCC_MSS_OFFLINE_AXI_CLK>,
+			   <GCC_MSS_Q6SS_BOOT_CLK_SRC>,
+			   <GCC_MSS_Q6_MEMNOC_AXI_CLK>,
+			   <GCC_MSS_SNOC_AXI_CLK>,
+			   <GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+			   <GCC_QSPI_CORE_CLK>,
+			   <GCC_QSPI_CORE_CLK_SRC>,
+			   <GCC_SEC_CTRL_CLK_SRC>,
+			   <GCC_WPSS_AHB_BDG_MST_CLK>,
+			   <GCC_WPSS_AHB_CLK>,
+			   <GCC_WPSS_RSCP_CLK>;
+};
+
+&lpass_aon {
+	status = "okay";
+};
+
+&lpass_core {
+	status = "okay";
+};
+
+&lpass_cpu {
+	status = "okay";
+
+	dai-link@5 {
+		reg = <LPASS_DP_RX>;
+	};
+
+	dai-link@6 {
+		reg = <LPASS_CDC_DMA_RX0>;
+	};
+
+	dai-link@19 {
+		reg = <LPASS_CDC_DMA_TX3>;
+	};
+};
+
+&lpass_hm {
+	status = "okay";
+};
+
+&lpass_rx_macro {
+	status = "okay";
+};
+
+&lpass_tx_macro {
+	status = "okay";
+};
+
+&lpass_va_macro {
+	status = "okay";
+};
+
+&lpasscc {
+	status = "okay";
+};
+
+&remoteproc_adsp {
+	status = "disabled";
+};
+
+&sound {
+	compatible = "radxa,dragon-q6a-sndcard", "google,sc7280-herobrine";
+	model = "qcs6490-wcd938x-dp";
+
+	audio-routing = "IN1_HPHL", "HPHL_OUT",
+			"IN2_HPHR", "HPHR_OUT",
+			"AMIC2", "MIC BIAS2",
+			"TX SWR_ADC1", "ADC2_OUTPUT";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	dai-link@0 {
+		link-name = "WCD9380 Playback";
+		reg = <0>;
+
+		cpu {
+			sound-dai = <&lpass_cpu LPASS_CDC_DMA_RX0>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 0>, <&swr0 0>, <&lpass_rx_macro 0>;
+		};
+	};
+
+	dai-link@1 {
+		link-name = "DisplayPort";
+		reg = <1>;
+
+		cpu {
+			sound-dai = <&lpass_cpu LPASS_DP_RX>;
+		};
+
+		codec {
+			sound-dai = <&mdss_dp>;
+		};
+	};
+
+	dai-link@2 {
+		link-name = "WCD9380 Capture";
+		reg = <2>;
+
+		cpu {
+			sound-dai = <&lpass_cpu LPASS_CDC_DMA_TX3>;
+		};
+
+		codec {
+			sound-dai = <&wcd938x 1>, <&swr1 0>, <&lpass_tx_macro 0>;
+		};
+	};
+};

-- 
2.53.0

Re: [PATCH 12/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: add LPASS CPU audio variant

[Konrad Dybcio]

On 4/7/26 5:20 PM, Xilin Wu wrote:
> Add a qcs6490-radxa-dragon-q6a-lpass-cpu.dts variant for debugging and
> bring-up of the host-controlled LPASS audio path on the Radxa Dragon
> Q6A.
> 
> This variant enables the LPASS blocks and codec macros needed by the
> lpass-cpu driver, wires WCD9380 playback/capture and DisplayPort audio
> to the LPASS CDC DMA and DP interfaces, and disables remoteproc_adsp so
> that the audio hardware is owned directly by Linux.
> 
> This DTB is an optional configuration for systems booted with the kernel
> running at EL2, where direct CPU access to the LPASS hardware is
> available. It is useful for users who need low-latency and fully
> controllable audio.

I believe on Chrome platforms it was done this way because at some point
it was determined that they would specifically like not to use the DSP.

I think this is more of a hack than anything else.. but at the end of the
commit message you mention low latency - is the impact actually measurable?

Konrad

Re: [PATCH 12/12] arm64: dts: qcom: qcs6490-radxa-dragon-q6a: add LPASS CPU audio variant

[Xilin Wu]

On 4/8/2026 5:06 PM, Konrad Dybcio wrote:
> On 4/7/26 5:20 PM, Xilin Wu wrote:
>> Add a qcs6490-radxa-dragon-q6a-lpass-cpu.dts variant for debugging and
>> bring-up of the host-controlled LPASS audio path on the Radxa Dragon
>> Q6A.
>>
>> This variant enables the LPASS blocks and codec macros needed by the
>> lpass-cpu driver, wires WCD9380 playback/capture and DisplayPort audio
>> to the LPASS CDC DMA and DP interfaces, and disables remoteproc_adsp so
>> that the audio hardware is owned directly by Linux.
>>
>> This DTB is an optional configuration for systems booted with the kernel
>> running at EL2, where direct CPU access to the LPASS hardware is
>> available. It is useful for users who need low-latency and fully
>> controllable audio.
> 
> I believe on Chrome platforms it was done this way because at some point
> it was determined that they would specifically like not to use the DSP.
> 
> I think this is more of a hack than anything else.. but at the end of the
> commit message you mention low latency - is the impact actually measurable?
> 

Some of our users also specifically prefer not to use the DSP [1] :)

Based on their testing, the AudioReach/ADSP path imposes a minimum 
scheduling interval of 10 ms, which is much higher than the 0.67 ms they 
can get on a Raspberry Pi 5 with direct I2S/DMA.

Since the lpass-cpu setup works properly, I would not consider this a hack.

[1] 
https://forum.radxa.com/t/dragon-q6a-lpaif-mi2s-registers-locked-by-qualcomm-trustzone-no-direct-low-latency-audio-access-possible/30592

> Konrad
> 


-- 
Best regards,
Xilin Wu <sophon@radxa.com>