From: sashiko-bot@kernel.org
To: "Vishnu Reddy" <busanna.reddy@oss.qualcomm.com>
Cc: devicetree@vger.kernel.org, robh@kernel.org, conor+dt@kernel.org,
krzk+dt@kernel.org
Subject: Re: [PATCH v5 07/14] media: iris: Enable Secure PAS support with IOMMU managed by Linux
Date: Sat, 09 May 2026 02:05:55 +0000 [thread overview]
Message-ID: <20260509020555.D9238C2BCB0@smtp.kernel.org> (raw)
In-Reply-To: <20260509-glymur-v5-7-7fbb340c5dbd@oss.qualcomm.com>
Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [High] Missing `qcom_scm_pas_metadata_release()` causes PAS metadata buffer memory leak.
- [High] Unbounded memory leak due to dynamic `devm_qcom_scm_pas_context_alloc()` inside `iris_load_fw_to_memory()`.
- [High] Skipped `iris_fw_iommu_unmap()` if `qcom_scm_pas_shutdown()` fails causes permanent device failure.
- [High] Directly calling `iommu_map()` on a default DMA domain bypasses the DMA API.
- [Medium] Original error codes from `iris_load_fw_to_memory()` are unconditionally masked with `-ENOMEM`.
--
commit f84ed6beb9478a59d8db52c92115b570f4c199ba
Author: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
media: iris: Enable Secure PAS support with IOMMU managed by Linux
This commit extends the Iris driver to handle IOMMU and SHM bridge
configurations for firmware load and resources mapping in the absence
of a proprietary hypervisor.
[ ... ]
> --- a/drivers/media/platform/qcom/iris/iris_firmware.c
> +++ b/drivers/media/platform/qcom/iris/iris_firmware.c
[ ... ]
> @@ -29,14 +33,18 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
> if (strlen(fw_name) >= MAX_FIRMWARE_NAME_SIZE - 4)
> return -EINVAL;
>
> - ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res);
> + ret = of_reserved_mem_region_to_resource(core->dev->of_node, 0, &res);
> if (ret)
> return ret;
>
> mem_phys = res.start;
> res_size = resource_size(&res);
>
> - ret = request_firmware(&firmware, fw_name, dev);
> + pas_ctx = devm_qcom_scm_pas_context_alloc(fw_dev, pas_id, mem_phys, res_size);
> + if (IS_ERR(pas_ctx))
> + return PTR_ERR(pas_ctx);
devm_qcom_scm_pas_context_alloc() ties the memory to the fw_dev unbind event.
If iris_load_fw_to_memory() is called dynamically (e.g., when userspace opens
the device) and fails later in the function, this devres allocation isn't
freed. Could repeated failures here lead to an unbounded memory leak?
> +
> + ret = request_firmware(&firmware, fw_name, fw_dev);
> if (ret)
> return ret;
>
[ ... ]
> @@ -52,9 +60,27 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_name)
> goto err_release_fw;
> }
>
> - ret = qcom_mdt_load(dev, firmware, fw_name,
> - pas_id, mem_virt, mem_phys, res_size, NULL);
> + pas_ctx->use_tzmem = !!core->fw_dev;
> + ret = qcom_mdt_pas_load(pas_ctx, firmware, fw_name, mem_virt, NULL);
> + if (ret)
> + goto err_mem_unmap;
> +
> + if (pas_ctx->use_tzmem) {
> + domain = iommu_get_domain_for_dev(fw_dev);
> + if (!domain) {
> + ret = -ENODEV;
> + goto err_mem_unmap;
> + }
> +
> + ret = iommu_map(domain, IRIS_FW_START_ADDR, mem_phys, res_size,
> + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL);
iommu_get_domain_for_dev() will return the default DMA domain attached to
fw_dev. Is it safe to call iommu_map() directly on a DMA domain?
This bypasses the DMA API's IOVA allocator and might trigger a kernel warning.
Should the driver allocate and attach an unmanaged domain instead?
> + if (ret)
> + goto err_mem_unmap;
> + }
>
> + core->pas_ctx = pas_ctx;
> +
> +err_mem_unmap:
> memunmap(mem_virt);
> err_release_fw:
> release_firmware(firmware);
[ ... ]
> @@ -79,10 +117,10 @@ int iris_fw_load(struct iris_core *core)
> return -ENOMEM;
> }
Now that iris_load_fw_to_memory() has been updated to return specific error
codes like -EINVAL, -ENODEV, or PTR_ERR(), is there a reason to continue
masking all of them with -ENOMEM here?
>
> - ret = qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id);
> + ret = qcom_scm_pas_prepare_and_auth_reset(core->pas_ctx);
qcom_mdt_pas_load() allocates a secure DMA buffer for firmware metadata via
qcom_scm_pas_init_image(). Does this driver need to call
qcom_scm_pas_metadata_release() after authentication here to avoid leaking the
metadata buffer?
> if (ret) {
> dev_err(core->dev, "auth and reset failed: %d\n", ret);
> - return ret;
> + goto err_unmap;
> }
>
[ ... ]
> @@ -93,17 +131,31 @@ int iris_fw_load(struct iris_core *core)
[ ... ]
> int iris_fw_unload(struct iris_core *core)
> {
> - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
> + int ret;
> +
> + ret = qcom_scm_pas_shutdown(core->pas_ctx->pas_id);
> + if (ret)
> + return ret;
> +
> + iris_fw_iommu_unmap(core);
> +
> + return ret;
If qcom_scm_pas_shutdown() fails and returns early, iris_fw_iommu_unmap() is
skipped. Will this leave the IOMMU mapping active at IRIS_FW_START_ADDR,
causing the next iommu_map() attempt during initialization to fail with
-EEXIST?
> }
>
> int iris_set_hw_state(struct iris_core *core, bool resume)
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260509-glymur-v5-0-7fbb340c5dbd@oss.qualcomm.com?part=7
next prev parent reply other threads:[~2026-05-09 2:05 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-08 18:59 [PATCH v5 00/14] media: iris: Add support for glymur platform Vishnu Reddy
2026-05-08 18:59 ` [PATCH v5 01/14] media: iris: Add iris vpu bus support Vishnu Reddy
2026-05-08 19:16 ` Dmitry Baryshkov
2026-05-09 17:05 ` Vishnu Reddy
2026-05-08 23:20 ` sashiko-bot
2026-05-08 18:59 ` [PATCH v5 02/14] iommu: Add iris-vpu-bus to iommu_buses Vishnu Reddy
2026-05-08 19:16 ` Dmitry Baryshkov
2026-05-08 23:42 ` sashiko-bot
2026-05-08 18:59 ` [PATCH v5 03/14] media: iris: Fix VM count passed to firmware Vishnu Reddy
2026-05-08 19:20 ` Dmitry Baryshkov
2026-05-08 18:59 ` [PATCH v5 04/14] dt-bindings: media: qcom,venus: Remove clock, power-domain, and iommus from common schema Vishnu Reddy
2026-05-08 19:22 ` Dmitry Baryshkov
2026-05-09 17:04 ` Vishnu Reddy
2026-05-08 18:59 ` [PATCH v5 05/14] dt-bindings: media: qcom,glymur-iris: Add glymur video codec Vishnu Reddy
2026-05-08 18:59 ` [PATCH v5 06/14] media: iris: Add context bank hooks for platform specific initialization Vishnu Reddy
2026-05-09 0:41 ` sashiko-bot
2026-05-08 18:59 ` [PATCH v5 07/14] media: iris: Enable Secure PAS support with IOMMU managed by Linux Vishnu Reddy
2026-05-08 19:05 ` Trilok Soni
2026-05-08 20:20 ` Dmitry Baryshkov
2026-05-09 2:05 ` sashiko-bot [this message]
2026-05-08 18:59 ` [PATCH v5 08/14] media: iris: Rename clock and power domain macros to use vcodec prefix Vishnu Reddy
2026-05-08 20:22 ` Dmitry Baryshkov
2026-05-09 17:07 ` Vishnu Reddy
2026-05-09 2:18 ` sashiko-bot
2026-05-08 18:59 ` [PATCH v5 09/14] media: iris: Use power domain type to look up pd_devs index Vishnu Reddy
2026-05-08 20:44 ` Dmitry Baryshkov
2026-05-09 17:02 ` Vishnu Reddy
2026-05-08 18:59 ` [PATCH v5 10/14] media: iris: Add power sequence for Glymur Vishnu Reddy
2026-05-08 20:54 ` Dmitry Baryshkov
2026-05-09 2:56 ` sashiko-bot
2026-05-08 19:00 ` [PATCH v5 11/14] media: iris: Add support to select core for dual core platforms Vishnu Reddy
2026-05-08 21:00 ` Dmitry Baryshkov
2026-05-09 3:55 ` sashiko-bot
2026-05-08 19:00 ` [PATCH v5 12/14] media: iris: Add platform data for glymur Vishnu Reddy
2026-05-08 21:05 ` Dmitry Baryshkov
2026-05-09 4:23 ` sashiko-bot
2026-05-08 19:00 ` [PATCH v5 13/14] arm64: dts: qcom: glymur: Add iris video node Vishnu Reddy
2026-05-08 19:27 ` Dmitry Baryshkov
2026-05-09 16:56 ` Vishnu Reddy
2026-05-08 19:00 ` [PATCH v5 14/14] arm64: dts: qcom: glymur-crd: Enable iris video codec node Vishnu Reddy
2026-05-08 23:54 ` Dmitry Baryshkov
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