[PATCH v2] arm64: dts: imx95: Increase PCIe outbound address space to 2GB

[PATCH v2] arm64: dts: imx95: Increase PCIe outbound address space to 2GB

[Richard Zhu]

Expand the PCIe outbound memory region from the current size to 2GB
to support devices requiring larger address spaces.

Fixes: 3b1d5deb29ff ("arm64: dts: imx95: add pcie[0,1] and pcie-ep[0,1] support")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
---
Changes in v2:
Add the Fixes tag, and rebase to latest imx/dt64 branch.

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index adcc0e1d3696b..201c0eae13948 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1940,7 +1940,7 @@ pcie0: pcie@4c300000 {
 			      <0 0x4c340000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
-				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
+				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -2015,7 +2015,7 @@ pcie1: pcie@4c380000 {
 			      <0 0x4c3c0000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
-				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
+				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";

base-commit: 5f9e9f83aee0fa8f2124c6f192505de2cdf7c5dc
-- 
2.37.1

Re: [PATCH v2] arm64: dts: imx95: Increase PCIe outbound address space to 2GB

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The expanded 2GB PCIe outbound memory window cannot allocate a 2GB BAR and restricts 1GB BAR allocations due to PCI address alignment constraints.
--

commit 6da3bf3dfff2671c469eeafa736ee204651d7b67
Author: Richard Zhu <hongxing.zhu@nxp.com>
arm64: dts: imx95: Increase PCIe outbound address space to 2GB

This commit expands the PCIe outbound memory region to 2GB to support
devices requiring larger address spaces.

> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1846,7 +1846,7 @@ pcie0: pcie@4c300000 {
>  			      <0 0x4c340000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> -				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> +				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x80000000>;

With this update, the PCI address window starts at 0x10000000 and has a
size of 0x80000000.

Because PCI specifications require a Base Address Register to be naturally
aligned to its size, a 2GB allocation would have to start at 0x80000000.

Since a 2GB allocation starting at 0x80000000 ends at 0xffffffff, does
this exceed the top of the defined window at 0x8fffffff?

It seems like this would prevent allocating a full 2GB address space.

[ ... ]

> @@ -1921,7 +1921,7 @@ pcie1: pcie@4c380000 {
>  			      <0 0x4c3c0000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
> -				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
> +				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x80000000>;

This appears to have the same alignment restriction that would prevent a
2GB allocation.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260509020440.3219767-1-hongxing.zhu@nxp.com?part=1