From: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
To: linux-mmc@vger.kernel.org
Cc: ulf.hansson@linaro.org,
Tanmay Kathpalia <tanmay.kathpalia@altera.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v1 2/9] dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties
Date: Mon, 11 May 2026 13:21:24 -0700 [thread overview]
Message-ID: <20260511202132.5597-3-tanmay.kathpalia@altera.com> (raw)
In-Reply-To: <20260511202132.5597-1-tanmay.kathpalia@altera.com>
Extend the Cadence SDHCI binding to support the sixth-generation
SD6HC controller. Add the cdns,sd6hc and altr,agilex5-sd6hc
compatible strings, clock-names, reset-names, iommus and three
SD6HC-specific PHY timing properties.
Add per-variant conditional blocks so SD6HC and SD4HC each enforce
their own clock, reset, and PHY property constraints independently.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com>
---
.../devicetree/bindings/mmc/cdns,sdhci.yaml | 107 ++++++++++++++++--
1 file changed, 97 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
index 6c7317d13aa6..e483ff83cbc2 100644
--- a/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
+++ b/Documentation/devicetree/bindings/mmc/cdns,sdhci.yaml
@@ -4,21 +4,29 @@
$id: http://devicetree.org/schemas/mmc/cdns,sdhci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Cadence SD/SDIO/eMMC Host Controller (SD4HC)
+title: Cadence SD/SDIO/eMMC Host Controller (SD4HC and SD6HC)
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
+ - Tanmay Kathpalia <tanmay.kathpalia@altera.com>
properties:
compatible:
- items:
- - enum:
- - amd,pensando-elba-sd4hc
- - microchip,mpfs-sd4hc
- - microchip,pic64gx-sd4hc
- - mobileye,eyeq-sd4hc
- - socionext,uniphier-sd4hc
- - const: cdns,sd4hc
+ oneOf:
+ - description: Cadence SD4HC controller
+ items:
+ - enum:
+ - amd,pensando-elba-sd4hc
+ - microchip,mpfs-sd4hc
+ - microchip,pic64gx-sd4hc
+ - mobileye,eyeq-sd4hc
+ - socionext,uniphier-sd4hc
+ - const: cdns,sd4hc
+ - description: Cadence SD6HC controller
+ items:
+ - enum:
+ - altr,agilex5-sd6hc
+ - const: cdns,sd6hc
reg:
minItems: 1
@@ -28,9 +36,14 @@ properties:
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
resets:
+ minItems: 1
+ maxItems: 3
+
+ iommus:
maxItems: 1
# PHY DLL input delays:
@@ -115,6 +128,25 @@ properties:
minimum: 0
maximum: 0x7f
+ # SD6HC PHY timing properties:
+ cdns,iocell-input-delay:
+ description: Input delay across IO cells in picoseconds
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 20000 # 20 ns
+
+ cdns,iocell-output-delay:
+ description: Output delay across IO cells in picoseconds
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0
+ maximum: 20000 # 20 ns
+
+ cdns,delay-element:
+ description: Delay element size in picoseconds
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 1000 # 1 ns
+
required:
- compatible
- reg
@@ -139,6 +171,61 @@ allOf:
reg:
maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: cdns,sd6hc
+ then:
+ description: SD6HC variant - use IO-cell and delay element properties
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: ciu
+ - const: biu
+ resets:
+ minItems: 3
+ maxItems: 3
+ reset-names:
+ items:
+ - const: sdhc-reset
+ - const: combophy
+ - const: sdmmc-ocp
+ cdns,phy-input-delay-sd-highspeed: false
+ cdns,phy-input-delay-legacy: false
+ cdns,phy-input-delay-sd-uhs-sdr12: false
+ cdns,phy-input-delay-sd-uhs-sdr25: false
+ cdns,phy-input-delay-sd-uhs-sdr50: false
+ cdns,phy-input-delay-sd-uhs-ddr50: false
+ cdns,phy-input-delay-mmc-highspeed: false
+ cdns,phy-input-delay-mmc-ddr: false
+ cdns,phy-dll-delay-sdclk: false
+ cdns,phy-dll-delay-sdclk-hsmmc: false
+ cdns,phy-dll-delay-strobe: false
+ required:
+ - resets
+ - clock-names
+ - reset-names
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: cdns,sd4hc
+ then:
+ description: SD4HC variant - use legacy DLL delay properties
+ properties:
+ clocks:
+ maxItems: 1
+ resets:
+ maxItems: 1
+ cdns,iocell-input-delay: false
+ cdns,iocell-output-delay: false
+ cdns,delay-element: false
+
unevaluatedProperties: false
examples:
--
2.43.7
next prev parent reply other threads:[~2026-05-11 20:21 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260511202132.5597-1-tanmay.kathpalia@altera.com>
2026-05-11 20:21 ` [PATCH v1 1/9] dt-bindings: reset: altr: add COMBOPHY_RESET for Agilex5 Tanmay Kathpalia
2026-05-12 17:33 ` Conor Dooley
2026-05-11 20:21 ` Tanmay Kathpalia [this message]
2026-05-12 17:33 ` [PATCH v1 2/9] dt-bindings: mmc: cdns,sdhci: add SD6HC support and PHY properties Conor Dooley
2026-05-13 0:23 ` sashiko-bot
2026-05-11 20:21 ` [PATCH v1 3/9] arm64: dts: agilex5: add Cadence SD6HC controller and SOCDK enablement Tanmay Kathpalia
2026-05-13 0:43 ` sashiko-bot
2026-05-13 6:34 ` Kathpalia, Tanmay
2026-05-11 20:21 ` [PATCH v1 4/9] dt-bindings: arm: intel: add Agilex5 SOCDK eMMC board variant Tanmay Kathpalia
2026-05-11 20:21 ` [PATCH v1 5/9] arm64: dts: agilex5: add SOCDK eMMC daughter board support Tanmay Kathpalia
2026-05-13 1:22 ` sashiko-bot
2026-05-13 6:25 ` Kathpalia, Tanmay
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