[PATCH v3] arm64: dts: imx95: Increase PCIe outbound address space to 4GB

[PATCH v3] arm64: dts: imx95: Increase PCIe outbound address space to 4GB

[Richard Zhu]

Fix the PCIe outbound memory region size to 4GB, which is the actual
hardware-supported memory space. The size was incorrectly set to 256MB
during bring-up.

Fixes: 3b1d5deb29ff ("arm64: dts: imx95: add pcie[0,1] and pcie-ep[0,1] support")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
---
Changes in v3:
Update the commit message, and set the region size to the max
hardware-supported memory space.

Changes in v2:
Add the Fixes tag, and rebase to latest imx/dt64 branch.

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index adcc0e1d3696b..7af25e880aa34 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1940,7 +1940,7 @@ pcie0: pcie@4c300000 {
 			      <0 0x4c340000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
-				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
+				 <0x82000000 0x0 0x10000000 0x9 0x00000000 1 0x00000000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
@@ -2015,7 +2015,7 @@ pcie1: pcie@4c380000 {
 			      <0 0x4c3c0000 0 0x4000>;
 			reg-names = "dbi", "config", "atu", "app";
 			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
-				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
+				 <0x82000000 0 0x10000000 0xa 0x00000000 1 0x00000000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";

base-commit: 5f9e9f83aee0fa8f2124c6f192505de2cdf7c5dc
-- 
2.37.1

Re: [PATCH v3] arm64: dts: imx95: Increase PCIe outbound address space to 4GB

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The updated 4GB PCIe outbound memory regions overflow the 32-bit PCI address space limit and unintentionally alter the CPU-to-PCI translation offset.
--

commit 4cfadeebb855cc5a85fa1d6b78564d2c9f105cec
Author: Richard Zhu <hongxing.zhu@nxp.com>

arm64: dts: imx95: Increase PCIe outbound address space to 4GB

This commit increases the PCIe outbound memory region size to 4GB, which
is the hardware-supported memory space, fixing an issue where it was
incorrectly set to 256MB during bring-up.

> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index adcc0e1d3696b..7af25e880aa34 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1940,7 +1940,7 @@ pcie0: pcie@4c300000 {
>  			      <0 0x4c340000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>,
> -				 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>;
> +				 <0x82000000 0x0 0x10000000 0x9 0x00000000 1 0x00000000>;

Does this overflow the 32-bit PCI address limit?

The updated size is 4GB (1 0x00000000) and the PCI base address is left at
0x10000000. This creates a PCI address range from 0x10000000 to 0x10FFFFFFF
which requires 33 bits.

The ranges entry continues to use the 0x82000000 flag, which designates a
strict 32-bit non-prefetchable memory space, causing the PCI core to
truncate the window.

Additionally, does this unintentionally alter the CPU-to-PCI translation
offset?

Originally, CPU 0x9_10000000 mapped to PCI 0x10000000 (a translation offset
of 0x9_00000000). Now, CPU 0x9_00000000 maps to PCI 0x10000000 (a translation
offset of 0x8_F0000000).

Could the PCI base address be changed to 0x0 0x00000000 to restore the
original mapping offset and stay within 32 bits, or should the flag be
updated to 0x83000000 to declare a 64-bit PCI space?

[ ... ]

> @@ -2015,7 +2015,7 @@ pcie1: pcie@4c380000 {
>  			      <0 0x4c3c0000 0 0x4000>;
>  			reg-names = "dbi", "config", "atu", "app";
>  			ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>,
> -				 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>;
> +				 <0x82000000 0 0x10000000 0xa 0x00000000 1 0x00000000>;

Is the same 32-bit overflow and translation offset change occurring for pcie1
here?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260511030751.3717935-1-hongxing.zhu@nxp.com?part=1