Re: [PATCH 1/2] dt-bindings: display: verisilicon,dc: generalize for DCUltra Lite variant

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] Relaxing base schema constraints without preserving them for existing hardware breaks validation for `thead,th1520-dc8200`.
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commit 381b44c205709ac6503cee93b907e15828645951
Author: Joey Lu <a0987203069@gmail.com>

dt-bindings: display: verisilicon,dc: generalize for DCUltra Lite variant

Extend the verisilicon,dc base schema to accommodate the Nuvoton MA35D1
DCUltra Lite variant by relaxing several constraints including clocks,
resets, ports, and additionalProperties. Add a dedicated sub-schema for
the Nuvoton variant.

> diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> index 9dc35ab973f20..00884529f8c1c 100644
> --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml
> +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml

[ ... ]

>  properties:
>    $nodename:
>      pattern: "^display@[0-9a-f]+$"
>  
>    compatible:
> -    items:
> -      - enum:
> -          - thead,th1520-dc8200
> -      - const: verisilicon,dc # DC IPs have discoverable ID/revision registers
> +    # Enumerated in full so the schema validator can verify any compatible
> +    # string against this list, including those from child schemas.
> +    contains:
> +      enum:
> +        - verisilicon,dc
> +        - thead,th1520-dc8200
> +        - nuvoton,ma35d1-dcu
>  
>    reg:
>      maxItems: 1
> @@ -26,32 +45,24 @@ properties:
>      maxItems: 1
>  
>    clocks:
> -    items:
> -      - description: DC Core clock
> -      - description: DMA AXI bus clock
> -      - description: Configuration AHB bus clock
> -      - description: Pixel clock of output 0
> -      - description: Pixel clock of output 1
> +    minItems: 2
> +    maxItems: 5

[ ... ]

> @@ -75,9 +86,8 @@ required:
>    - interrupts
>    - clocks
>    - clock-names
> -  - ports
>  
> -additionalProperties: false
> +additionalProperties: true

Does relaxing these constraints break schema validation for the existing
thead,th1520-dc8200 hardware?

Since thead,th1520-dc8200 relies directly on this base schema and does not
appear to have its own sub-schema, it seems malformed device tree nodes for
this existing hardware could now silently pass validation. 

For example, missing the verisilicon,dc fallback string, omitting the ports
node, or containing undocumented properties would no longer be caught by the
validator.

Should the legacy constraints for thead,th1520-dc8200 be preserved via an
allOf if-then conditional block in this file, or by moving the existing
hardware to its own dedicated sub-schema?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260511075142.54752-1-a0987203069@gmail.com?part=1