* [PATCH 0/4] arm64: dts: qcom: Add initial device tree support for Shikra
@ 2026-05-12 4:08 Komal Bajaj
2026-05-12 4:08 ` [PATCH 1/4] dt-bindings: arm: qcom: Document Shikra and its EVK boards Komal Bajaj
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Komal Bajaj @ 2026-05-12 4:08 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng,
Ulf Hansson
Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc,
Komal Bajaj, Imran Shaik, Krishna Kurapati, Monish Chunara,
Rakesh Kota, Raviteja Laggyshetty, Sneh Mankad, Vishnu Santhosh,
Xueyao An
Add initial device tree support for the Qualcomm Shikra SoC.
Shikra ships in a SoM form factor; this series covers the CQM variant
and its two EVK boards.
The series adds:
- dt-bindings for the CQM SoM variant and its two EVK boards
- SoC base DTSI
- CQM SoM DTSI with PM4125 PMIC regulator definitions
- EVK DTS files enabling UART, USB, and eMMC on the carrier board
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Komal Bajaj (4):
dt-bindings: arm: qcom: Document Shikra and its EVK boards
arm64: dts: qcom: Introduce Shikra SoC base dtsi
arm64: dts: qcom: Add Shikra CQM SoM platform
arm64: dts: qcom: Add Shikra CQM and CQS EVK boards
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 61 ++
arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 112 +++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 61 ++
arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 13 +
arch/arm64/boot/dts/qcom/shikra.dtsi | 966 ++++++++++++++++++++++++
7 files changed, 1222 insertions(+)
---
base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
change-id: 20260511-shikra-dt-d75d97454646
prerequisite-change-id: 20260429-shikra-pinctrl-fd71ab6ecd6f:v3
prerequisite-patch-id: d84e0b4c2788ab6cfcefc9806e7a6011eef8f91d
prerequisite-patch-id: b173720338ac515e3c89ab2c96d7b1b9ff99540a
prerequisite-change-id: 20260320-shikra_icc-b1fcef45122d:v3
prerequisite-patch-id: d36ec191324b7992a56c463a15ff09bacd8d7ba1
prerequisite-patch-id: c6edf2e05d1409667c9674b765dbd0917401a903
prerequisite-change-id: 20260429-add_pm8150_regulators-a373f53eb48f:v1
prerequisite-patch-id: b312905695c635bf1e3deab87b718c92adf07f54
prerequisite-patch-id: 390dee07914f18c7df08c57b3c59c25d1588b62f
prerequisite-change-id: 20260429-add_rpmpd_shikra-f57873b2fa7c:v1
prerequisite-patch-id: 2aab0b42cafb535b31c5154002c12f381a52be9a
prerequisite-patch-id: 491f7ab91ee90ebe98d78f7a9d706208ad74be5c
prerequisite-change-id: 20260429-shikra-gcc-rpmcc-clks-2094edfff3b0:v2
prerequisite-patch-id: 5a0fbdd458785da2d0e850c851a05046672ecadf
prerequisite-patch-id: 1f98e515a52bbeb25e2a960a804afe16c6a472a1
prerequisite-patch-id: a64476b2ba6e0f2a55928baf72ec32672ee0123c
prerequisite-patch-id: d0c8651205232862b40f942929e1efdaa3084eb3
prerequisite-change-id: 20260430-shikra_mailbox_and_rpm_changes-2de7fe8e964f:v3
prerequisite-patch-id: e80ea7940b9817449cec21afa6e9e443e007166f
prerequisite-patch-id: 2526e0507d3b5c065eafd75a657d7f903af8488f
prerequisite-patch-id: c3b7e18cd60d1f779b88ace2fae1227d3d37d83e
prerequisite-message-id: 20260504170659.282532-1-krishna.kurapati@oss.qualcomm.com
prerequisite-patch-id: 0cbcb69abbbf83da785619c266c96af624c38a87
prerequisite-patch-id: 047b2e1c1db0a5928b951a3f0bc9b0416032cb2b
prerequisite-patch-id: 6126fcda921fe53b86b3a18c649fd8ff2e1f43d8
prerequisite-patch-id: 8d1bc1ee4b4c1009a953bda66e849198d9e16352
prerequisite-message-id: 20260504145710.257211-1-krishna.kurapati@oss.qualcomm.com
prerequisite-patch-id: 2d2cba33f2dfbb05b620484e9c46eb31306fa72d
prerequisite-change-id: 20260430-shikra-smmu-binding-7befe45ecf2a:v1
prerequisite-patch-id: 657d2fa91247aa0c222b595c41328087f04f01a2
prerequisite-change-id: 20260430-shikra-imem-binding-a7bb9d2f16d2:v1
prerequisite-patch-id: 80d8ab865b7b0663c5b2878b45b55e2e4fde9c19
prerequisite-change-id: 20260501-shikra-scm-binding-a7ff5fabd0f2:v1
prerequisite-patch-id: 8e645e1c6ad6182de4813a726c293654324de1df
prerequisite-change-id: 20260501-shikra-tcsr-binding-fff1689e4097:v1
prerequisite-patch-id: f6781d2cf0829ccb32f1400623c95739972f2ee2
prerequisite-change-id: 20260501-shikra-wdog-binding-33873dcfa81f:v1
prerequisite-patch-id: de5184831054bcb48889fca16b2f4b5e95da9935
prerequisite-change-id: 20260501-shikra-qfprom-binding-c262fa19640a:v2
prerequisite-patch-id: f284f0dc01674ea0a78c8cf40ada72a7a1636463
prerequisite-change-id: 20260502-shikra-llcc-binding-7832b24ef74f:v1
prerequisite-patch-id: b9e53d2b5b494d4a957a691340fb2563f3dd681c
prerequisite-message-id: 20260508101544.736317-1-monish.chunara@oss.qualcomm.com
prerequisite-patch-id: 2a9d88175f19bfdb9495a704681ff0093da5566c
Best regards,
--
Komal Bajaj <komal.bajaj@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH 1/4] dt-bindings: arm: qcom: Document Shikra and its EVK boards 2026-05-12 4:08 [PATCH 0/4] arm64: dts: qcom: Add initial device tree support for Shikra Komal Bajaj @ 2026-05-12 4:08 ` Komal Bajaj 2026-05-12 4:08 ` [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi Komal Bajaj ` (2 subsequent siblings) 3 siblings, 0 replies; 12+ messages in thread From: Komal Bajaj @ 2026-05-12 4:08 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng, Ulf Hansson Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc, Komal Bajaj Shikra is a Qualcomm IoT SoC available in a System-on-Module (SoM) form factor. The SoM integrates the Shikra SoC, PMICs, and essential passives, and is designed to be mounted on carrier boards. One SoM variant is introduced: - CQM: retail variant with integrated modem (PM4125 PMIC) Two EVK boards are supported: - shikra-cqm-evk: pairs with the CQM SoM - shikra-cqs-evk: pairs with the CQM SoM, with no modem support Each EVK provides debug UART, USB, and other peripheral interfaces. Add compatible strings for the CQM SoM variant and its two corresponding EVK boards. Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 2741c07e9f41..f041d71d7957 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -963,6 +963,13 @@ properties: - const: qcom,qcs9100 - const: qcom,sa8775p + - items: + - enum: + - qcom,shikra-cqm-evk + - qcom,shikra-cqs-evk + - const: qcom,shikra-cqm-som + - const: qcom,shikra + - items: - enum: - google,blueline -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi 2026-05-12 4:08 [PATCH 0/4] arm64: dts: qcom: Add initial device tree support for Shikra Komal Bajaj 2026-05-12 4:08 ` [PATCH 1/4] dt-bindings: arm: qcom: Document Shikra and its EVK boards Komal Bajaj @ 2026-05-12 4:08 ` Komal Bajaj 2026-05-13 4:06 ` sashiko-bot 2026-05-12 4:08 ` [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform Komal Bajaj 2026-05-12 4:08 ` [PATCH 4/4] arm64: dts: qcom: Add Shikra CQM and CQS EVK boards Komal Bajaj 3 siblings, 1 reply; 12+ messages in thread From: Komal Bajaj @ 2026-05-12 4:08 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng, Ulf Hansson Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc, Komal Bajaj, Imran Shaik, Krishna Kurapati, Monish Chunara, Rakesh Kota, Raviteja Laggyshetty, Sneh Mankad, Vishnu Santhosh, Xueyao An Add initial device tree support for the Qualcomm Shikra SoC, an IoT-focused platform built around a heterogeneous CPU cluster (Cortex-A55 + Cortex-A78C) with RPM-based power and clock management. Enable support for the following peripherals: - CPU nodes - Global Clock Controller (GCC) - RPM-based clock controller (RPMCC) and power domains (RPMPD) - Interrupt controller - Top Level Mode Multiplexer (TLMM) - Debug UART - eMMC host controller - USB 3.0 controller with QUSB2 and QMP PHYs - System timer and watchdog Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Co-developed-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/shikra.dtsi | 966 +++++++++++++++++++++++++++++++++++ 1 file changed, 966 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi new file mode 100644 index 000000000000..262c488add1e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -0,0 +1,966 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include <dt-bindings/clock/qcom,rpmcc.h> +#include <dt-bindings/clock/qcom,shikra-gcc.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,rpm-icc.h> +#include <dt-bindings/interconnect/qcom,shikra.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&l3>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a78c"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&l2_3>; + capacity-dmips-mhz = <1946>; + dynamic-power-coefficient = <486>; + + l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&l3>; + cache-size = <0x40000>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu3>; + }; + }; + }; + + l3: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x80000>; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-shikra", "qcom,scm"; + clocks = <&rpmcc RPM_SMD_CE1_CLK>; + clock-names = "core"; + qcom,dload-mode = <&tcsr_regs 0x13000>; + #reset-cells = <1>; + interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0xa0000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rpm: remoteproc { + compatible = "qcom,shikra-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm_requests: rpm-requests { + compatible = "qcom,rpm-shikra", "qcom,glink-smd-rpm"; + qcom,glink-channels = "rpm_requests"; + + rpmcc: clock-controller { + compatible = "qcom,rpmcc-shikra", "qcom,rpmcc"; + clocks = <&xo_board>; + clock-names = "xo"; + #clock-cells = <1>; + }; + + rpmpd: power-controller { + compatible = "qcom,shikra-rpmpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmpd_opp_table>; + + rpmpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmpd_opp_min_svs: opp1 { + opp-level = <RPM_SMD_LEVEL_MIN_SVS>; + }; + + rpmpd_opp_low_svs: opp2 { + opp-level = <RPM_SMD_LEVEL_LOW_SVS>; + }; + + rpmpd_opp_svs: opp3 { + opp-level = <RPM_SMD_LEVEL_SVS>; + }; + + rpmpd_opp_svs_plus: opp4 { + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; + }; + + rpmpd_opp_nom: opp5 { + opp-level = <RPM_SMD_LEVEL_NOM>; + }; + + rpmpd_opp_nom_plus: opp6 { + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; + }; + + rpmpd_opp_turbo: opp7 { + opp-level = <RPM_SMD_LEVEL_TURBO>; + }; + + rpmpd_opp_turbo_plus: opp8 { + opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; + }; + }; + }; + }; + }; + + mpm: interrupt-controller { + compatible = "qcom,mpm"; + qcom,rpm-msg-ram = <&apss_mpm>; + interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; + mboxes = <&apcs_glb 1>; + interrupt-controller; + #interrupt-cells = <2>; + #power-domain-cells = <0>; + interrupt-parent = <&intc>; + qcom,mpm-pin-count = <96>; + qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ + <12 422>, /* DWC3 ss_phy_irq */ + <58 272>, /* QUSB2_PHY dmse_hv_vddmx */ + <59 273>, /* QUSB2_PHY dpse_hv_vddmx */ + <86 183>, /* MPM wake, SPMI */ + <90 157>, /* QUSB2_PHY DM */ + <91 158>; /* QUSB2_PHY DP */ + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg = <0x0 0x80000000 0x0 0x1600000>; + no-map; + }; + + xblboot_mem: xblboot@85e00000 { + reg = <0x0 0x85e00000 0x0 0x100000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@85fff000 { + reg = <0x0 0x85fff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@86000000 { + compatible = "qcom,smem"; + reg = <0x0 0x86000000 0x0 0x200000>; + no-map; + + hwlocks = <&tcsr_mutex 3>; + }; + + audio_heap_mem: audio-heap@86200000 { + reg = <0x0 0x86200000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat@a0000000 { + reg = <0x0 0xa0000000 0x0 0x100000>; + no-map; + }; + + qtee_mem: qtee@a1300000 { + reg = <0x0 0xa1300000 0x0 0x500000>; + no-map; + }; + + tz_apps_mem: tz-apps@a1800000 { + reg = <0x0 0xa1800000 0x0 0x2100000>; + no-map; + }; + + mpss_wlan_mem: mpss-wlan@ab000000 { + reg = <0x0 0xab000000 0x0 0x6e00000>; + no-map; + }; + + wlan_mem: wlan@b2300000 { + reg = <0x0 0xb2300000 0x0 0x100000>; + no-map; + }; + + cdsp_mem: cdsp@b2400000 { + reg = <0x0 0xb2400000 0x0 0x1900000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code@b3d00000 { + reg = <0x0 0xb3d00000 0x0 0x2000>; + no-map; + }; + + video_mem: video@b3d02000 { + reg = <0x0 0xb3d02000 0x0 0x700000>; + no-map; + }; + + lmcu_mem: lmcu@b4402000 { + reg = <0x0 0xb4402000 0x0 0x300000>; + no-map; + }; + + lmcu_dtb_mem: lmcu-dtb@b4702000 { + reg = <0x0 0xb4702000 0x0 0x40000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + + tcsr_mutex: syscon@340000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x00340000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tcsr_regs: syscon@3c0000 { + compatible = "qcom,shikra-tcsr", "syscon"; + reg = <0x0 0x003c0000 0x0 0x40000>; + }; + + tlmm: pinctrl@500000 { + compatible = "qcom,shikra-tlmm"; + reg = <0x0 0x00500000 0x0 0x700000>; + + interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 165>; + wakeup-parent = <&mpm>; + + qup_uart0_default: qup-uart0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0_se0"; + drive-strength = <2>; + bias-disable; + }; + + sdc1_state_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <6>; + bias-disable; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <6>; + bias-pull-up; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <6>; + bias-pull-up; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_state_off: sdc1-off-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <2>; + bias-bus-hold; + }; + + cmd-pins { + pins = "sdc1_cmd"; + drive-strength = <2>; + bias-bus-hold; + }; + + data-pins { + pins = "sdc1_data"; + drive-strength = <2>; + bias-bus-hold; + }; + + rclk-pins { + pins = "sdc1_rclk"; + bias-bus-hold; + }; + }; + }; + + mem_noc: interconnect@d00000 { + compatible = "qcom,shikra-mem-noc-core"; + reg = <0x0 0x00d00000 0x0 0x43080>; + clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>; + clock-names = "gpu_axi"; + #interconnect-cells = <2>; + }; + + llcc: system-cache-controller@e00000 { + compatible = "qcom,shikra-llcc"; + reg = <0x0 0x00e00000 0x0 0x80000>, + <0x0 0x00f00000 0x0 0x80000>, + <0x0 0x01000000 0x0 0x80000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc_broadcast_base"; + interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>; + }; + + gcc: clock-controller@1400000 { + compatible = "qcom,shikra-gcc"; + reg = <0x0 0x01400000 0x0 0x1f0000>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmpd RPMPD_VDDCX>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + usb_1_hsphy: phy@1613000 { + compatible = "qcom,shikra-qusb2-phy"; + reg = <0x0 0x01613000 0x0 0x180>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + nvmem-cells = <&qusb2_hstx_trim_1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_qmpphy: phy@1615000 { + compatible = "qcom,shikra-qmp-usb3-phy"; + reg = <0x0 0x01615000 0x0 0x1000>; + + clocks = <&gcc GCC_AHB2PHY_USB_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "cfg_ahb", + "ref", + "com_aux", + "pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, + <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; + reset-names = "phy", + "phy_phy"; + + #clock-cells = <0>; + clock-output-names = "usb3_phy_pipe_clk_src"; + + #phy-cells = <0>; + orientation-switch; + + qcom,tcsr-reg = <&tcsr_regs 0xb244>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + + system_noc: interconnect@1880000 { + compatible = "qcom,shikra-sys-noc"; + reg = <0x0 0x01880000 0x0 0x6a080>; + clocks = <&gcc GCC_EMAC0_AXI_SYS_NOC_CLK>, + <&gcc GCC_EMAC1_AXI_SYS_NOC_CLK>, + <&gcc GCC_SYS_NOC_USB2_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; + clock-names = "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi"; + #interconnect-cells = <2>; + + clk_virt: interconnect-clk { + compatible = "qcom,shikra-clk-virt"; + #interconnect-cells = <2>; + }; + + mc_virt: interconnect-mc { + compatible = "qcom,shikra-mc-virt"; + #interconnect-cells = <2>; + }; + + mmrt_virt: interconnect-mmrt { + compatible = "qcom,shikra-mmrt-virt"; + #interconnect-cells = <2>; + }; + + mmnrt_virt: interconnect-mmnrt { + compatible = "qcom,shikra-mmnrt-virt"; + #interconnect-cells = <2>; + }; + }; + + config_noc: interconnect@1900000 { + compatible = "qcom,shikra-config-noc"; + reg = <0x0 0x01900000 0x0 0x8080>; + #interconnect-cells = <2>; + }; + + qfprom: efuse@1b44000 { + compatible = "qcom,shikra-qfprom", "qcom,qfprom"; + reg = <0x0 0x01b44000 0x0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + qusb2_hstx_trim_1: hstx-trim@25b { + reg = <0x25b 0x1>; + bits = <1 4>; + }; + + gpu_speed_bin: gpu-speed-bin@2006 { + reg = <0x2006 0x2>; + bits = <5 8>; + }; + }; + + spmi_bus: spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0 0x01c40000 0x0 0x1100>, + <0x0 0x01e00000 0x0 0x2000000>, + <0x0 0x03e00000 0x0 0x100000>, + <0x0 0x03f00000 0x0 0xa0000>, + <0x0 0x01c0a000 0x0 0x26000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + interrupts-extended = <&mpm 86 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + qcom,channel = <0>; + qcom,ee = <0>; + }; + + rpm_msg_ram: sram@45f0000 { + compatible = "qcom,rpm-msg-ram", "mmio-sram"; + reg = <0x0 0x045f0000 0x0 0x7000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x045f0000 0x7000>; + + apss_mpm: sram@1b8 { + reg = <0x1b8 0x48>; + }; + }; + + sram@4690000 { + compatible = "qcom,rpm-stats"; + reg = <0x0 0x04690000 0x0 0x14000>; + }; + + sdhc_1: mmc@4744000 { + compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; + + reg = <0x0 0x04744000 0x0 0x1000>, + <0x0 0x04745000 0x0 0x1000>; + reg-names = "hc", + "cqhci"; + + iommus = <&apps_smmu 0xc0 0x0>; + + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmpd RPMHPD_CX>; + operating-points-v2 = <&sdhc1_opp_table>; + + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + + bus-width = <8>; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + resets = <&gcc GCC_SDCC1_BCR>; + + status = "disabled"; + + sdhc1_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_low_svs>; + opp-peak-kBps = <250000 133320>; + opp-avg-kBps = <104000 0>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + opp-peak-kBps = <800000 300000>; + opp-avg-kBps = <400000 0>; + }; + }; + }; + + qupv3_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@4a80000 { + compatible = "qcom,geni-debug-uart"; + reg = <0x0 0x04a80000 0x0 0x4000>; + + interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG + &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart0_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + usb_1: usb@4e00000 { + compatible = "qcom,shikra-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x04e00000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <133333333>; + + interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "qusb2_phy", + "hs_phy_irq", + "ss_phy_irq"; + + iommus = <&apps_smmu 0x120 0x0>; + + phys = <&usb_1_hsphy>, <&usb_qmpphy>; + phy-names = "usb2-phy", "usb3-phy"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + snps,usb3_lpm_capable; + snps,parkmode-disable-ss-quirk; + + usb-role-switch; + + wakeup-source; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_qmpphy_usb_ss_in>; + }; + }; + }; + }; + + sram@c11e000 { + compatible = "qcom,shikra-imem", "mmio-sram"; + reg = <0x0 0x0c11e000 0x0 0x1000>; + ranges = <0x0 0x0 0x0c11e000 0x1000>; + + no-memory-wc; + + #address-cells = <1>; + #size-cells = <1>; + + pil-sram@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + + apps_smmu: iommu@c600000 { + compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x0c600000 0x0 0x80000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + reg = <0x0 0xf200000 0x0 0x10000>, + <0x0 0xf240000 0x0 0x80000>; + + interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>; + + #interrupt-cells = <3>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + }; + + apcs_glb: mailbox@f400000 { + compatible = "qcom,shikra-apss-shared", "qcom,sdm845-apss-shared"; + reg = <0x0 0x0f400000 0x0 0x1000>; + #mbox-cells = <1>; + }; + + watchdog@f410000 { + compatible = "qcom,apss-wdt-shikra", "qcom,kpss-wdt"; + reg = <0x0 0x0f410000 0x0 0x1000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sleep_clk>; + }; + + timer@f420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x0f420000 0x0 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x10000000>; + + frame@f421000 { + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + frame-number = <0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + }; + + frame@f423000 { + reg = <0x0f423000 0x1000>; + frame-number = <1>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f425000 { + reg = <0x0f425000 0x1000>; + frame-number = <2>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f427000 { + reg = <0x0f427000 0x1000>; + frame-number = <3>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f429000 { + reg = <0x0f429000 0x1000>; + frame-number = <4>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f42b000 { + reg = <0x0f42b000 0x1000>; + frame-number = <5>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + frame@f42d000 { + reg = <0x0f42d000 0x1000>; + frame-number = <6>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi 2026-05-12 4:08 ` [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi Komal Bajaj @ 2026-05-13 4:06 ` sashiko-bot 0 siblings, 0 replies; 12+ messages in thread From: sashiko-bot @ 2026-05-13 4:06 UTC (permalink / raw) To: Komal Bajaj Cc: linux-phy, krzk+dt, devicetree, neil.armstrong, olteanv, conor+dt, robh, vkoul Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider: - [High] Invalid PPI interrupt numbers (1, 2, 3, 0) are specified for the ARMv8 generic timer instead of the architecturally required numbers (13, 14, 11, 10). - [Medium] The `sdhc_1` node incorrectly uses RPMh interconnect tags (`QCOM_ICC_TAG_ALWAYS`, `QCOM_ICC_TAG_ACTIVE_ONLY`) on an RPM-based interconnect topology. - [Medium] The USB SuperSpeed wakeup interrupt (`ss_phy_irq`) directly references the GIC instead of routing through the MPM, breaking system wake-up from deep sleep. - [Low] The `sdhc_1` node uses the undeclared macro `RPMHPD_CX` for its `power-domains` property, which will cause a Device Tree compiler syntax error. -- commit e2ee94ef3a5741f2cb9aae14dbef52c5f4a760f1 Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com> Subject: arm64: dts: qcom: Introduce Shikra SoC base dtsi This commit adds initial device tree support for the Qualcomm Shikra SoC, an IoT-focused platform featuring a Cortex-A55 and Cortex-A78C cluster. It configures RPM-based power and clock management alongside various peripherals like USB, eMMC, and the generic timer. > diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi > new file mode 100644 > index 0000000000000..262c488add1ec > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi [ ... ] > + sdhc_1: mmc@4744000 { > + compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5"; > + > + reg = <0x0 0x04744000 0x0 0x1000>, > + <0x0 0x04745000 0x0 0x1000>; [ ... ] > + interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, > + <&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; Since the Shikra SoC utilizes an RPM-based architecture, should this node use interconnect tags from qcom,rpm-icc.h (such as RPM_ALWAYS_TAG) instead? Passing RPMh interconnect tags from qcom,icc.h to an RPM interconnect provider might result in unhandled parameters or silent bandwidth request failures. > + interconnect-names = "sdhc-ddr", > + "cpu-sdhc"; > + > + power-domains = <&rpmpd RPMHPD_CX>; Does this power-domains assignment use an undeclared macro? RPMHPD_CX belongs to RPMh-based power domains, while this platform relies on RPMPD. This looks like it will cause a dtc syntax error during the build. [ ... ] > + usb_1: usb@4e00000 { > + compatible = "qcom,shikra-dwc3", "qcom,snps-dwc3"; > + reg = <0x0 0x04e00000 0x0 0xfc100>; [ ... ] > + interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, > + <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "dwc_usb3", > + "pwr_event", > + "qusb2_phy", > + "hs_phy_irq", > + "ss_phy_irq"; The mpm node correctly maps pin 12 to GIC SPI 422 for the DWC3 ss_phy_irq. Could routing this directly to the GIC here instead of hierarchically through the mpm (e.g., <&mpm 12 IRQ_TYPE_LEVEL_HIGH>) prevent the hardware from waking up from low-power states upon USB activity? [ ... ] > + timer { > + compatible = "arm,armv8-timer"; > + > + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, > + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; > + }; Are these PPI interrupt numbers correct for the ARMv8 generic timer? The architecturally defined numbers are typically 13 for Secure, 14 for Non-secure, 11 for Virtual, and 10 for Hypervisor. Using invalid hardware IRQ lines here could prevent the kernel from receiving scheduler ticks and stall the boot. > +}; -- Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=2 ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform 2026-05-12 4:08 [PATCH 0/4] arm64: dts: qcom: Add initial device tree support for Shikra Komal Bajaj 2026-05-12 4:08 ` [PATCH 1/4] dt-bindings: arm: qcom: Document Shikra and its EVK boards Komal Bajaj 2026-05-12 4:08 ` [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi Komal Bajaj @ 2026-05-12 4:08 ` Komal Bajaj 2026-05-13 4:28 ` sashiko-bot 2026-05-12 4:08 ` [PATCH 4/4] arm64: dts: qcom: Add Shikra CQM and CQS EVK boards Komal Bajaj 3 siblings, 1 reply; 12+ messages in thread From: Komal Bajaj @ 2026-05-12 4:08 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng, Ulf Hansson Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc, Komal Bajaj, Rakesh Kota Add device tree include for the CQM variant of the Shikra System-on-Module, a compact compute module integrating the Shikra SoC and PMIC for IoT applications, designed to mount on carrier boards. - shikra-cqm-som.dtsi: Retail SoM with modem (PM4125 PMIC) The DTSI includes the common shikra.dtsi and adds PM4125 PMIC regulator definitions specific to this variant. Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi | 112 +++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi new file mode 100644 index 000000000000..401e71720519 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include "shikra.dtsi" + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm2250-regulators"; + + pm4125_s2: s2 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pm4125_l3: l3 { + regulator-min-microvolt = <624000>; + regulator-max-microvolt = <650000>; + }; + + pm4125_l4: l4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + }; + + pm4125_l5: l5 { + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l6: l6 { + regulator-min-microvolt = <788000>; + regulator-max-microvolt = <1050000>; + }; + + pm4125_l7: l7 { + regulator-min-microvolt = <664000>; + regulator-max-microvolt = <664000>; + }; + + pm4125_l8: l8 { + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <1000000>; + }; + + pm4125_l9: l9 { + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <1000000>; + }; + + pm4125_l10: l10 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + + pm4125_l12: l12 { + regulator-min-microvolt = <928000>; + regulator-max-microvolt = <975000>; + }; + + pm4125_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm4125_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm4125_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm4125_l16: l16 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm4125_l17: l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3544000>; + }; + + pm4125_l18: l18 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + }; + + pm4125_l19: l19 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2960000>; + }; + + pm4125_l20: l20 { + regulator-min-microvolt = <2952000>; + regulator-max-microvolt = <2952000>; + }; + + pm4125_l21: l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3056000>; + }; + + pm4125_l22: l22 { + regulator-min-microvolt = <3304000>; + regulator-max-microvolt = <3304000>; + }; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform 2026-05-12 4:08 ` [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform Komal Bajaj @ 2026-05-13 4:28 ` sashiko-bot 2026-05-13 12:01 ` Dmitry Baryshkov 2026-05-13 13:31 ` Rakesh Kota 0 siblings, 2 replies; 12+ messages in thread From: sashiko-bot @ 2026-05-13 4:28 UTC (permalink / raw) To: Komal Bajaj Cc: robh, linux-phy, neil.armstrong, vkoul, olteanv, krzk+dt, conor+dt, devicetree Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy. - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125). -- commit 457abf6e7ac410430c866842e08e602ec3daaa51 Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com> arm64: dts: qcom: Add Shikra CQM SoM platform Add device tree include for the CQM variant of the Shikra System-on-Module. This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes the common shikra.dtsi and adds PM4125 PMIC regulator definitions. > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > new file mode 100644 > index 0000000000000..401e71720519d > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi [ ... ] > +&rpm_requests { > + regulators { > + compatible = "qcom,rpm-pm2250-regulators"; Since the commit message indicates this is a PM4125 PMIC, should the compatible string include a specific identifier for the actual hardware? Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside the fallback allows the kernel to apply specific quirks if PM4125 errata are discovered later. > + > + pm4125_s2: s2 { > + regulator-min-microvolt = <1000000>; > + regulator-max-microvolt = <1200000>; > + }; Do these regulators need to explicitly define their input supply dependencies such as vdd_s2-supply? Without these properties, the regulator framework might be unaware that the PMIC regulators draw power from upstream supplies. If the kernel dynamically manages the upstream supply and its reference count drops to zero, could it be disabled, causing an unexpected power loss for downstream components? [ ... ] -- Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3 ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform 2026-05-13 4:28 ` sashiko-bot @ 2026-05-13 12:01 ` Dmitry Baryshkov 2026-05-13 14:29 ` Rakesh Kota 2026-05-13 13:31 ` Rakesh Kota 1 sibling, 1 reply; 12+ messages in thread From: Dmitry Baryshkov @ 2026-05-13 12:01 UTC (permalink / raw) To: sashiko-reviews Cc: Komal Bajaj, robh, linux-phy, neil.armstrong, vkoul, olteanv, krzk+dt, conor+dt, devicetree On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy. > - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125). > -- > > commit 457abf6e7ac410430c866842e08e602ec3daaa51 > Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com> > > arm64: dts: qcom: Add Shikra CQM SoM platform > > Add device tree include for the CQM variant of the Shikra System-on-Module. > This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes > the common shikra.dtsi and adds PM4125 PMIC regulator definitions. > > > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > > new file mode 100644 > > index 0000000000000..401e71720519d > > --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > [ ... ] > > +&rpm_requests { > > + regulators { > > + compatible = "qcom,rpm-pm2250-regulators"; > > Since the commit message indicates this is a PM4125 PMIC, should the > compatible string include a specific identifier for the actual hardware? > > Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside > the fallback allows the kernel to apply specific quirks if PM4125 errata > are discovered later. This can be ignored. The compat is a leftover from the historically incorrect naming. > > > + > > + pm4125_s2: s2 { > > + regulator-min-microvolt = <1000000>; > > + regulator-max-microvolt = <1200000>; > > + }; > > Do these regulators need to explicitly define their input supply dependencies > such as vdd_s2-supply? > > Without these properties, the regulator framework might be unaware that the > PMIC regulators draw power from upstream supplies. > > If the kernel dynamically manages the upstream supply and its reference count > drops to zero, could it be disabled, causing an unexpected power loss for > downstream components? And this is a correct comment. Please provide missing supplies. > > [ ... ] > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3 -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform 2026-05-13 12:01 ` Dmitry Baryshkov @ 2026-05-13 14:29 ` Rakesh Kota 2026-05-13 15:14 ` Dmitry Baryshkov 0 siblings, 1 reply; 12+ messages in thread From: Rakesh Kota @ 2026-05-13 14:29 UTC (permalink / raw) To: Dmitry Baryshkov Cc: sashiko-reviews, Komal Bajaj, robh, linux-phy, neil.armstrong, vkoul, olteanv, krzk+dt, conor+dt, devicetree On Wed, May 13, 2026 at 03:01:47PM +0300, Dmitry Baryshkov wrote: > On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > > - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy. > > - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125). > > -- > > > > commit 457abf6e7ac410430c866842e08e602ec3daaa51 > > Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com> > > > > arm64: dts: qcom: Add Shikra CQM SoM platform > > > > Add device tree include for the CQM variant of the Shikra System-on-Module. > > This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes > > the common shikra.dtsi and adds PM4125 PMIC regulator definitions. > > > > > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > > > new file mode 100644 > > > index 0000000000000..401e71720519d > > > --- /dev/null > > > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > > [ ... ] > > > +&rpm_requests { > > > + regulators { > > > + compatible = "qcom,rpm-pm2250-regulators"; > > > > Since the commit message indicates this is a PM4125 PMIC, should the > > compatible string include a specific identifier for the actual hardware? > > > > Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside > > the fallback allows the kernel to apply specific quirks if PM4125 errata > > are discovered later. > > This can be ignored. The compat is a leftover from the historically > incorrect naming. > > > > > > + > > > + pm4125_s2: s2 { > > > + regulator-min-microvolt = <1000000>; > > > + regulator-max-microvolt = <1200000>; > > > + }; > > > > Do these regulators need to explicitly define their input supply dependencies > > such as vdd_s2-supply? > > > > Without these properties, the regulator framework might be unaware that the > > PMIC regulators draw power from upstream supplies. > > > > If the kernel dynamically manages the upstream supply and its reference count > > drops to zero, could it be disabled, causing an unexpected power loss for > > downstream components? > > And this is a correct comment. Please provide missing supplies. > As per the Qualcomm system design, the parent-child supply relationship is managed by the RPM firmware, not the Linux regulator framework. The RPM ensures the parent supply is never disabled until all subsystem votes are cleared. regards Rakesh kota > > > > [ ... ] > > > > -- > > Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3 > > -- > With best wishes > Dmitry > > -- > linux-phy mailing list > linux-phy@lists.infradead.org > https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform 2026-05-13 14:29 ` Rakesh Kota @ 2026-05-13 15:14 ` Dmitry Baryshkov 0 siblings, 0 replies; 12+ messages in thread From: Dmitry Baryshkov @ 2026-05-13 15:14 UTC (permalink / raw) To: Rakesh Kota, linux-arm-msm Cc: sashiko-reviews, Komal Bajaj, robh, linux-phy, neil.armstrong, vkoul, olteanv, krzk+dt, conor+dt, devicetree On 13/05/2026 17:29, Rakesh Kota wrote: > On Wed, May 13, 2026 at 03:01:47PM +0300, Dmitry Baryshkov wrote: >> On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote: >>> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: >>> - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy. >>> - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125). >>> -- >>> >>> commit 457abf6e7ac410430c866842e08e602ec3daaa51 >>> Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com> >>> >>> arm64: dts: qcom: Add Shikra CQM SoM platform >>> >>> Add device tree include for the CQM variant of the Shikra System-on-Module. >>> This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes >>> the common shikra.dtsi and adds PM4125 PMIC regulator definitions. >>> >>>> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi >>>> new file mode 100644 >>>> index 0000000000000..401e71720519d >>>> --- /dev/null >>>> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi >>> [ ... ] >>>> +&rpm_requests { >>>> + regulators { >>>> + compatible = "qcom,rpm-pm2250-regulators"; >>> >>> Since the commit message indicates this is a PM4125 PMIC, should the >>> compatible string include a specific identifier for the actual hardware? >>> >>> Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside >>> the fallback allows the kernel to apply specific quirks if PM4125 errata >>> are discovered later. >> >> This can be ignored. The compat is a leftover from the historically >> incorrect naming. >> >>> >>>> + >>>> + pm4125_s2: s2 { >>>> + regulator-min-microvolt = <1000000>; >>>> + regulator-max-microvolt = <1200000>; >>>> + }; >>> >>> Do these regulators need to explicitly define their input supply dependencies >>> such as vdd_s2-supply? >>> >>> Without these properties, the regulator framework might be unaware that the >>> PMIC regulators draw power from upstream supplies. >>> >>> If the kernel dynamically manages the upstream supply and its reference count >>> drops to zero, could it be disabled, causing an unexpected power loss for >>> downstream components? >> >> And this is a correct comment. Please provide missing supplies. >> > As per the Qualcomm system design, the parent-child supply relationship > is managed by the RPM firmware, not the Linux regulator framework. The > RPM ensures the parent supply is never disabled until all subsystem > votes are cleared. How is this different from other, previous platforms? -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform 2026-05-13 4:28 ` sashiko-bot 2026-05-13 12:01 ` Dmitry Baryshkov @ 2026-05-13 13:31 ` Rakesh Kota 1 sibling, 0 replies; 12+ messages in thread From: Rakesh Kota @ 2026-05-13 13:31 UTC (permalink / raw) To: sashiko-reviews Cc: Komal Bajaj, robh, linux-phy, neil.armstrong, vkoul, olteanv, krzk+dt, conor+dt, devicetree On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy. > - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125). > -- > > commit 457abf6e7ac410430c866842e08e602ec3daaa51 > Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com> > > arm64: dts: qcom: Add Shikra CQM SoM platform > > Add device tree include for the CQM variant of the Shikra System-on-Module. > This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes > the common shikra.dtsi and adds PM4125 PMIC regulator definitions. > > > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > > new file mode 100644 > > index 0000000000000..401e71720519d > > --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > [ ... ] > > +&rpm_requests { > > + regulators { > > + compatible = "qcom,rpm-pm2250-regulators"; > > Since the commit message indicates this is a PM4125 PMIC, should the > compatible string include a specific identifier for the actual hardware? > > Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside > the fallback allows the kernel to apply specific quirks if PM4125 errata > are discovered later. > PM2250 and PM4125 share identical regulator hardware with no functional differences. Therefore, using qcom,rpm-pm2250-regulators as the compatible string is sufficient i think. > > + > > + pm4125_s2: s2 { > > + regulator-min-microvolt = <1000000>; > > + regulator-max-microvolt = <1200000>; > > + }; > > Do these regulators need to explicitly define their input supply dependencies > such as vdd_s2-supply? > > Without these properties, the regulator framework might be unaware that the > PMIC regulators draw power from upstream supplies. > > If the kernel dynamically manages the upstream supply and its reference count > drops to zero, could it be disabled, causing an unexpected power loss for > downstream components? > As per the Qualcomm system design, the parent-child supply relationships for these regulators are managed by the AOP (Always-On Processor) FW. regards Rakesh Kota > [ ... ] > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3 > > -- > linux-phy mailing list > linux-phy@lists.infradead.org > https://lists.infradead.org/mailman/listinfo/linux-phy On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote: > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy. > - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125). > -- > > commit 457abf6e7ac410430c866842e08e602ec3daaa51 > Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com> > > arm64: dts: qcom: Add Shikra CQM SoM platform > > Add device tree include for the CQM variant of the Shikra System-on-Module. > This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes > the common shikra.dtsi and adds PM4125 PMIC regulator definitions. > > > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > > new file mode 100644 > > index 0000000000000..401e71720519d > > --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi > [ ... ] > > +&rpm_requests { > > + regulators { > > + compatible = "qcom,rpm-pm2250-regulators"; > > Since the commit message indicates this is a PM4125 PMIC, should the > compatible string include a specific identifier for the actual hardware? > > Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside > the fallback allows the kernel to apply specific quirks if PM4125 errata > are discovered later. > PM2250 and PM4125 share identical regulator hardware with no functional differences. Therefore, using qcom,rpm-pm2250-regulators as the compatible string is sufficient i think. > > + > > + pm4125_s2: s2 { > > + regulator-min-microvolt = <1000000>; > > + regulator-max-microvolt = <1200000>; > > + }; > > Do these regulators need to explicitly define their input supply dependencies > such as vdd_s2-supply? > > Without these properties, the regulator framework might be unaware that the > PMIC regulators draw power from upstream supplies. > > If the kernel dynamically manages the upstream supply and its reference count > drops to zero, could it be disabled, causing an unexpected power loss for > downstream components? > As per the Qualcomm system design, the parent-child supply relationships for these regulators are managed by the AOP (Always-On Processor) FW. regards Rakesh Kota > [ ... ] > > -- > Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3 > > -- > linux-phy mailing list > linux-phy@lists.infradead.org > https://lists.infradead.org/mailman/listinfo/linux-phy ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 4/4] arm64: dts: qcom: Add Shikra CQM and CQS EVK boards 2026-05-12 4:08 [PATCH 0/4] arm64: dts: qcom: Add initial device tree support for Shikra Komal Bajaj ` (2 preceding siblings ...) 2026-05-12 4:08 ` [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform Komal Bajaj @ 2026-05-12 4:08 ` Komal Bajaj 2026-05-13 12:04 ` Dmitry Baryshkov 3 siblings, 1 reply; 12+ messages in thread From: Komal Bajaj @ 2026-05-12 4:08 UTC (permalink / raw) To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng, Ulf Hansson Cc: linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc, Komal Bajaj, Imran Shaik, Krishna Kurapati, Monish Chunara, Rakesh Kota, Raviteja Laggyshetty, Sneh Mankad, Vishnu Santhosh, Xueyao An Add device trees for the Shikra EVK platform, which combines the CQM SoM variant with a common carrier board. Two EVK boards are introduced: - shikra-cqm-evk.dts: pairs with CQM SoM (retail, with modem) - shikra-cqs-evk.dts: pairs with CQM SoM (retail, board has no modem support) Also add shikra-evk.dtsi common across both EVK boards. Each board DTS enables USB (peripheral mode) with the appropriate PMIC regulator supplies for the QUSB2 and QMP PHYs, and eMMC with the correct vmmc/vqmmc supplies for the CQM SoM's PMIC. Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> Co-developed-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> --- arch/arm64/boot/dts/qcom/Makefile | 2 + arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 61 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 61 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 13 ++++++ 4 files changed, 137 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index cc42829f92eb..6de783bcd133 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -328,6 +328,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-huawei-matebook-e-2019.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts new file mode 100644 index 000000000000..12eeca84832c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-cqm-som.dtsi" +#include "shikra-evk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shikra CQM EVK"; + compatible = "qcom,shikra-cqm-evk", "qcom,shikra-cqm-som", "qcom,shikra"; + chassis-type = "embedded"; + + aliases { + mmc0 = &sdhc_1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + vdda-phy-dpdm-supply = <&pm4125_l21>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l8>; + vdda-pll-supply = <&pm4125_l13>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts new file mode 100644 index 000000000000..bc93282f64cf --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "shikra-cqm-som.dtsi" +#include "shikra-evk.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shikra CQS EVK"; + compatible = "qcom,shikra-cqs-evk", "qcom,shikra-cqm-som", "qcom,shikra"; + chassis-type = "embedded"; + + aliases { + mmc0 = &sdhc_1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm4125_l20>; + vqmmc-supply = <&pm4125_l14>; + + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + + non-removable; + supports-cqe; + no-sdio; + no-sd; + + status = "okay"; +}; + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_1_hsphy { + vdd-supply = <&pm4125_l12>; + vdda-pll-supply = <&pm4125_l13>; + vdda-phy-dpdm-supply = <&pm4125_l21>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&pm4125_l8>; + vdda-pll-supply = <&pm4125_l13>; + + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi new file mode 100644 index 000000000000..fae8c75b68b3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +&qupv3_0 { + firmware-name = "qcom/shikra/qupv3fw.elf"; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH 4/4] arm64: dts: qcom: Add Shikra CQM and CQS EVK boards 2026-05-12 4:08 ` [PATCH 4/4] arm64: dts: qcom: Add Shikra CQM and CQS EVK boards Komal Bajaj @ 2026-05-13 12:04 ` Dmitry Baryshkov 0 siblings, 0 replies; 12+ messages in thread From: Dmitry Baryshkov @ 2026-05-13 12:04 UTC (permalink / raw) To: Komal Bajaj Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng, Ulf Hansson, linux-arm-msm, devicetree, linux-kernel, linux-phy, linux-mmc, Imran Shaik, Krishna Kurapati, Monish Chunara, Rakesh Kota, Raviteja Laggyshetty, Sneh Mankad, Vishnu Santhosh, Xueyao An On Tue, May 12, 2026 at 09:38:07AM +0530, Komal Bajaj wrote: > Add device trees for the Shikra EVK platform, which combines the CQM > SoM variant with a common carrier board. > > Two EVK boards are introduced: > - shikra-cqm-evk.dts: pairs with CQM SoM (retail, with modem) > - shikra-cqs-evk.dts: pairs with CQM SoM (retail, board has no modem CQS > support) > > Also add shikra-evk.dtsi common across both EVK boards. What is the split between shikra-cq[ms]-evk.dts and shikra-evk.dtsi? > > Each board DTS enables USB (peripheral mode) with the appropriate PMIC > regulator supplies for the QUSB2 and QMP PHYs, and eMMC with the > correct vmmc/vqmmc supplies for the CQM SoM's PMIC. > > Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com> > Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com> > Co-developed-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> > Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com> > Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com> > Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com> > Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> > Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com> > Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> > Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> > Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> > Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com> > Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> > Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com> > Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com> > Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com> > Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com> > --- > arch/arm64/boot/dts/qcom/Makefile | 2 + > arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 61 +++++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 61 +++++++++++++++++++++++++++++ > arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 13 ++++++ > 4 files changed, 137 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index cc42829f92eb..6de783bcd133 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -328,6 +328,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm850-huawei-matebook-e-2019.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb > dtb-$(CONFIG_ARCH_QCOM) += sdx75-idp.dtb > +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqm-evk.dtb > +dtb-$(CONFIG_ARCH_QCOM) += shikra-cqs-evk.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm4250-oneplus-billie2.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm4450-qrd.dtb > dtb-$(CONFIG_ARCH_QCOM) += sm6115-fxtec-pro1x.dtb > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts > new file mode 100644 > index 000000000000..12eeca84832c > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts > @@ -0,0 +1,61 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +/dts-v1/; > + > +#include "shikra-cqm-som.dtsi" > +#include "shikra-evk.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. Shikra CQM EVK"; > + compatible = "qcom,shikra-cqm-evk", "qcom,shikra-cqm-som", "qcom,shikra"; > + chassis-type = "embedded"; > + > + aliases { > + mmc0 = &sdhc_1; > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&sdhc_1 { > + vmmc-supply = <&pm4125_l20>; > + vqmmc-supply = <&pm4125_l14>; > + > + pinctrl-0 = <&sdc1_state_on>; > + pinctrl-1 = <&sdc1_state_off>; > + pinctrl-names = "default", "sleep"; > + > + non-removable; > + supports-cqe; > + no-sdio; > + no-sd; > + > + status = "okay"; > +}; > + > +&usb_1 { > + dr_mode = "peripheral"; > + > + status = "okay"; > +}; > + > +&usb_1_hsphy { > + vdd-supply = <&pm4125_l12>; > + vdda-pll-supply = <&pm4125_l13>; > + vdda-phy-dpdm-supply = <&pm4125_l21>; > + > + status = "okay"; > +}; > + > +&usb_qmpphy { > + vdda-phy-supply = <&pm4125_l8>; > + vdda-pll-supply = <&pm4125_l13>; > + > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts > new file mode 100644 > index 000000000000..bc93282f64cf > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts > @@ -0,0 +1,61 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +/dts-v1/; > + > +#include "shikra-cqm-som.dtsi" > +#include "shikra-evk.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. Shikra CQS EVK"; > + compatible = "qcom,shikra-cqs-evk", "qcom,shikra-cqm-som", "qcom,shikra"; > + chassis-type = "embedded"; > + > + aliases { > + mmc0 = &sdhc_1; > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&sdhc_1 { > + vmmc-supply = <&pm4125_l20>; > + vqmmc-supply = <&pm4125_l14>; > + > + pinctrl-0 = <&sdc1_state_on>; > + pinctrl-1 = <&sdc1_state_off>; > + pinctrl-names = "default", "sleep"; > + > + non-removable; > + supports-cqe; > + no-sdio; > + no-sd; > + > + status = "okay"; > +}; > + > +&usb_1 { > + dr_mode = "peripheral"; > + > + status = "okay"; > +}; > + > +&usb_1_hsphy { > + vdd-supply = <&pm4125_l12>; > + vdda-pll-supply = <&pm4125_l13>; > + vdda-phy-dpdm-supply = <&pm4125_l21>; > + > + status = "okay"; > +}; > + > +&usb_qmpphy { > + vdda-phy-supply = <&pm4125_l8>; > + vdda-pll-supply = <&pm4125_l13>; > + > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi > new file mode 100644 > index 000000000000..fae8c75b68b3 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi > @@ -0,0 +1,13 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +&qupv3_0 { > + firmware-name = "qcom/shikra/qupv3fw.elf"; > + status = "okay"; > +}; > + > +&uart0 { > + status = "okay"; > +}; > > -- > 2.34.1 > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2026-05-13 15:14 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-05-12 4:08 [PATCH 0/4] arm64: dts: qcom: Add initial device tree support for Shikra Komal Bajaj 2026-05-12 4:08 ` [PATCH 1/4] dt-bindings: arm: qcom: Document Shikra and its EVK boards Komal Bajaj 2026-05-12 4:08 ` [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi Komal Bajaj 2026-05-13 4:06 ` sashiko-bot 2026-05-12 4:08 ` [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform Komal Bajaj 2026-05-13 4:28 ` sashiko-bot 2026-05-13 12:01 ` Dmitry Baryshkov 2026-05-13 14:29 ` Rakesh Kota 2026-05-13 15:14 ` Dmitry Baryshkov 2026-05-13 13:31 ` Rakesh Kota 2026-05-12 4:08 ` [PATCH 4/4] arm64: dts: qcom: Add Shikra CQM and CQS EVK boards Komal Bajaj 2026-05-13 12:04 ` Dmitry Baryshkov
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